1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
15 #define LLVM_TARGET_SYSTEMZINSTRINFO_H
18 #include "SystemZRegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
21 #define GET_INSTRINFO_HEADER
22 #include "SystemZGenInstrInfo.inc"
26 class SystemZTargetMachine;
30 // See comments in SystemZInstrFormats.td.
31 SimpleBDXLoad = (1 << 0),
32 SimpleBDXStore = (1 << 1),
33 Has20BitOffset = (1 << 2),
36 AccessSizeMask = (31 << 5),
38 CCValuesMask = (15 << 10),
40 CompareZeroCCMaskMask = (15 << 14),
41 CompareZeroCCMaskShift = 14,
42 CCMaskFirst = (1 << 18),
43 CCMaskLast = (1 << 19),
46 static inline unsigned getAccessSize(unsigned int Flags) {
47 return (Flags & AccessSizeMask) >> AccessSizeShift;
49 static inline unsigned getCCValues(unsigned int Flags) {
50 return (Flags & CCValuesMask) >> CCValuesShift;
52 static inline unsigned getCompareZeroCCMask(unsigned int Flags) {
53 return (Flags & CompareZeroCCMaskMask) >> CompareZeroCCMaskShift;
56 // SystemZ MachineOperand target flags.
58 // Masks out the bits for the access model.
59 MO_SYMBOL_MODIFIER = (1 << 0),
64 // Classifies a branch.
66 // An instruction that branches on the current value of CC.
69 // An instruction that peforms a 32-bit signed comparison and branches
73 // An instruction that peforms a 32-bit unsigned comparison and branches
77 // An instruction that peforms a 64-bit signed comparison and branches
81 // An instruction that peforms a 64-bit unsigned comparison and branches
85 // An instruction that decrements a 32-bit register and branches if
86 // the result is nonzero.
89 // An instruction that decrements a 64-bit register and branches if
90 // the result is nonzero.
93 // Information about a branch instruction.
95 // The type of the branch.
98 // CCMASK_<N> is set if CC might be equal to N.
101 // CCMASK_<N> is set if the branch should be taken when CC == N.
104 // The target of the branch.
105 const MachineOperand *Target;
107 Branch(BranchType type, unsigned ccValid, unsigned ccMask,
108 const MachineOperand *target)
109 : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
113 class SystemZInstrInfo : public SystemZGenInstrInfo {
114 const SystemZRegisterInfo RI;
115 SystemZTargetMachine &TM;
117 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
118 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
119 void expandRIPseudo(MachineInstr *MI, unsigned LowOpcode,
120 unsigned HighOpcode, bool ConvertHigh) const;
121 void expandRIEPseudo(MachineInstr *MI, unsigned LowOpcode,
122 unsigned LowOpcodeK, unsigned HighOpcode) const;
123 void expandRXYPseudo(MachineInstr *MI, unsigned LowOpcode,
124 unsigned HighOpcode) const;
125 void expandZExtPseudo(MachineInstr *MI, unsigned LowOpcode,
126 unsigned Size) const;
127 void emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
128 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
129 unsigned LowLowOpcode, unsigned Size, bool KillSrc) const;
130 virtual void anchor();
133 explicit SystemZInstrInfo(SystemZTargetMachine &TM);
135 // Override TargetInstrInfo.
136 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
137 int &FrameIndex) const override;
138 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
139 int &FrameIndex) const override;
140 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
141 int &SrcFrameIndex) const override;
142 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
143 MachineBasicBlock *&TBB,
144 MachineBasicBlock *&FBB,
145 SmallVectorImpl<MachineOperand> &Cond,
146 bool AllowModify) const override;
147 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
148 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
149 MachineBasicBlock *FBB,
150 const SmallVectorImpl<MachineOperand> &Cond,
151 DebugLoc DL) const override;
152 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
153 unsigned &SrcReg2, int &Mask, int &Value) const override;
154 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
155 unsigned SrcReg2, int Mask, int Value,
156 const MachineRegisterInfo *MRI) const override;
157 virtual bool isPredicable(MachineInstr *MI) const override;
159 isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
160 unsigned ExtraPredCycles,
161 const BranchProbability &Probability) const override;
163 isProfitableToIfCvt(MachineBasicBlock &TMBB,
165 unsigned ExtraPredCyclesT,
166 MachineBasicBlock &FMBB,
168 unsigned ExtraPredCyclesF,
169 const BranchProbability &Probability) const override;
171 PredicateInstruction(MachineInstr *MI,
172 const SmallVectorImpl<MachineOperand> &Pred) const override;
173 virtual void copyPhysReg(MachineBasicBlock &MBB,
174 MachineBasicBlock::iterator MBBI, DebugLoc DL,
175 unsigned DestReg, unsigned SrcReg,
176 bool KillSrc) const override;
178 storeRegToStackSlot(MachineBasicBlock &MBB,
179 MachineBasicBlock::iterator MBBI,
180 unsigned SrcReg, bool isKill, int FrameIndex,
181 const TargetRegisterClass *RC,
182 const TargetRegisterInfo *TRI) const override;
184 loadRegFromStackSlot(MachineBasicBlock &MBB,
185 MachineBasicBlock::iterator MBBI,
186 unsigned DestReg, int FrameIdx,
187 const TargetRegisterClass *RC,
188 const TargetRegisterInfo *TRI) const override;
189 virtual MachineInstr *
190 convertToThreeAddress(MachineFunction::iterator &MFI,
191 MachineBasicBlock::iterator &MBBI,
192 LiveVariables *LV) const;
193 virtual MachineInstr *
194 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
195 const SmallVectorImpl<unsigned> &Ops,
196 int FrameIndex) const;
197 virtual MachineInstr *
198 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
199 const SmallVectorImpl<unsigned> &Ops,
200 MachineInstr* LoadMI) const;
202 expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const override;
204 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
206 // Return the SystemZRegisterInfo, which this class owns.
207 const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
209 // Return the size in bytes of MI.
210 uint64_t getInstSizeInBytes(const MachineInstr *MI) const;
212 // Return true if MI is a conditional or unconditional branch.
213 // When returning true, set Cond to the mask of condition-code
214 // values on which the instruction will branch, and set Target
215 // to the operand that contains the branch target. This target
216 // can be a register or a basic block.
217 SystemZII::Branch getBranchInfo(const MachineInstr *MI) const;
219 // Get the load and store opcodes for a given register class.
220 void getLoadStoreOpcodes(const TargetRegisterClass *RC,
221 unsigned &LoadOpcode, unsigned &StoreOpcode) const;
223 // Opcode is the opcode of an instruction that has an address operand,
224 // and the caller wants to perform that instruction's operation on an
225 // address that has displacement Offset. Return the opcode of a suitable
226 // instruction (which might be Opcode itself) or 0 if no such instruction
228 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
230 // If Opcode is a load instruction that has a LOAD AND TEST form,
231 // return the opcode for the testing form, otherwise return 0.
232 unsigned getLoadAndTest(unsigned Opcode) const;
234 // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
235 // Mask of the R2 operand, given that only the low BitSize bits of Mask are
236 // significant. Set Start and End to the I3 and I4 operands if so.
237 bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
238 unsigned &Start, unsigned &End) const;
240 // If Opcode is a COMPARE opcode for which an associated COMPARE AND
241 // BRANCH exists, return the opcode for the latter, otherwise return 0.
242 // MI, if nonnull, is the compare instruction.
243 unsigned getCompareAndBranch(unsigned Opcode,
244 const MachineInstr *MI = 0) const;
246 // Emit code before MBBI in MI to move immediate value Value into
247 // physical register Reg.
248 void loadImmediate(MachineBasicBlock &MBB,
249 MachineBasicBlock::iterator MBBI,
250 unsigned Reg, uint64_t Value) const;
252 } // end namespace llvm