1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
15 #define LLVM_TARGET_SYSTEMZINSTRINFO_H
18 #include "SystemZRegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
21 #define GET_INSTRINFO_HEADER
22 #include "SystemZGenInstrInfo.inc"
26 class SystemZTargetMachine;
30 // See comments in SystemZInstrFormats.td.
31 SimpleBDXLoad = (1 << 0),
32 SimpleBDXStore = (1 << 1),
33 Has20BitOffset = (1 << 2),
37 // SystemZ MachineOperand target flags.
39 // Masks out the bits for the access model.
40 MO_SYMBOL_MODIFIER = (1 << 0),
45 // Classifies a branch.
47 // An instruction that branches on the current value of CC.
50 // An instruction that peforms a 32-bit signed comparison and branches
54 // An instruction that peforms a 64-bit signed comparison and branches
58 // Information about a branch instruction.
60 // The type of the branch.
63 // CCMASK_<N> is set if the branch should be taken when CC == N.
66 // The target of the branch.
67 const MachineOperand *Target;
69 Branch(BranchType type, unsigned ccMask, const MachineOperand *target)
70 : Type(type), CCMask(ccMask), Target(target) {}
74 class SystemZInstrInfo : public SystemZGenInstrInfo {
75 const SystemZRegisterInfo RI;
77 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
78 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
81 explicit SystemZInstrInfo(SystemZTargetMachine &TM);
83 // Override TargetInstrInfo.
84 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
85 int &FrameIndex) const LLVM_OVERRIDE;
86 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
87 int &FrameIndex) const LLVM_OVERRIDE;
88 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
89 MachineBasicBlock *&TBB,
90 MachineBasicBlock *&FBB,
91 SmallVectorImpl<MachineOperand> &Cond,
92 bool AllowModify) const LLVM_OVERRIDE;
93 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const LLVM_OVERRIDE;
94 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
95 MachineBasicBlock *FBB,
96 const SmallVectorImpl<MachineOperand> &Cond,
97 DebugLoc DL) const LLVM_OVERRIDE;
98 virtual void copyPhysReg(MachineBasicBlock &MBB,
99 MachineBasicBlock::iterator MBBI, DebugLoc DL,
100 unsigned DestReg, unsigned SrcReg,
101 bool KillSrc) const LLVM_OVERRIDE;
103 storeRegToStackSlot(MachineBasicBlock &MBB,
104 MachineBasicBlock::iterator MBBI,
105 unsigned SrcReg, bool isKill, int FrameIndex,
106 const TargetRegisterClass *RC,
107 const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
109 loadRegFromStackSlot(MachineBasicBlock &MBB,
110 MachineBasicBlock::iterator MBBI,
111 unsigned DestReg, int FrameIdx,
112 const TargetRegisterClass *RC,
113 const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
115 expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const LLVM_OVERRIDE;
117 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
120 // Return the SystemZRegisterInfo, which this class owns.
121 const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
123 // Return the size in bytes of MI.
124 uint64_t getInstSizeInBytes(const MachineInstr *MI) const;
126 // Return true if MI is a conditional or unconditional branch.
127 // When returning true, set Cond to the mask of condition-code
128 // values on which the instruction will branch, and set Target
129 // to the operand that contains the branch target. This target
130 // can be a register or a basic block.
131 SystemZII::Branch getBranchInfo(const MachineInstr *MI) const;
133 // Get the load and store opcodes for a given register class.
134 void getLoadStoreOpcodes(const TargetRegisterClass *RC,
135 unsigned &LoadOpcode, unsigned &StoreOpcode) const;
137 // Opcode is the opcode of an instruction that has an address operand,
138 // and the caller wants to perform that instruction's operation on an
139 // address that has displacement Offset. Return the opcode of a suitable
140 // instruction (which might be Opcode itself) or 0 if no such instruction
142 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
144 // If Opcode is a COMPARE opcode for which an associated COMPARE AND
145 // BRANCH exists, return the opcode for the latter, otherwise return 0.
146 // MI, if nonnull, is the compare instruction.
147 unsigned getCompareAndBranch(unsigned Opcode,
148 const MachineInstr *MI = 0) const;
150 // Emit code before MBBI in MI to move immediate value Value into
151 // physical register Reg.
152 void loadImmediate(MachineBasicBlock &MBB,
153 MachineBasicBlock::iterator MBBI,
154 unsigned Reg, uint64_t Value) const;
156 } // end namespace llvm