Fix fallout from 12-bit stuff landing: decide whether 20 bit displacements are needed...
[oota-llvm.git] / lib / Target / SystemZ / SystemZInstrInfo.h
1 //===- SystemZInstrInfo.h - SystemZ Instruction Information -------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
15 #define LLVM_TARGET_SYSTEMZINSTRINFO_H
16
17 #include "SystemZ.h"
18 #include "SystemZRegisterInfo.h"
19 #include "llvm/ADT/IndexedMap.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21
22 namespace llvm {
23
24 class SystemZTargetMachine;
25
26 class SystemZInstrInfo : public TargetInstrInfoImpl {
27   const SystemZRegisterInfo RI;
28   SystemZTargetMachine &TM;
29   IndexedMap<unsigned> RegSpillOffsets;
30 public:
31   explicit SystemZInstrInfo(SystemZTargetMachine &TM);
32
33   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
34   /// such, whenever a client has an instance of instruction info, it should
35   /// always be able to get register info as well (through this method).
36   ///
37   virtual const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
38
39   bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
40                     unsigned DestReg, unsigned SrcReg,
41                     const TargetRegisterClass *DestRC,
42                     const TargetRegisterClass *SrcRC) const;
43
44   bool isMoveInstr(const MachineInstr& MI,
45                    unsigned &SrcReg, unsigned &DstReg,
46                    unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
47
48   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
49                                    MachineBasicBlock::iterator MI,
50                                    unsigned SrcReg, bool isKill,
51                                    int FrameIndex,
52                                    const TargetRegisterClass *RC) const;
53   virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
54                                     MachineBasicBlock::iterator MI,
55                                     unsigned DestReg, int FrameIdx,
56                                     const TargetRegisterClass *RC) const;
57
58   virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
59                                          MachineBasicBlock::iterator MI,
60                                  const std::vector<CalleeSavedInfo> &CSI) const;
61   virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
62                                            MachineBasicBlock::iterator MI,
63                                  const std::vector<CalleeSavedInfo> &CSI) const;
64
65   virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
66                                 MachineBasicBlock *FBB,
67                              const SmallVectorImpl<MachineOperand> &Cond) const;
68
69   const TargetInstrDesc& getBrCond(SystemZCC::CondCodes CC) const;
70   const TargetInstrDesc& getLongDispOpc(unsigned Opc) const;
71 };
72
73 }
74
75 #endif