lib/Target/SystemZ/SystemZInstrInfo.td

   1 //===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the SystemZ instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // SystemZ Instruction Predicate Definitions.
  16 def IsZ10 : Predicate<"Subtarget.isZ10()">;
  17
  18 include "SystemZInstrFormats.td"
  19
  20 //===----------------------------------------------------------------------===//
  21 // Type Constraints.
  22 //===----------------------------------------------------------------------===//
  23 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
  24 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
  25 class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>;
  26 class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
  27
  28 //===----------------------------------------------------------------------===//
  29 // Type Profiles.
  30 //===----------------------------------------------------------------------===//
  31 def SDT_SystemZCall         : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
  32 def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
  33 def SDT_SystemZCallSeqEnd   : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
  34 def SDT_CmpTest             : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
  35 def SDT_BrCond              : SDTypeProfile<0, 3,
  36                                            [SDTCisVT<0, OtherVT>,
  37                                             SDTCisI8<1>, SDTCisVT<2, i64>]>;
  38 def SDT_SelectCC            : SDTypeProfile<1, 4,
  39                                            [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  40                                             SDTCisI8<3>, SDTCisVT<4, i64>]>;
  41 def SDT_Address             : SDTypeProfile<1, 1,
  42                                             [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
  43
  44 //===----------------------------------------------------------------------===//
  45 // SystemZ Specific Node Definitions.
  46 //===----------------------------------------------------------------------===//
  47 def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
  48                      [SDNPHasChain, SDNPOptInFlag]>;
  49 def SystemZcall    : SDNode<"SystemZISD::CALL", SDT_SystemZCall,
  50                      [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
  51 def SystemZcallseq_start :
  52                  SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart,
  53                         [SDNPHasChain, SDNPOutFlag]>;
  54 def SystemZcallseq_end :
  55                  SDNode<"ISD::CALLSEQ_END",   SDT_SystemZCallSeqEnd,
  56                         [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
  57 def SystemZcmp     : SDNode<"SystemZISD::CMP", SDT_CmpTest>;
  58 def SystemZucmp    : SDNode<"SystemZISD::UCMP", SDT_CmpTest>;
  59 def SystemZbrcond  : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
  60                             [SDNPHasChain]>;
  61 def SystemZselect  : SDNode<"SystemZISD::SELECT", SDT_SelectCC>;
  62 def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
  63
  64
  65 include "SystemZOperands.td"
  66
  67 //===----------------------------------------------------------------------===//
  68 // Instruction list..
  69
  70 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
  71                               "#ADJCALLSTACKDOWN",
  72                               [(SystemZcallseq_start timm:$amt)]>;
  73 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
  74                               "#ADJCALLSTACKUP",
  75                               [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
  76
  77 let Uses = [PSW], usesCustomInserter = 1 in {
  78   def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
  79                         "# Select32 PSEUDO",
  80                         [(set GR32:$dst,
  81                               (SystemZselect GR32:$src1, GR32:$src2, imm:$cc, PSW))]>;
  82   def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
  83                         "# Select64 PSEUDO",
  84                         [(set GR64:$dst,
  85                               (SystemZselect GR64:$src1, GR64:$src2, imm:$cc, PSW))]>;
  86 }
  87
  88
  89 //===----------------------------------------------------------------------===//
  90 //  Control Flow Instructions...
  91 //
  92
  93 // FIXME: Provide proper encoding!
  94 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
  95   def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
  96 }
  97
  98 let isBranch = 1, isTerminator = 1 in {
  99   let isBarrier = 1 in {
 100     def JMP  : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
 101
 102     let isIndirectBranch = 1 in
 103       def JMPr   : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
 104   }
 105
 106   let Uses = [PSW] in {
 107     def JO  : Pseudo<(outs), (ins brtarget:$dst),
 108                      "jo\t$dst",
 109                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_O, PSW)]>;
 110     def JH  : Pseudo<(outs), (ins brtarget:$dst),
 111                      "jh\t$dst",
 112                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H, PSW)]>;
 113     def JNLE: Pseudo<(outs), (ins brtarget:$dst),
 114                      "jnle\t$dst",
 115                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLE, PSW)]>;
 116     def JL  : Pseudo<(outs), (ins brtarget:$dst),
 117                      "jl\t$dst",
 118                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L, PSW)]>;
 119     def JNHE: Pseudo<(outs), (ins brtarget:$dst),
 120                      "jnhe\t$dst",
 121                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NHE, PSW)]>;
 122     def JLH : Pseudo<(outs), (ins brtarget:$dst),
 123                      "jlh\t$dst",
 124                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LH, PSW)]>;
 125     def JNE : Pseudo<(outs), (ins brtarget:$dst),
 126                      "jne\t$dst",
 127                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE, PSW)]>;
 128     def JE  : Pseudo<(outs), (ins brtarget:$dst),
 129                      "je\t$dst",
 130                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E, PSW)]>;
 131     def JNLH: Pseudo<(outs), (ins brtarget:$dst),
 132                      "jnlh\t$dst",
 133                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLH, PSW)]>;
 134     def JHE : Pseudo<(outs), (ins brtarget:$dst),
 135                      "jhe\t$dst",
 136                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE, PSW)]>;
 137     def JNL : Pseudo<(outs), (ins brtarget:$dst),
 138                      "jnl\t$dst",
 139                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NL, PSW)]>;
 140     def JLE : Pseudo<(outs), (ins brtarget:$dst),
 141                      "jle\t$dst",
 142                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE, PSW)]>;
 143     def JNH : Pseudo<(outs), (ins brtarget:$dst),
 144                      "jnh\t$dst",
 145                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NH, PSW)]>;
 146     def JNO : Pseudo<(outs), (ins brtarget:$dst),
 147                      "jno\t$dst",
 148                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NO, PSW)]>;
 149   } // Uses = [PSW]
 150 } // isBranch = 1
 151
 152 //===----------------------------------------------------------------------===//
 153 //  Call Instructions...
 154 //
 155
 156 let isCall = 1 in
 157   // All calls clobber the non-callee saved registers. Uses for argument
 158   // registers are added manually.
 159   let Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
 160               F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L] in {
 161     def CALLi     : Pseudo<(outs), (ins imm_pcrel:$dst, variable_ops),
 162                            "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
 163     def CALLr     : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
 164                            "basr\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>;
 165   }
 166
 167 //===----------------------------------------------------------------------===//
 168 //  Miscellaneous Instructions.
 169 //
 170
 171 let isReMaterializable = 1 in
 172 // FIXME: Provide imm12 variant
 173 // FIXME: Address should be halfword aligned...
 174 def LA64r  : RXI<0x47,
 175                  (outs GR64:$dst), (ins laaddr:$src),
 176                  "lay\t{$dst, $src}",
 177                  [(set GR64:$dst, laaddr:$src)]>;
 178 def LA64rm : RXYI<0x71E3,
 179                   (outs GR64:$dst), (ins i64imm:$src),
 180                   "larl\t{$dst, $src}",
 181                   [(set GR64:$dst,
 182                         (SystemZpcrelwrapper tglobaladdr:$src))]>;
 183
 184 let neverHasSideEffects = 1 in
 185 def NOP : Pseudo<(outs), (ins), "# no-op", []>;
 186
 187 //===----------------------------------------------------------------------===//
 188 // Move Instructions
 189
 190 let neverHasSideEffects = 1 in {
 191 def MOV32rr : RRI<0x18,
 192                   (outs GR32:$dst), (ins GR32:$src),
 193                   "lr\t{$dst, $src}",
 194                   []>;
 195 def MOV64rr : RREI<0xB904,
 196                    (outs GR64:$dst), (ins GR64:$src),
 197                    "lgr\t{$dst, $src}",
 198                    []>;
 199 def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
 200                      "# MOV128 PSEUDO!\n"
 201                      "\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 202                      "\tlgr\t${dst:subreg_even}, ${src:subreg_even}",
 203                      []>;
 204 def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
 205                      "# MOV64P PSEUDO!\n"
 206                      "\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 207                      "\tlr\t${dst:subreg_even}, ${src:subreg_even}",
 208                      []>;
 209 }
 210
 211 def MOVSX64rr32 : RREI<0xB914,
 212                        (outs GR64:$dst), (ins GR32:$src),
 213                        "lgfr\t{$dst, $src}",
 214                        [(set GR64:$dst, (sext GR32:$src))]>;
 215 def MOVZX64rr32 : RREI<0xB916,
 216                        (outs GR64:$dst), (ins GR32:$src),
 217                        "llgfr\t{$dst, $src}",
 218                        [(set GR64:$dst, (zext GR32:$src))]>;
 219
 220 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 221 def MOV32ri16 : RII<0x8A7,
 222                     (outs GR32:$dst), (ins s16imm:$src),
 223                     "lhi\t{$dst, $src}",
 224                     [(set GR32:$dst, immSExt16:$src)]>;
 225 def MOV64ri16 : RII<0x9A7,
 226                     (outs GR64:$dst), (ins s16imm64:$src),
 227                     "lghi\t{$dst, $src}",
 228                     [(set GR64:$dst, immSExt16:$src)]>;
 229
 230 def MOV64rill16 : RII<0xFA5,
 231                       (outs GR64:$dst), (ins i64imm:$src),
 232                       "llill\t{$dst, $src}",
 233                       [(set GR64:$dst, i64ll16:$src)]>;
 234 def MOV64rilh16 : RII<0xEA5,
 235                       (outs GR64:$dst), (ins i64imm:$src),
 236                       "llilh\t{$dst, $src}",
 237                       [(set GR64:$dst, i64lh16:$src)]>;
 238 def MOV64rihl16 : RII<0xDA5,
 239                       (outs GR64:$dst), (ins i64imm:$src),
 240                       "llihl\t{$dst, $src}",
 241                       [(set GR64:$dst, i64hl16:$src)]>;
 242 def MOV64rihh16 : RII<0xCA5,
 243                       (outs GR64:$dst), (ins i64imm:$src),
 244                       "llihh\t{$dst, $src}",
 245                       [(set GR64:$dst, i64hh16:$src)]>;
 246
 247 def MOV64ri32 : RILI<0x1C0,
 248                      (outs GR64:$dst), (ins s32imm64:$src),
 249                      "lgfi\t{$dst, $src}",
 250                      [(set GR64:$dst, immSExt32:$src)]>;
 251 def MOV64rilo32 : RILI<0xFC0,
 252                        (outs GR64:$dst), (ins i64imm:$src),
 253                        "llilf\t{$dst, $src}",
 254                        [(set GR64:$dst, i64lo32:$src)]>;
 255 def MOV64rihi32 : RILI<0xEC0, (outs GR64:$dst), (ins i64imm:$src),
 256                        "llihf\t{$dst, $src}",
 257                        [(set GR64:$dst, i64hi32:$src)]>;
 258 }
 259
 260 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
 261 def MOV32rm  : RXI<0x58,
 262                    (outs GR32:$dst), (ins rriaddr12:$src),
 263                    "l\t{$dst, $src}",
 264                    [(set GR32:$dst, (load rriaddr12:$src))]>;
 265 def MOV32rmy : RXYI<0x58E3,
 266                     (outs GR32:$dst), (ins rriaddr:$src),
 267                     "ly\t{$dst, $src}",
 268                     [(set GR32:$dst, (load rriaddr:$src))]>;
 269 def MOV64rm  : RXYI<0x04E3,
 270                     (outs GR64:$dst), (ins rriaddr:$src),
 271                     "lg\t{$dst, $src}",
 272                     [(set GR64:$dst, (load rriaddr:$src))]>;
 273 def MOV64Prm : Pseudo<(outs GR64P:$dst), (ins rriaddr12:$src),
 274                       "# MOV64P PSEUDO!\n"
 275                       "\tl\t${dst:subreg_odd},  $src\n"
 276                       "\tl\t${dst:subreg_even}, 4+$src",
 277                       [(set GR64P:$dst, (load rriaddr12:$src))]>;
 278 def MOV64Prmy : Pseudo<(outs GR64P:$dst), (ins rriaddr:$src),
 279                        "# MOV64P PSEUDO!\n"
 280                        "\tly\t${dst:subreg_odd},  $src\n"
 281                        "\tly\t${dst:subreg_even}, 4+$src",
 282                        [(set GR64P:$dst, (load rriaddr:$src))]>;
 283 def MOV128rm : Pseudo<(outs GR128:$dst), (ins rriaddr:$src),
 284                       "# MOV128 PSEUDO!\n"
 285                       "\tlg\t${dst:subreg_odd},  $src\n"
 286                       "\tlg\t${dst:subreg_even}, 8+$src",
 287                       [(set GR128:$dst, (load rriaddr:$src))]>;
 288 }
 289
 290 def MOV32mr  : RXI<0x50,
 291                    (outs), (ins rriaddr12:$dst, GR32:$src),
 292                    "st\t{$src, $dst}",
 293                    [(store GR32:$src, rriaddr12:$dst)]>;
 294 def MOV32mry : RXYI<0x50E3,
 295                     (outs), (ins rriaddr:$dst, GR32:$src),
 296                     "sty\t{$src, $dst}",
 297                     [(store GR32:$src, rriaddr:$dst)]>;
 298 def MOV64mr  : RXYI<0x24E3,
 299                     (outs), (ins rriaddr:$dst, GR64:$src),
 300                     "stg\t{$src, $dst}",
 301                     [(store GR64:$src, rriaddr:$dst)]>;
 302 def MOV64Pmr : Pseudo<(outs), (ins rriaddr12:$dst, GR64P:$src),
 303                       "# MOV64P PSEUDO!\n"
 304                       "\tst\t${src:subreg_odd}, $dst\n"
 305                       "\tst\t${src:subreg_even}, 4+$dst",
 306                       [(store GR64P:$src, rriaddr12:$dst)]>;
 307 def MOV64Pmry : Pseudo<(outs), (ins rriaddr:$dst, GR64P:$src),
 308                        "# MOV64P PSEUDO!\n"
 309                        "\tsty\t${src:subreg_odd}, $dst\n"
 310                        "\tsty\t${src:subreg_even}, 4+$dst",
 311                        [(store GR64P:$src, rriaddr:$dst)]>;
 312 def MOV128mr : Pseudo<(outs), (ins rriaddr:$dst, GR128:$src),
 313                       "# MOV128 PSEUDO!\n"
 314                       "\tstg\t${src:subreg_odd}, $dst\n"
 315                       "\tstg\t${src:subreg_even}, 8+$dst",
 316                       [(store GR128:$src, rriaddr:$dst)]>;
 317
 318 def MOV8mi    : SII<0x92,
 319                     (outs), (ins riaddr12:$dst, i32i8imm:$src),
 320                     "mvi\t{$dst, $src}",
 321                     [(truncstorei8 (i32 i32immSExt8:$src), riaddr12:$dst)]>;
 322 def MOV8miy   : SIYI<0x52EB,
 323                      (outs), (ins riaddr:$dst, i32i8imm:$src),
 324                      "mviy\t{$dst, $src}",
 325                      [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
 326
 327 let AddedComplexity = 2 in {
 328 def MOV16mi   : SILI<0xE544,
 329                      (outs), (ins riaddr12:$dst, s16imm:$src),
 330                      "mvhhi\t{$dst, $src}",
 331                      [(truncstorei16 (i32 i32immSExt16:$src), riaddr12:$dst)]>,
 332                      Requires<[IsZ10]>;
 333 def MOV32mi16 : SILI<0xE54C,
 334                      (outs), (ins riaddr12:$dst, s32imm:$src),
 335                      "mvhi\t{$dst, $src}",
 336                      [(store (i32 immSExt16:$src), riaddr12:$dst)]>,
 337                      Requires<[IsZ10]>;
 338 def MOV64mi16 : SILI<0xE548,
 339                      (outs), (ins riaddr12:$dst, s32imm64:$src),
 340                      "mvghi\t{$dst, $src}",
 341                      [(store (i64 immSExt16:$src), riaddr12:$dst)]>,
 342                      Requires<[IsZ10]>;
 343 }
 344
 345 // sexts
 346 def MOVSX32rr8  : RREI<0xB926,
 347                        (outs GR32:$dst), (ins GR32:$src),
 348                        "lbr\t{$dst, $src}",
 349                        [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>;
 350 def MOVSX64rr8  : RREI<0xB906,
 351                        (outs GR64:$dst), (ins GR64:$src),
 352                        "lgbr\t{$dst, $src}",
 353                        [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>;
 354 def MOVSX32rr16 : RREI<0xB927,
 355                        (outs GR32:$dst), (ins GR32:$src),
 356                        "lhr\t{$dst, $src}",
 357                        [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>;
 358 def MOVSX64rr16 : RREI<0xB907,
 359                        (outs GR64:$dst), (ins GR64:$src),
 360                        "lghr\t{$dst, $src}",
 361                        [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>;
 362
 363 // extloads
 364 def MOVSX32rm8   : RXYI<0x76E3,
 365                         (outs GR32:$dst), (ins rriaddr:$src),
 366                         "lb\t{$dst, $src}",
 367                         [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
 368 def MOVSX32rm16  : RXI<0x48,
 369                        (outs GR32:$dst), (ins rriaddr12:$src),
 370                        "lh\t{$dst, $src}",
 371                        [(set GR32:$dst, (sextloadi32i16 rriaddr12:$src))]>;
 372 def MOVSX32rm16y : RXYI<0x78E3,
 373                         (outs GR32:$dst), (ins rriaddr:$src),
 374                         "lhy\t{$dst, $src}",
 375                         [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
 376 def MOVSX64rm8   : RXYI<0x77E3,
 377                         (outs GR64:$dst), (ins rriaddr:$src),
 378                         "lgb\t{$dst, $src}",
 379                         [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
 380 def MOVSX64rm16  : RXYI<0x15E3,
 381                         (outs GR64:$dst), (ins rriaddr:$src),
 382                         "lgh\t{$dst, $src}",
 383                         [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
 384 def MOVSX64rm32  : RXYI<0x14E3,
 385                         (outs GR64:$dst), (ins rriaddr:$src),
 386                         "lgf\t{$dst, $src}",
 387                         [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
 388
 389 def MOVZX32rm8  : RXYI<0x94E3,
 390                        (outs GR32:$dst), (ins rriaddr:$src),
 391                        "llc\t{$dst, $src}",
 392                        [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
 393 def MOVZX32rm16 : RXYI<0x95E3,
 394                        (outs GR32:$dst), (ins rriaddr:$src),
 395                        "llh\t{$dst, $src}",
 396                        [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
 397 def MOVZX64rm8  : RXYI<0x90E3,
 398                        (outs GR64:$dst), (ins rriaddr:$src),
 399                        "llgc\t{$dst, $src}",
 400                        [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
 401 def MOVZX64rm16 : RXYI<0x91E3,
 402                        (outs GR64:$dst), (ins rriaddr:$src),
 403                        "llgh\t{$dst, $src}",
 404                        [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
 405 def MOVZX64rm32 : RXYI<0x16E3,
 406                        (outs GR64:$dst), (ins rriaddr:$src),
 407                        "llgf\t{$dst, $src}",
 408                        [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
 409
 410 // truncstores
 411 def MOV32m8r   : RXI<0x42,
 412                      (outs), (ins rriaddr12:$dst, GR32:$src),
 413                      "stc\t{$src, $dst}",
 414                      [(truncstorei8 GR32:$src, rriaddr12:$dst)]>;
 415
 416 def MOV32m8ry  : RXYI<0x72E3,
 417                       (outs), (ins rriaddr:$dst, GR32:$src),
 418                       "stcy\t{$src, $dst}",
 419                       [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
 420
 421 def MOV32m16r  : RXI<0x40,
 422                      (outs), (ins rriaddr12:$dst, GR32:$src),
 423                      "sth\t{$src, $dst}",
 424                      [(truncstorei16 GR32:$src, rriaddr12:$dst)]>;
 425
 426 def MOV32m16ry : RXYI<0x70E3,
 427                       (outs), (ins rriaddr:$dst, GR32:$src),
 428                       "sthy\t{$src, $dst}",
 429                       [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
 430
 431 def MOV64m8r   : RXI<0x42,
 432                      (outs), (ins rriaddr12:$dst, GR64:$src),
 433                      "stc\t{$src, $dst}",
 434                      [(truncstorei8 GR64:$src, rriaddr12:$dst)]>;
 435
 436 def MOV64m8ry  : RXYI<0x72E3,
 437                       (outs), (ins rriaddr:$dst, GR64:$src),
 438                       "stcy\t{$src, $dst}",
 439                       [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
 440
 441 def MOV64m16r  : RXI<0x40,
 442                      (outs), (ins rriaddr12:$dst, GR64:$src),
 443                      "sth\t{$src, $dst}",
 444                      [(truncstorei16 GR64:$src, rriaddr12:$dst)]>;
 445
 446 def MOV64m16ry : RXYI<0x70E3,
 447                       (outs), (ins rriaddr:$dst, GR64:$src),
 448                       "sthy\t{$src, $dst}",
 449                       [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
 450
 451 def MOV64m32r  : RXI<0x50,
 452                      (outs), (ins rriaddr12:$dst, GR64:$src),
 453                      "st\t{$src, $dst}",
 454                      [(truncstorei32 GR64:$src, rriaddr12:$dst)]>;
 455
 456 def MOV64m32ry : RXYI<0x50E3,
 457                       (outs), (ins rriaddr:$dst, GR64:$src),
 458                       "sty\t{$src, $dst}",
 459                       [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
 460
 461 // multiple regs moves
 462 // FIXME: should we use multiple arg nodes?
 463 def MOV32mrm  : RSYI<0x90EB,
 464                      (outs), (ins riaddr:$dst, GR32:$from, GR32:$to),
 465                      "stmy\t{$from, $to, $dst}",
 466                      []>;
 467 def MOV64mrm  : RSYI<0x24EB,
 468                      (outs), (ins riaddr:$dst, GR64:$from, GR64:$to),
 469                      "stmg\t{$from, $to, $dst}",
 470                      []>;
 471 def MOV32rmm  : RSYI<0x90EB,
 472                      (outs GR32:$from, GR32:$to), (ins riaddr:$dst),
 473                      "lmy\t{$from, $to, $dst}",
 474                      []>;
 475 def MOV64rmm  : RSYI<0x04EB,
 476                      (outs GR64:$from, GR64:$to), (ins riaddr:$dst),
 477                      "lmg\t{$from, $to, $dst}",
 478                      []>;
 479
 480 let isReMaterializable = 1, isAsCheapAsAMove = 1, isTwoAddress = 1 in {
 481 def MOV64Pr0_even : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
 482                            "lhi\t${dst:subreg_even}, 0",
 483                            []>;
 484 def MOV128r0_even : Pseudo<(outs GR128:$dst), (ins GR128:$src),
 485                            "lghi\t${dst:subreg_even}, 0",
 486                            []>;
 487 }
 488
 489 // Byte swaps
 490 def BSWAP32rr : RREI<0xB91F,
 491                      (outs GR32:$dst), (ins GR32:$src),
 492                      "lrvr\t{$dst, $src}",
 493                      [(set GR32:$dst, (bswap GR32:$src))]>;
 494 def BSWAP64rr : RREI<0xB90F,
 495                      (outs GR64:$dst), (ins GR64:$src),
 496                      "lrvgr\t{$dst, $src}",
 497                      [(set GR64:$dst, (bswap GR64:$src))]>;
 498
 499 // FIXME: this is invalid pattern for big-endian
 500 //def BSWAP16rm : RXYI<0x1FE3, (outs GR32:$dst), (ins rriaddr:$src),
 501 //                     "lrvh\t{$dst, $src}",
 502 //                     [(set GR32:$dst, (bswap (extloadi32i16 rriaddr:$src)))]>;
 503 def BSWAP32rm : RXYI<0x1EE3, (outs GR32:$dst), (ins rriaddr:$src),
 504                      "lrv\t{$dst, $src}",
 505                      [(set GR32:$dst, (bswap (load rriaddr:$src)))]>;
 506 def BSWAP64rm : RXYI<0x0FE3, (outs GR64:$dst), (ins rriaddr:$src),
 507                      "lrvg\t{$dst, $src}",
 508                      [(set GR64:$dst, (bswap (load rriaddr:$src)))]>;
 509
 510 //def BSWAP16mr : RXYI<0xE33F, (outs), (ins rriaddr:$dst, GR32:$src),
 511 //                     "strvh\t{$src, $dst}",
 512 //                     [(truncstorei16 (bswap GR32:$src), rriaddr:$dst)]>;
 513 def BSWAP32mr : RXYI<0xE33E, (outs), (ins rriaddr:$dst, GR32:$src),
 514                      "strv\t{$src, $dst}",
 515                      [(store (bswap GR32:$src), rriaddr:$dst)]>;
 516 def BSWAP64mr : RXYI<0xE32F, (outs), (ins rriaddr:$dst, GR64:$src),
 517                      "strvg\t{$src, $dst}",
 518                      [(store (bswap GR64:$src), rriaddr:$dst)]>;
 519
 520 //===----------------------------------------------------------------------===//
 521 // Arithmetic Instructions
 522
 523 let Defs = [PSW] in {
 524 def NEG32rr : RRI<0x13,
 525                   (outs GR32:$dst), (ins GR32:$src),
 526                   "lcr\t{$dst, $src}",
 527                   [(set GR32:$dst, (ineg GR32:$src)),
 528                    (implicit PSW)]>;
 529 def NEG64rr : RREI<0xB903, (outs GR64:$dst), (ins GR64:$src),
 530                    "lcgr\t{$dst, $src}",
 531                    [(set GR64:$dst, (ineg GR64:$src)),
 532                     (implicit PSW)]>;
 533 def NEG64rr32 : RREI<0xB913, (outs GR64:$dst), (ins GR32:$src),
 534                      "lcgfr\t{$dst, $src}",
 535                      [(set GR64:$dst, (ineg (sext GR32:$src))),
 536                       (implicit PSW)]>;
 537 }
 538
 539 let isTwoAddress = 1 in {
 540
 541 let Defs = [PSW] in {
 542
 543 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
 544 def ADD32rr : RRI<0x1A, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 545                   "ar\t{$dst, $src2}",
 546                   [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 547                    (implicit PSW)]>;
 548 def ADD64rr : RREI<0xB908, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 549                    "agr\t{$dst, $src2}",
 550                    [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
 551                     (implicit PSW)]>;
 552 }
 553
 554 def ADD32rm   : RXI<0x5A, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
 555                     "a\t{$dst, $src2}",
 556                     [(set GR32:$dst, (add GR32:$src1, (load rriaddr12:$src2))),
 557                      (implicit PSW)]>;
 558 def ADD32rmy  : RXYI<0xE35A, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 559                      "ay\t{$dst, $src2}",
 560                      [(set GR32:$dst, (add GR32:$src1, (load rriaddr:$src2))),
 561                       (implicit PSW)]>;
 562 def ADD64rm   : RXYI<0xE308, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 563                      "ag\t{$dst, $src2}",
 564                      [(set GR64:$dst, (add GR64:$src1, (load rriaddr:$src2))),
 565                       (implicit PSW)]>;
 566
 567
 568 def ADD32ri16 : RII<0xA7A,
 569                     (outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 570                     "ahi\t{$dst, $src2}",
 571                     [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
 572                      (implicit PSW)]>;
 573 def ADD32ri   : RILI<0xC29,
 574                      (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 575                      "afi\t{$dst, $src2}",
 576                      [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
 577                       (implicit PSW)]>;
 578 def ADD64ri16 : RILI<0xA7B,
 579                      (outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 580                      "aghi\t{$dst, $src2}",
 581                      [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
 582                       (implicit PSW)]>;
 583 def ADD64ri32 : RILI<0xC28,
 584                      (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 585                      "agfi\t{$dst, $src2}",
 586                      [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
 587                       (implicit PSW)]>;
 588
 589 let isCommutable = 1 in { // X = ADC Y, Z  == X = ADC Z, Y
 590 def ADC32rr : RRI<0x1E, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 591                   "alr\t{$dst, $src2}",
 592                   [(set GR32:$dst, (addc GR32:$src1, GR32:$src2))]>;
 593 def ADC64rr : RREI<0xB90A, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 594                    "algr\t{$dst, $src2}",
 595                    [(set GR64:$dst, (addc GR64:$src1, GR64:$src2))]>;
 596 }
 597
 598 def ADC32ri   : RILI<0xC2B,
 599                      (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 600                      "alfi\t{$dst, $src2}",
 601                      [(set GR32:$dst, (addc GR32:$src1, imm:$src2))]>;
 602 def ADC64ri32 : RILI<0xC2A,
 603                      (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 604                      "algfi\t{$dst, $src2}",
 605                      [(set GR64:$dst, (addc GR64:$src1, immSExt32:$src2))]>;
 606
 607 let Uses = [PSW] in {
 608 def ADDE32rr : RREI<0xB998, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 609                     "alcr\t{$dst, $src2}",
 610                     [(set GR32:$dst, (adde GR32:$src1, GR32:$src2)),
 611                      (implicit PSW)]>;
 612 def ADDE64rr : RREI<0xB988, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 613                     "alcgr\t{$dst, $src2}",
 614                     [(set GR64:$dst, (adde GR64:$src1, GR64:$src2)),
 615                      (implicit PSW)]>;
 616 }
 617
 618 let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
 619 def AND32rr : RRI<0x14,
 620                   (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 621                   "nr\t{$dst, $src2}",
 622                   [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
 623 def AND64rr : RREI<0xB980,
 624                    (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 625                    "ngr\t{$dst, $src2}",
 626                    [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
 627 }
 628
 629 def AND32rm   : RXI<0x54, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
 630                     "n\t{$dst, $src2}",
 631                     [(set GR32:$dst, (and GR32:$src1, (load rriaddr12:$src2))),
 632                      (implicit PSW)]>;
 633 def AND32rmy  : RXYI<0xE354, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 634                      "ny\t{$dst, $src2}",
 635                      [(set GR32:$dst, (and GR32:$src1, (load rriaddr:$src2))),
 636                       (implicit PSW)]>;
 637 def AND64rm   : RXYI<0xE360, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 638                      "ng\t{$dst, $src2}",
 639                      [(set GR64:$dst, (and GR64:$src1, (load rriaddr:$src2))),
 640                       (implicit PSW)]>;
 641
 642 def AND32rill16 : RII<0xA57,
 643                       (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 644                       "nill\t{$dst, $src2}",
 645                       [(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>;
 646 def AND64rill16 : RII<0xA57,
 647                       (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 648                       "nill\t{$dst, $src2}",
 649                       [(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>;
 650
 651 def AND32rilh16 : RII<0xA56,
 652                       (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 653                       "nilh\t{$dst, $src2}",
 654                       [(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>;
 655 def AND64rilh16 : RII<0xA56,
 656                       (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 657                       "nilh\t{$dst, $src2}",
 658                       [(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>;
 659
 660 def AND64rihl16 : RII<0xA55,
 661                       (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 662                       "nihl\t{$dst, $src2}",
 663                       [(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>;
 664 def AND64rihh16 : RII<0xA54,
 665                       (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 666                       "nihh\t{$dst, $src2}",
 667                       [(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>;
 668
 669 def AND32ri     : RILI<0xC0B,
 670                        (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 671                        "nilf\t{$dst, $src2}",
 672                        [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
 673 def AND64rilo32 : RILI<0xC0B,
 674                        (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 675                        "nilf\t{$dst, $src2}",
 676                        [(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>;
 677 def AND64rihi32 : RILI<0xC0A,
 678                        (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 679                        "nihf\t{$dst, $src2}",
 680                        [(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>;
 681
 682 let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
 683 def OR32rr : RRI<0x16,
 684                  (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 685                  "or\t{$dst, $src2}",
 686                  [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
 687 def OR64rr : RREI<0xB981,
 688                   (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 689                   "ogr\t{$dst, $src2}",
 690                   [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
 691 }
 692
 693 def OR32rm   : RXI<0x56, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
 694                    "o\t{$dst, $src2}",
 695                    [(set GR32:$dst, (or GR32:$src1, (load rriaddr12:$src2))),
 696                     (implicit PSW)]>;
 697 def OR32rmy  : RXYI<0xE356, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 698                     "oy\t{$dst, $src2}",
 699                     [(set GR32:$dst, (or GR32:$src1, (load rriaddr:$src2))),
 700                      (implicit PSW)]>;
 701 def OR64rm   : RXYI<0xE381, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 702                     "og\t{$dst, $src2}",
 703                     [(set GR64:$dst, (or GR64:$src1, (load rriaddr:$src2))),
 704                      (implicit PSW)]>;
 705
 706  // FIXME: Provide proper encoding!
 707 def OR32ri16  : RII<0xA5B,
 708                     (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 709                     "oill\t{$dst, $src2}",
 710                     [(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>;
 711 def OR32ri16h : RII<0xA5A,
 712                     (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 713                     "oilh\t{$dst, $src2}",
 714                     [(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>;
 715 def OR32ri : RILI<0xC0D,
 716                   (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 717                   "oilf\t{$dst, $src2}",
 718                   [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
 719
 720 def OR64rill16 : RII<0xA5B,
 721                      (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 722                      "oill\t{$dst, $src2}",
 723                      [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
 724 def OR64rilh16 : RII<0xA5A,
 725                      (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 726                      "oilh\t{$dst, $src2}",
 727                      [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
 728 def OR64rihl16 : RII<0xA59,
 729                      (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 730                      "oihl\t{$dst, $src2}",
 731                      [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
 732 def OR64rihh16 : RII<0xA58,
 733                      (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 734                      "oihh\t{$dst, $src2}",
 735                      [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
 736
 737 def OR64rilo32 : RILI<0xC0D,
 738                       (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 739                       "oilf\t{$dst, $src2}",
 740                       [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
 741 def OR64rihi32 : RILI<0xC0C,
 742                       (outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 743                       "oihf\t{$dst, $src2}",
 744                       [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
 745
 746 def SUB32rr : RRI<0x1B,
 747                   (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 748                   "sr\t{$dst, $src2}",
 749                   [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
 750 def SUB64rr : RREI<0xB909,
 751                    (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 752                    "sgr\t{$dst, $src2}",
 753                    [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
 754
 755 def SUB32rm   : RXI<0x5B, (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
 756                     "s\t{$dst, $src2}",
 757                     [(set GR32:$dst, (sub GR32:$src1, (load rriaddr12:$src2))),
 758                      (implicit PSW)]>;
 759 def SUB32rmy  : RXYI<0xE35B, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 760                      "sy\t{$dst, $src2}",
 761                      [(set GR32:$dst, (sub GR32:$src1, (load rriaddr:$src2))),
 762                       (implicit PSW)]>;
 763 def SUB64rm   : RXYI<0xE309, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 764                      "sg\t{$dst, $src2}",
 765                      [(set GR64:$dst, (sub GR64:$src1, (load rriaddr:$src2))),
 766                       (implicit PSW)]>;
 767
 768 def SBC32rr : RRI<0x1F,
 769                   (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 770                   "slr\t{$dst, $src2}",
 771                   [(set GR32:$dst, (subc GR32:$src1, GR32:$src2))]>;
 772 def SBC64rr : RREI<0xB90B,
 773                    (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 774                    "slgr\t{$dst, $src2}",
 775                    [(set GR64:$dst, (subc GR64:$src1, GR64:$src2))]>;
 776
 777 def SBC32ri   : RILI<0xC25,
 778                      (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 779                      "sllfi\t{$dst, $src2}",
 780                      [(set GR32:$dst, (subc GR32:$src1, imm:$src2))]>;
 781 def SBC64ri32 : RILI<0xC24,
 782                      (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 783                      "slgfi\t{$dst, $src2}",
 784                      [(set GR64:$dst, (subc GR64:$src1, immSExt32:$src2))]>;
 785
 786 let Uses = [PSW] in {
 787 def SUBE32rr : RREI<0xB999, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 788                     "slbr\t{$dst, $src2}",
 789                     [(set GR32:$dst, (sube GR32:$src1, GR32:$src2)),
 790                      (implicit PSW)]>;
 791 def SUBE64rr : RREI<0xB989, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 792                     "slbgr\t{$dst, $src2}",
 793                     [(set GR64:$dst, (sube GR64:$src1, GR64:$src2)),
 794                      (implicit PSW)]>;
 795 }
 796
 797 let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
 798 def XOR32rr : RRI<0x17,
 799                   (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 800                   "xr\t{$dst, $src2}",
 801                   [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
 802 def XOR64rr : RREI<0xB982,
 803                    (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 804                    "xgr\t{$dst, $src2}",
 805                    [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
 806 }
 807
 808 def XOR32rm   : RXI<0x57,(outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
 809                     "x\t{$dst, $src2}",
 810                     [(set GR32:$dst, (xor GR32:$src1, (load rriaddr12:$src2))),
 811                      (implicit PSW)]>;
 812 def XOR32rmy  : RXYI<0xE357, (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 813                      "xy\t{$dst, $src2}",
 814                      [(set GR32:$dst, (xor GR32:$src1, (load rriaddr:$src2))),
 815                       (implicit PSW)]>;
 816 def XOR64rm   : RXYI<0xE382, (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 817                      "xg\t{$dst, $src2}",
 818                      [(set GR64:$dst, (xor GR64:$src1, (load rriaddr:$src2))),
 819                       (implicit PSW)]>;
 820
 821 def XOR32ri : RILI<0xC07,
 822                    (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 823                    "xilf\t{$dst, $src2}",
 824                    [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
 825
 826 } // Defs = [PSW]
 827
 828 let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
 829 def MUL32rr : RREI<0xB252,
 830                    (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 831                    "msr\t{$dst, $src2}",
 832                    [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
 833 def MUL64rr : RREI<0xB90C,
 834                    (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 835                    "msgr\t{$dst, $src2}",
 836                    [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
 837 }
 838
 839 def MUL64rrP   : RRI<0x1C,
 840                      (outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 841                      "mr\t{$dst, $src2}",
 842                      []>;
 843 def UMUL64rrP  : RREI<0xB996,
 844                       (outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 845                       "mlr\t{$dst, $src2}",
 846                       []>;
 847 def UMUL128rrP : RREI<0xB986,
 848                       (outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 849                       "mlgr\t{$dst, $src2}",
 850                       []>;
 851
 852 def MUL32ri16   : RII<0xA7C,
 853                       (outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 854                       "mhi\t{$dst, $src2}",
 855                       [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
 856 def MUL64ri16   : RII<0xA7D,
 857                       (outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 858                       "mghi\t{$dst, $src2}",
 859                       [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
 860
 861 let AddedComplexity = 2 in {
 862 def MUL32ri     : RILI<0xC21,
 863                        (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 864                        "msfi\t{$dst, $src2}",
 865                        [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>,
 866                        Requires<[IsZ10]>;
 867 def MUL64ri32   : RILI<0xC20,
 868                        (outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 869                        "msgfi\t{$dst, $src2}",
 870                        [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
 871                        Requires<[IsZ10]>;
 872 }
 873
 874 def MUL32rm : RXI<0x71,
 875                   (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
 876                   "ms\t{$dst, $src2}",
 877                   [(set GR32:$dst, (mul GR32:$src1, (load rriaddr12:$src2)))]>;
 878 def MUL32rmy : RXYI<0xE351,
 879                     (outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 880                     "msy\t{$dst, $src2}",
 881                     [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
 882 def MUL64rm  : RXYI<0xE30C,
 883                     (outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 884                     "msg\t{$dst, $src2}",
 885                     [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
 886
 887 def MULSX64rr32 : RREI<0xB91C,
 888                        (outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
 889                        "msgfr\t{$dst, $src2}",
 890                        [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
 891
 892 def SDIVREM32r : RREI<0xB91D,
 893                       (outs GR128:$dst), (ins GR128:$src1, GR32:$src2),
 894                       "dsgfr\t{$dst, $src2}",
 895                       []>;
 896 def SDIVREM64r : RREI<0xB90D,
 897                       (outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 898                       "dsgr\t{$dst, $src2}",
 899                       []>;
 900
 901 def UDIVREM32r : RREI<0xB997,
 902                       (outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 903                       "dlr\t{$dst, $src2}",
 904                       []>;
 905 def UDIVREM64r : RREI<0xB987,
 906                       (outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 907                       "dlgr\t{$dst, $src2}",
 908                       []>;
 909 let mayLoad = 1 in {
 910 def SDIVREM32m : RXYI<0xE31D,
 911                       (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
 912                       "dsgf\t{$dst, $src2}",
 913                       []>;
 914 def SDIVREM64m : RXYI<0xE30D,
 915                       (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
 916                       "dsg\t{$dst, $src2}",
 917                       []>;
 918
 919 def UDIVREM32m : RXYI<0xE397, (outs GR64P:$dst), (ins GR64P:$src1, rriaddr:$src2),
 920                       "dl\t{$dst, $src2}",
 921                       []>;
 922 def UDIVREM64m : RXYI<0xE387, (outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
 923                       "dlg\t{$dst, $src2}",
 924                       []>;
 925 } // mayLoad
 926 } // isTwoAddress = 1
 927
 928 //===----------------------------------------------------------------------===//
 929 // Shifts
 930
 931 let isTwoAddress = 1 in
 932 def SRL32rri : RSI<0x88,
 933                    (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 934                    "srl\t{$src, $amt}",
 935                    [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
 936 def SRL64rri : RSYI<0xEB0C,
 937                     (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 938                     "srlg\t{$dst, $src, $amt}",
 939                     [(set GR64:$dst, (srl GR64:$src, riaddr:$amt))]>;
 940
 941 let isTwoAddress = 1 in
 942 def SHL32rri : RSI<0x89,
 943                    (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 944                    "sll\t{$src, $amt}",
 945                    [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
 946 def SHL64rri : RSYI<0xEB0D,
 947                     (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 948                     "sllg\t{$dst, $src, $amt}",
 949                     [(set GR64:$dst, (shl GR64:$src, riaddr:$amt))]>;
 950
 951 let Defs = [PSW] in {
 952 let isTwoAddress = 1 in
 953 def SRA32rri : RSI<0x8A,
 954                    (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 955                    "sra\t{$src, $amt}",
 956                    [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
 957                     (implicit PSW)]>;
 958
 959 def SRA64rri : RSYI<0xEB0A,
 960                     (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 961                     "srag\t{$dst, $src, $amt}",
 962                     [(set GR64:$dst, (sra GR64:$src, riaddr:$amt)),
 963                      (implicit PSW)]>;
 964 } // Defs = [PSW]
 965
 966 def ROTL32rri : RSYI<0xEB1D,
 967                      (outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 968                      "rll\t{$dst, $src, $amt}",
 969                      [(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>;
 970 def ROTL64rri : RSYI<0xEB1C,
 971                      (outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 972                      "rllg\t{$dst, $src, $amt}",
 973                      [(set GR64:$dst, (rotl GR64:$src, riaddr:$amt))]>;
 974
 975 //===----------------------------------------------------------------------===//
 976 // Test instructions (like AND but do not produce any result)
 977
 978 // Integer comparisons
 979 let Defs = [PSW] in {
 980 def CMP32rr : RRI<0x19,
 981                   (outs), (ins GR32:$src1, GR32:$src2),
 982                   "cr\t$src1, $src2",
 983                   [(SystemZcmp GR32:$src1, GR32:$src2),
 984                    (implicit PSW)]>;
 985 def CMP64rr : RREI<0xB920,
 986                    (outs), (ins GR64:$src1, GR64:$src2),
 987                    "cgr\t$src1, $src2",
 988                    [(SystemZcmp GR64:$src1, GR64:$src2),
 989                     (implicit PSW)]>;
 990
 991 def CMP32ri   : RILI<0xC2D,
 992                      (outs), (ins GR32:$src1, s32imm:$src2),
 993                      "cfi\t$src1, $src2",
 994                      [(SystemZcmp GR32:$src1, imm:$src2),
 995                       (implicit PSW)]>;
 996 def CMP64ri32 : RILI<0xC2C,
 997                      (outs), (ins GR64:$src1, s32imm64:$src2),
 998                      "cgfi\t$src1, $src2",
 999                      [(SystemZcmp GR64:$src1, i64immSExt32:$src2),
1000                       (implicit PSW)]>;
1001
1002 def CMP32rm : RXI<0x59,
1003                   (outs), (ins GR32:$src1, rriaddr12:$src2),
1004                   "c\t$src1, $src2",
1005                   [(SystemZcmp GR32:$src1, (load rriaddr12:$src2)),
1006                    (implicit PSW)]>;
1007 def CMP32rmy : RXYI<0xE359,
1008                     (outs), (ins GR32:$src1, rriaddr:$src2),
1009                     "cy\t$src1, $src2",
1010                     [(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
1011                      (implicit PSW)]>;
1012 def CMP64rm  : RXYI<0xE320,
1013                     (outs), (ins GR64:$src1, rriaddr:$src2),
1014                     "cg\t$src1, $src2",
1015                     [(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
1016                      (implicit PSW)]>;
1017
1018 def UCMP32rr : RRI<0x15,
1019                    (outs), (ins GR32:$src1, GR32:$src2),
1020                    "clr\t$src1, $src2",
1021                    [(SystemZucmp GR32:$src1, GR32:$src2),
1022                     (implicit PSW)]>;
1023 def UCMP64rr : RREI<0xB921,
1024                     (outs), (ins GR64:$src1, GR64:$src2),
1025                     "clgr\t$src1, $src2",
1026                     [(SystemZucmp GR64:$src1, GR64:$src2),
1027                      (implicit PSW)]>;
1028
1029 def UCMP32ri   : RILI<0xC2F,
1030                       (outs), (ins GR32:$src1, i32imm:$src2),
1031                       "clfi\t$src1, $src2",
1032                       [(SystemZucmp GR32:$src1, imm:$src2),
1033                        (implicit PSW)]>;
1034 def UCMP64ri32 : RILI<0xC2E,
1035                       (outs), (ins GR64:$src1, i64i32imm:$src2),
1036                       "clgfi\t$src1, $src2",
1037                       [(SystemZucmp GR64:$src1, i64immZExt32:$src2),
1038                        (implicit PSW)]>;
1039
1040 def UCMP32rm  : RXI<0x55,
1041                     (outs), (ins GR32:$src1, rriaddr12:$src2),
1042                     "cl\t$src1, $src2",
1043                     [(SystemZucmp GR32:$src1, (load rriaddr12:$src2)),
1044                      (implicit PSW)]>;
1045 def UCMP32rmy : RXYI<0xE355,
1046                      (outs), (ins GR32:$src1, rriaddr:$src2),
1047                      "cly\t$src1, $src2",
1048                      [(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
1049                       (implicit PSW)]>;
1050 def UCMP64rm  : RXYI<0xE351,
1051                      (outs), (ins GR64:$src1, rriaddr:$src2),
1052                      "clg\t$src1, $src2",
1053                      [(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
1054                       (implicit PSW)]>;
1055
1056 def CMPSX64rr32  : RREI<0xB930,
1057                         (outs), (ins GR64:$src1, GR32:$src2),
1058                         "cgfr\t$src1, $src2",
1059                         [(SystemZucmp GR64:$src1, (sext GR32:$src2)),
1060                          (implicit PSW)]>;
1061 def UCMPZX64rr32 : RREI<0xB931,
1062                         (outs), (ins GR64:$src1, GR32:$src2),
1063                         "clgfr\t$src1, $src2",
1064                         [(SystemZucmp GR64:$src1, (zext GR32:$src2)),
1065                          (implicit PSW)]>;
1066
1067 def CMPSX64rm32   : RXYI<0xE330,
1068                          (outs), (ins GR64:$src1, rriaddr:$src2),
1069                          "cgf\t$src1, $src2",
1070                          [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
1071                           (implicit PSW)]>;
1072 def UCMPZX64rm32  : RXYI<0xE331,
1073                          (outs), (ins GR64:$src1, rriaddr:$src2),
1074                          "clgf\t$src1, $src2",
1075                          [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
1076                           (implicit PSW)]>;
1077
1078 // FIXME: Add other crazy ucmp forms
1079
1080 } // Defs = [PSW]
1081
1082 //===----------------------------------------------------------------------===//
1083 // Other crazy stuff
1084 let Defs = [PSW] in {
1085 def FLOGR64 : RREI<0xB983,
1086                    (outs GR128:$dst), (ins GR64:$src),
1087                    "flogr\t{$dst, $src}",
1088                    []>;
1089 } // Defs = [PSW]
1090
1091 //===----------------------------------------------------------------------===//
1092 // Non-Instruction Patterns.
1093 //===----------------------------------------------------------------------===//
1094
1095 // ConstPools, JumpTables
1096 def : Pat<(SystemZpcrelwrapper tjumptable:$src), (LA64rm tjumptable:$src)>;
1097 def : Pat<(SystemZpcrelwrapper tconstpool:$src), (LA64rm tconstpool:$src)>;
1098
1099 // anyext
1100 def : Pat<(i64 (anyext GR32:$src)),
1101           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
1102
1103 // calls
1104 def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), (CALLi tglobaladdr:$dst)>;
1105 def : Pat<(SystemZcall (i64 texternalsym:$dst)), (CALLi texternalsym:$dst)>;
1106
1107 //===----------------------------------------------------------------------===//
1108 // Peepholes.
1109 //===----------------------------------------------------------------------===//
1110
1111 // FIXME: use add/sub tricks with 32678/-32768
1112
1113 // Arbitrary immediate support.
1114 def : Pat<(i32 imm:$src),
1115           (EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;
1116
1117 // Implement in terms of LLIHF/OILF.
1118 def : Pat<(i64 imm:$imm),
1119           (OR64rilo32 (MOV64rihi32 (HI32 imm:$imm)), (LO32 imm:$imm))>;
1120
1121 // trunc patterns
1122 def : Pat<(i32 (trunc GR64:$src)),
1123           (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
1124
1125 // sext_inreg patterns
1126 def : Pat<(sext_inreg GR64:$src, i32),
1127           (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
1128
1129 // extload patterns
1130 def : Pat<(extloadi32i8  rriaddr:$src), (MOVZX32rm8  rriaddr:$src)>;
1131 def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>;
1132 def : Pat<(extloadi64i8  rriaddr:$src), (MOVZX64rm8  rriaddr:$src)>;
1133 def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
1134 def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
1135
1136 // muls
1137 def : Pat<(mulhs GR32:$src1, GR32:$src2),
1138           (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1139                                                    GR32:$src1, subreg_odd32),
1140                                     GR32:$src2),
1141                           subreg_even32)>;
1142
1143 def : Pat<(mulhu GR32:$src1, GR32:$src2),
1144           (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1145                                                     GR32:$src1, subreg_odd32),
1146                                      GR32:$src2),
1147                           subreg_even32)>;
1148 def : Pat<(mulhu GR64:$src1, GR64:$src2),
1149           (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1150                                                      GR64:$src1, subreg_odd),
1151                                       GR64:$src2),
1152                           subreg_even)>;
1153
1154 def : Pat<(ctlz GR64:$src),
1155           (EXTRACT_SUBREG (FLOGR64 GR64:$src), subreg_even)>;