lib/Target/SystemZ/SystemZInstrInfo.td

   1 //===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the SystemZ instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "SystemZInstrFormats.td"
  15
  16 //===----------------------------------------------------------------------===//
  17 // Type Constraints.
  18 //===----------------------------------------------------------------------===//
  19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
  20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
  21 class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>;
  22 class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
  23
  24 //===----------------------------------------------------------------------===//
  25 // Type Profiles.
  26 //===----------------------------------------------------------------------===//
  27 def SDT_SystemZCall         : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
  28 def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
  29 def SDT_SystemZCallSeqEnd   : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
  30 def SDT_CmpTest             : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
  31 def SDT_BrCond              : SDTypeProfile<0, 2,
  32                                            [SDTCisVT<0, OtherVT>,
  33                                             SDTCisI8<1>]>;
  34 def SDT_SelectCC            : SDTypeProfile<1, 3,
  35                                            [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  36                                             SDTCisI8<3>]>;
  37 def SDT_Address             : SDTypeProfile<1, 1,
  38                                             [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
  39
  40 //===----------------------------------------------------------------------===//
  41 // SystemZ Specific Node Definitions.
  42 //===----------------------------------------------------------------------===//
  43 def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
  44                      [SDNPHasChain, SDNPOptInFlag]>;
  45 def SystemZcall    : SDNode<"SystemZISD::CALL", SDT_SystemZCall,
  46                      [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
  47 def SystemZcallseq_start :
  48                  SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart,
  49                         [SDNPHasChain, SDNPOutFlag]>;
  50 def SystemZcallseq_end :
  51                  SDNode<"ISD::CALLSEQ_END",   SDT_SystemZCallSeqEnd,
  52                         [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
  53 def SystemZcmp     : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>;
  54 def SystemZucmp    : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>;
  55 def SystemZbrcond  : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
  56                             [SDNPHasChain, SDNPInFlag]>;
  57 def SystemZselect  : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>;
  58 def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
  59
  60 //===----------------------------------------------------------------------===//
  61 // Instruction Pattern Stuff.
  62 //===----------------------------------------------------------------------===//
  63
  64 // SystemZ specific condition code. These correspond to CondCode in
  65 // SystemZ.h. They must be kept in synch.
  66 def SYSTEMZ_COND_E  : PatLeaf<(i8 0)>;
  67 def SYSTEMZ_COND_NE : PatLeaf<(i8 1)>;
  68 def SYSTEMZ_COND_H  : PatLeaf<(i8 2)>;
  69 def SYSTEMZ_COND_L  : PatLeaf<(i8 3)>;
  70 def SYSTEMZ_COND_HE : PatLeaf<(i8 4)>;
  71 def SYSTEMZ_COND_LE : PatLeaf<(i8 5)>;
  72
  73 def LL16 : SDNodeXForm<imm, [{
  74   // Transformation function: return low 16 bits.
  75   return getI16Imm(N->getZExtValue() & 0x000000000000FFFFULL);
  76 }]>;
  77
  78 def LH16 : SDNodeXForm<imm, [{
  79   // Transformation function: return bits 16-31.
  80   return getI16Imm((N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16);
  81 }]>;
  82
  83 def HL16 : SDNodeXForm<imm, [{
  84   // Transformation function: return bits 32-47.
  85   return getI16Imm((N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32);
  86 }]>;
  87
  88 def HH16 : SDNodeXForm<imm, [{
  89   // Transformation function: return bits 48-63.
  90   return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48);
  91 }]>;
  92
  93 def LO32 : SDNodeXForm<imm, [{
  94   // Transformation function: return low 32 bits.
  95   return getI32Imm(N->getZExtValue() & 0x00000000FFFFFFFFULL);
  96 }]>;
  97
  98 def HI32 : SDNodeXForm<imm, [{
  99   // Transformation function: return bits 32-63.
 100   return getI32Imm(N->getZExtValue() >> 32);
 101 }]>;
 102
 103 def i64ll16 : PatLeaf<(imm), [{
 104   // i64ll16 predicate - true if the 64-bit immediate has only rightmost 16
 105   // bits set.
 106   return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
 107 }], LL16>;
 108
 109 def i64lh16 : PatLeaf<(imm), [{
 110   // i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set.
 111   return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
 112 }], LH16>;
 113
 114 def i64hl16 : PatLeaf<(i64 imm), [{
 115   // i64hl16 predicate - true if the 64-bit immediate has only bits 32-47 set.
 116   return ((N->getZExtValue() & 0x0000FFFF00000000ULL) == N->getZExtValue());
 117 }], HL16>;
 118
 119 def i64hh16 : PatLeaf<(i64 imm), [{
 120   // i64hh16 predicate - true if the 64-bit immediate has only bits 48-63 set.
 121   return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue());
 122 }], HH16>;
 123
 124 def immSExt16 : PatLeaf<(imm), [{
 125   // immSExt16 predicate - true if the immediate fits in a 16-bit sign extended
 126   // field.
 127   if (N->getValueType(0) == MVT::i64) {
 128     uint64_t val = N->getZExtValue();
 129     return ((int64_t)val == (int16_t)val);
 130   } else if (N->getValueType(0) == MVT::i32) {
 131     uint32_t val = N->getZExtValue();
 132     return ((int32_t)val == (int16_t)val);
 133   }
 134
 135   return false;
 136 }]>;
 137
 138 def immSExt32 : PatLeaf<(i64 imm), [{
 139   // immSExt32 predicate - true if the immediate fits in a 32-bit sign extended
 140   // field.
 141   uint64_t val = N->getZExtValue();
 142   return ((int64_t)val == (int32_t)val);
 143 }]>;
 144
 145 def i64lo32 : PatLeaf<(i64 imm), [{
 146   // i64lo32 predicate - true if the 64-bit immediate has only rightmost 32
 147   // bits set.
 148   return ((N->getZExtValue() & 0x00000000FFFFFFFFULL) == N->getZExtValue());
 149 }], LO32>;
 150
 151 def i64hi32 : PatLeaf<(i64 imm), [{
 152   // i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set.
 153   return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue());
 154 }], HI32>;
 155
 156 def i32immSExt8  : PatLeaf<(i32 imm), [{
 157   // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
 158   // sign extended field.
 159   return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
 160 }]>;
 161
 162 def i32immSExt16 : PatLeaf<(i32 imm), [{
 163   // i32immSExt16 predicate - True if the 32-bit immediate fits in a 16-bit
 164   // sign extended field.
 165   return (int32_t)N->getZExtValue() == (int16_t)N->getZExtValue();
 166 }]>;
 167
 168 def i64immSExt32 : PatLeaf<(i64 imm), [{
 169   // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
 170   // sign extended field.
 171   return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
 172 }]>;
 173
 174 def i64immZExt32 : PatLeaf<(i64 imm), [{
 175   // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
 176   // zero extended field.
 177   return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
 178 }]>;
 179
 180 // extloads
 181 def extloadi32i8   : PatFrag<(ops node:$ptr), (i32 (extloadi8  node:$ptr))>;
 182 def extloadi32i16  : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
 183 def extloadi64i8   : PatFrag<(ops node:$ptr), (i64 (extloadi8  node:$ptr))>;
 184 def extloadi64i16  : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
 185 def extloadi64i32  : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
 186
 187 def sextloadi32i8   : PatFrag<(ops node:$ptr), (i32 (sextloadi8  node:$ptr))>;
 188 def sextloadi32i16  : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
 189 def sextloadi64i8   : PatFrag<(ops node:$ptr), (i64 (sextloadi8  node:$ptr))>;
 190 def sextloadi64i16  : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
 191 def sextloadi64i32  : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
 192
 193 def zextloadi32i8   : PatFrag<(ops node:$ptr), (i32 (zextloadi8  node:$ptr))>;
 194 def zextloadi32i16  : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
 195 def zextloadi64i8   : PatFrag<(ops node:$ptr), (i64 (zextloadi8  node:$ptr))>;
 196 def zextloadi64i16  : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
 197 def zextloadi64i32  : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
 198
 199 // A couple of more descriptive operand definitions.
 200 // 32-bits but only 8 bits are significant.
 201 def i32i8imm  : Operand<i32>;
 202 // 32-bits but only 16 bits are significant.
 203 def i32i16imm : Operand<i32>;
 204 // 64-bits but only 32 bits are significant.
 205 def i64i32imm : Operand<i64>;
 206 // Branch targets have OtherVT type.
 207 def brtarget : Operand<OtherVT>;
 208
 209 //===----------------------------------------------------------------------===//
 210 // SystemZ Operand Definitions.
 211 //===----------------------------------------------------------------------===//
 212
 213 // Address operands
 214
 215 // riaddr := reg + imm
 216 def riaddr32 : Operand<i32>,
 217                ComplexPattern<i32, 2, "SelectAddrRI", []> {
 218   let PrintMethod = "printRIAddrOperand";
 219   let MIOperandInfo = (ops ADDR32:$base, i32imm:$disp);
 220 }
 221
 222 def riaddr : Operand<i64>,
 223              ComplexPattern<i64, 2, "SelectAddrRI", []> {
 224   let PrintMethod = "printRIAddrOperand";
 225   let MIOperandInfo = (ops ADDR64:$base, i64imm:$disp);
 226 }
 227
 228 //===----------------------------------------------------------------------===//
 229
 230 // rriaddr := reg + reg + imm
 231 def rriaddr : Operand<i64>,
 232               ComplexPattern<i64, 3, "SelectAddrRRI", [], []> {
 233   let PrintMethod = "printRRIAddrOperand";
 234   let MIOperandInfo = (ops ADDR64:$base, i64imm:$disp, ADDR64:$index);
 235 }
 236 def laaddr : Operand<i64>,
 237              ComplexPattern<i64, 3, "SelectLAAddr", [add, sub, or, frameindex], []> {
 238   let PrintMethod = "printRRIAddrOperand";
 239   let MIOperandInfo = (ops ADDR64:$base, i64imm:$disp, ADDR64:$index);
 240 }
 241
 242 //===----------------------------------------------------------------------===//
 243 // Instruction list..
 244
 245 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
 246                               "#ADJCALLSTACKDOWN",
 247                               [(SystemZcallseq_start timm:$amt)]>;
 248 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
 249                               "#ADJCALLSTACKUP",
 250                               [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
 251
 252 let usesCustomDAGSchedInserter = 1 in {
 253   def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
 254                         "# Select32 PSEUDO",
 255                         [(set GR32:$dst,
 256                               (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>;
 257   def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
 258                         "# Select64 PSEUDO",
 259                         [(set GR64:$dst,
 260                               (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>;
 261 }
 262
 263
 264 //===----------------------------------------------------------------------===//
 265 //  Control Flow Instructions...
 266 //
 267
 268 // FIXME: Provide proper encoding!
 269 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
 270   def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
 271 }
 272
 273 let isBranch = 1, isTerminator = 1 in {
 274   let isBarrier = 1 in
 275     def JMP  : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
 276
 277   let Uses = [PSW] in {
 278     def JE  : Pseudo<(outs), (ins brtarget:$dst),
 279                      "je\t$dst",
 280                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>;
 281     def JNE : Pseudo<(outs), (ins brtarget:$dst),
 282                      "jne\t$dst",
 283                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>;
 284     def JH  : Pseudo<(outs), (ins brtarget:$dst),
 285                      "jh\t$dst",
 286                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>;
 287     def JL  : Pseudo<(outs), (ins brtarget:$dst),
 288                      "jl\t$dst",
 289                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>;
 290     def JHE : Pseudo<(outs), (ins brtarget:$dst),
 291                      "jhe\t$dst",
 292                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>;
 293     def JLE : Pseudo<(outs), (ins brtarget:$dst),
 294                      "jle\t$dst",
 295                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>;
 296
 297   } // Uses = [PSW]
 298 } // isBranch = 1
 299
 300 //===----------------------------------------------------------------------===//
 301 //  Call Instructions...
 302 //
 303
 304 let isCall = 1 in
 305   // All calls clobber the non-callee saved registers (except R14 which we
 306   // handle separately). Uses for argument registers are added manually.
 307   let Defs = [R0D, R1D, R2D, R3D, R4D, R5D] in {
 308     def CALLi     : Pseudo<(outs), (ins i64imm:$dst, variable_ops),
 309                            "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
 310     def CALLr     : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
 311                            "brasl\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>;
 312   }
 313
 314 //===----------------------------------------------------------------------===//
 315 //  Miscellaneous Instructions.
 316 //
 317
 318 let isReMaterializable = 1 in
 319 // FIXME: Provide imm12 variant
 320 def LA64r  : Pseudo<(outs GR64:$dst), (ins laaddr:$src),
 321                     "lay\t{$dst, $src}",
 322                     [(set GR64:$dst, laaddr:$src)]>;
 323 def LA64rm : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 324                     "larl\t{$dst, $src}",
 325                     [(set GR64:$dst,
 326                           (SystemZpcrelwrapper tglobaladdr:$src))]>;
 327
 328 let neverHasSideEffects = 1 in
 329 def NOP : Pseudo<(outs), (ins), "# no-op", []>;
 330
 331 //===----------------------------------------------------------------------===//
 332 // Move Instructions
 333
 334 // FIXME: Provide proper encoding!
 335 let neverHasSideEffects = 1 in {
 336 def MOV32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 337                      "lr\t{$dst, $src}",
 338                      []>;
 339 def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 340                      "lgr\t{$dst, $src}",
 341                      []>;
 342 def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
 343                      "# MOV128 PSEUDO!"
 344                      "lgr\t{$dst:subreg_odd, $src:subreg_odd}\n"
 345                      "lgr\t{$dst:subreg_even, $src:subreg_even}",
 346                      []>;
 347 def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
 348                      "# MOV64P PSEUDO!"
 349                      "lr\t{$dst:subreg_odd, $src:subreg_odd}\n"
 350                      "lr\t{$dst:subreg_even, $src:subreg_even}",
 351                      []>;
 352 }
 353
 354 def MOVSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 355                          "lgfr\t{$dst, $src}",
 356                          [(set GR64:$dst, (sext GR32:$src))]>;
 357 def MOVZX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 358                          "llgfr\t{$dst, $src}",
 359                          [(set GR64:$dst, (zext GR32:$src))]>;
 360
 361 // FIXME: Provide proper encoding!
 362 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 363 def MOV32ri16 : Pseudo<(outs GR32:$dst), (ins i32imm:$src),
 364                        "lhi\t{$dst, $src}",
 365                        [(set GR32:$dst, immSExt16:$src)]>;
 366 def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 367                        "lghi\t{$dst, $src}",
 368                        [(set GR64:$dst, immSExt16:$src)]>;
 369
 370 def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 371                          "llill\t{$dst, $src}",
 372                          [(set GR64:$dst, i64ll16:$src)]>;
 373 def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 374                          "llilh\t{$dst, $src}",
 375                          [(set GR64:$dst, i64lh16:$src)]>;
 376 def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 377                          "llihl\t{$dst, $src}",
 378                          [(set GR64:$dst, i64hl16:$src)]>;
 379 def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 380                          "llihh\t{$dst, $src}",
 381                          [(set GR64:$dst, i64hh16:$src)]>;
 382 // FIXME: these 3 instructions seem to require extimm facility
 383 def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 384                        "lgfi\t{$dst, $src}",
 385                        [(set GR64:$dst, immSExt32:$src)]>;
 386 def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 387                          "llilf\t{$dst, $src}",
 388                          [(set GR64:$dst, i64lo32:$src)]>;
 389 def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 390                          "llihf\t{$dst, $src}",
 391                          [(set GR64:$dst, i64hi32:$src)]>;
 392 }
 393
 394 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
 395 def MOV32rm : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 396                      "ly\t{$dst, $src}",
 397                      [(set GR32:$dst, (load rriaddr:$src))]>;
 398 def MOV64rm : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 399                      "lg\t{$dst, $src}",
 400                      [(set GR64:$dst, (load rriaddr:$src))]>;
 401
 402 }
 403
 404 def MOV32mr : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 405                      "sty\t{$src, $dst}",
 406                      [(store GR32:$src, rriaddr:$dst)]>;
 407 def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 408                      "stg\t{$src, $dst}",
 409                      [(store GR64:$src, rriaddr:$dst)]>;
 410
 411 // FIXME: displacements here are really 12 bit, not 20!
 412 def MOV8mi    : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src),
 413                        "mvi\t{$dst, $src}",
 414                        [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
 415 def MOV16mi   : Pseudo<(outs), (ins riaddr:$dst, i32i16imm:$src),
 416                        "mvhhi\t{$dst, $src}",
 417                        [(truncstorei16 (i32 i32immSExt16:$src), riaddr:$dst)]>;
 418 def MOV32mi16 : Pseudo<(outs), (ins riaddr:$dst, i32imm:$src),
 419                        "mvhi\t{$dst, $src}",
 420                        [(store (i32 immSExt16:$src), riaddr:$dst)]>;
 421 def MOV64mi16 : Pseudo<(outs), (ins riaddr:$dst, i64imm:$src),
 422                        "mvghi\t{$dst, $src}",
 423                        [(store (i64 immSExt16:$src), riaddr:$dst)]>;
 424
 425 // sexts
 426 def MOVSX32rr8  : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 427                          "lbr\t{$dst, $src}",
 428                          [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>;
 429 def MOVSX64rr8  : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 430                          "lgbr\t{$dst, $src}",
 431                          [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>;
 432 def MOVSX32rr16 : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 433                          "lhr\t{$dst, $src}",
 434                          [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>;
 435 def MOVSX64rr16 : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 436                          "lghr\t{$dst, $src}",
 437                          [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>;
 438
 439 // extloads
 440 def MOVSX32rm8  : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 441                          "lb\t{$dst, $src}",
 442                          [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
 443 def MOVSX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 444                          "lhy\t{$dst, $src}",
 445                          [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
 446 def MOVSX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 447                          "lgb\t{$dst, $src}",
 448                          [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
 449 def MOVSX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 450                          "lgh\t{$dst, $src}",
 451                          [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
 452 def MOVSX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 453                          "lgf\t{$dst, $src}",
 454                          [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
 455
 456 def MOVZX32rm8  : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 457                          "llc\t{$dst, $src}",
 458                          [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
 459 def MOVZX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 460                          "llh\t{$dst, $src}",
 461                          [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
 462 def MOVZX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 463                          "llgc\t{$dst, $src}",
 464                          [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
 465 def MOVZX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 466                          "llgh\t{$dst, $src}",
 467                          [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
 468 def MOVZX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 469                          "llgf\t{$dst, $src}",
 470                          [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
 471
 472 // truncstores
 473 // FIXME: Implement 12-bit displacement stuff someday
 474 def MOV32m8r  : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 475                        "stcy\t{$src, $dst}",
 476                        [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
 477
 478 def MOV32m16r : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 479                        "sthy\t{$src, $dst}",
 480                        [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
 481
 482 def MOV64m8r  : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 483                        "stcy\t{$src, $dst}",
 484                        [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
 485
 486 def MOV64m16r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 487                        "sthy\t{$src, $dst}",
 488                        [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
 489
 490 def MOV64m32r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 491                        "sty\t{$src, $dst}",
 492                        [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
 493
 494 // multiple regs moves
 495 // FIXME: should we use multiple arg nodes?
 496 def MOV32mrm  : Pseudo<(outs), (ins riaddr:$dst, GR32:$from, GR32:$to),
 497                        "stmy\t{$from, $to, $dst}",
 498                        []>;
 499 def MOV64mrm  : Pseudo<(outs), (ins riaddr:$dst, GR64:$from, GR64:$to),
 500                        "stmg\t{$from, $to, $dst}",
 501                        []>;
 502 def MOV32rmm  : Pseudo<(outs GR32:$from, GR32:$to), (ins riaddr:$dst),
 503                        "lmy\t{$from, $to, $dst}",
 504                        []>;
 505 def MOV64rmm  : Pseudo<(outs GR64:$from, GR64:$to), (ins riaddr:$dst),
 506                        "lmg\t{$from, $to, $dst}",
 507                        []>;
 508
 509
 510 //===----------------------------------------------------------------------===//
 511 // Arithmetic Instructions
 512
 513 let isTwoAddress = 1 in {
 514
 515 let Defs = [PSW] in {
 516
 517 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
 518 // FIXME: Provide proper encoding!
 519 def ADD32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 520                      "ar\t{$dst, $src2}",
 521                      [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 522                       (implicit PSW)]>;
 523 def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 524                      "agr\t{$dst, $src2}",
 525                      [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
 526                       (implicit PSW)]>;
 527 }
 528
 529 // FIXME: Provide proper encoding!
 530 def ADD32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 531                        "ahi\t{$dst, $src2}",
 532                        [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
 533                         (implicit PSW)]>;
 534 def ADD32ri   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 535                        "afi\t{$dst, $src2}",
 536                        [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
 537                         (implicit PSW)]>;
 538 def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 539                        "aghi\t{$dst, $src2}",
 540                        [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
 541                         (implicit PSW)]>;
 542 def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 543                        "agfi\t{$dst, $src2}",
 544                        [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
 545                         (implicit PSW)]>;
 546
 547 let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
 548 // FIXME: Provide proper encoding!
 549 def AND32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 550                      "nr\t{$dst, $src2}",
 551                      [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
 552 def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 553                      "ngr\t{$dst, $src2}",
 554                      [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
 555 }
 556
 557 // FIXME: Provide proper encoding!
 558 def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 559                          "nill\t{$dst, $src2}",
 560                          [(set GR64:$dst, (and GR64:$src1, i64ll16:$src2))]>;
 561 def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 562                          "nilh\t{$dst, $src2}",
 563                          [(set GR64:$dst, (and GR64:$src1, i64lh16:$src2))]>;
 564 def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 565                          "nihl\t{$dst, $src2}",
 566                          [(set GR64:$dst, (and GR64:$src1, i64hl16:$src2))]>;
 567 def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 568                          "nihh\t{$dst, $src2}",
 569                          [(set GR64:$dst, (and GR64:$src1, i64hh16:$src2))]>;
 570 // FIXME: these 2 instructions seem to require extimm facility
 571 def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 572                          "nilf\t{$dst, $src2}",
 573                          [(set GR64:$dst, (and GR64:$src1, i64lo32:$src2))]>;
 574 def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 575                          "nihf\t{$dst, $src2}",
 576                          [(set GR64:$dst, (and GR64:$src1, i64hi32:$src2))]>;
 577
 578 let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
 579 // FIXME: Provide proper encoding!
 580 def OR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 581                     "or\t{$dst, $src2}",
 582                     [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
 583 def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 584                     "ogr\t{$dst, $src2}",
 585                     [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
 586 }
 587
 588 def OR32ri16  : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2),
 589                       "oill\t{$dst, $src2}",
 590                       [(set GR32:$dst, (or GR32:$src1, i64ll16:$src2))]>;
 591 def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2),
 592                       "oilh\t{$dst, $src2}",
 593                       [(set GR32:$dst, (or GR32:$src1, i64lh16:$src2))]>;
 594 def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 595                     "oilf\t{$dst, $src2}",
 596                     [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
 597
 598 def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 599                         "oill\t{$dst, $src2}",
 600                         [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
 601 def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 602                         "oilh\t{$dst, $src2}",
 603                         [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
 604 def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 605                         "oihl\t{$dst, $src2}",
 606                         [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
 607 def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 608                         "oihh\t{$dst, $src2}",
 609                         [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
 610 // FIXME: these 2 instructions seem to require extimm facility
 611 def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 612                         "oilf\t{$dst, $src2}",
 613                         [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
 614 def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 615                         "oihf\t{$dst, $src2}",
 616                         [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
 617
 618 // FIXME: Provide proper encoding!
 619 def SUB32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 620                      "sr\t{$dst, $src2}",
 621                      [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
 622 def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 623                      "sgr\t{$dst, $src2}",
 624                      [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
 625
 626
 627 let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
 628 // FIXME: Provide proper encoding!
 629 def XOR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 630                      "xr\t{$dst, $src2}",
 631                      [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
 632 def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 633                      "xgr\t{$dst, $src2}",
 634                      [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
 635 }
 636
 637 def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 638                      "xilf\t{$dst, $src2}",
 639                      [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
 640
 641 // FIXME: these 2 instructions seem to require extimm facility
 642 def XOR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 643                          "xilf\t{$dst, $src2}",
 644                          [(set GR64:$dst, (xor GR64:$src1, i64lo32:$src2))]>;
 645 def XOR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 646                          "xihf\t{$dst, $src2}",
 647                          [(set GR64:$dst, (xor GR64:$src1, i64hi32:$src2))]>;
 648
 649 } // Defs = [PSW]
 650
 651 let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
 652 def MUL32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 653                      "msr\t{$dst, $src2}",
 654                      [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
 655 def MUL64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 656                      "msgr\t{$dst, $src2}",
 657                      [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
 658
 659 def MUL64rrP   : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 660                         "mr\t{$dst, $src2}",
 661                         []>;
 662 def UMUL64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 663                          "mlr\t{$dst, $src2}",
 664                          []>;
 665 def UMUL128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 666                         "mlgr\t{$dst, $src2}",
 667                         []>;
 668 }
 669
 670
 671 def MUL32ri16   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32i16imm:$src2),
 672                          "mhi\t{$dst, $src2}",
 673                          [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
 674 def MUL32ri     : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 675                          "msfi\t{$dst, $src2}",
 676                          [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
 677 def MUL64ri16   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 678                          "mghi\t{$dst, $src2}",
 679                          [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
 680 def MUL64ri32   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
 681                          "msgfi\t{$dst, $src2}",
 682                          [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>;
 683
 684 def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 685                      "msy\t{$dst, $src2}",
 686                      [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
 687 def MUL64rm : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 688                      "msgy\t{$dst, $src2}",
 689                      [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
 690
 691 def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
 692                          "msgfr\t{$dst, $src2}",
 693                          [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
 694
 695 def SDIVREM64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 696                            "dr\t{$dst, $src2}",
 697                            []>;
 698
 699 def SDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 700                            "dsgr\t{$dst, $src2}",
 701                            []>;
 702
 703 def UDIVREM64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 704                            "dlr\t{$dst, $src2}",
 705                            []>;
 706
 707 def UDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 708                            "dlgr\t{$dst, $src2}",
 709                            []>;
 710
 711 } // isTwoAddress = 1
 712
 713 //===----------------------------------------------------------------------===//
 714 // Shifts
 715
 716 let isTwoAddress = 1 in
 717 def SRL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 718                       "srl\t{$src, $amt}",
 719                       [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
 720 def SRL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 721                       "srlg\t{$dst, $src, $amt}",
 722                       [(set GR64:$dst, (srl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 723 def SRLA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 724                       "srlg\t{$dst, $src, $amt}",
 725                       [(set GR64:$dst, (srl GR64:$src, (i32 imm:$amt)))]>;
 726
 727 let isTwoAddress = 1 in
 728 def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 729                       "sll\t{$src, $amt}",
 730                       [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
 731 def SHL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 732                       "sllg\t{$dst, $src, $amt}",
 733                       [(set GR64:$dst, (shl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 734 def SHL64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 735                       "sllg\t{$dst, $src, $amt}",
 736                       [(set GR64:$dst, (shl GR64:$src, (i32 imm:$amt)))]>;
 737
 738
 739 let Defs = [PSW] in {
 740 let isTwoAddress = 1 in
 741 def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 742                       "sra\t{$src, $amt}",
 743                       [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
 744                        (implicit PSW)]>;
 745 def SRA64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 746                       "srag\t{$dst, $src, $amt}",
 747                       [(set GR64:$dst, (sra GR64:$src, (i32 (trunc riaddr:$amt)))),
 748                        (implicit PSW)]>;
 749 def SRA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 750                       "srag\t{$dst, $src, $amt}",
 751                       [(set GR64:$dst, (sra GR64:$src, (i32 imm:$amt))),
 752                        (implicit PSW)]>;
 753 } // Defs = [PSW]
 754
 755 //===----------------------------------------------------------------------===//
 756 // Test instructions (like AND but do not produce any result
 757
 758 // Integer comparisons
 759 let Defs = [PSW] in {
 760 def CMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 761                      "cr\t$src1, $src2",
 762                      [(SystemZcmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 763 def CMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 764                      "cgr\t$src1, $src2",
 765                      [(SystemZcmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 766
 767 def CMP32ri   : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2),
 768                        "cfi\t$src1, $src2",
 769                        [(SystemZcmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 770 def CMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2),
 771                        "cgfi\t$src1, $src2",
 772                        [(SystemZcmp GR64:$src1, i64immSExt32:$src2),
 773                         (implicit PSW)]>;
 774
 775 def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 776                      "cy\t$src1, $src2",
 777                      [(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
 778                       (implicit PSW)]>;
 779 def CMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 780                      "cg\t$src1, $src2",
 781                      [(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
 782                       (implicit PSW)]>;
 783
 784 def UCMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 785                       "clr\t$src1, $src2",
 786                       [(SystemZucmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 787 def UCMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 788                       "clgr\t$src1, $src2",
 789                       [(SystemZucmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 790
 791 def UCMP32ri   : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2),
 792                         "clfi\t$src1, $src2",
 793                         [(SystemZucmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 794 def UCMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2),
 795                         "clgfi\t$src1, $src2",
 796                         [(SystemZucmp GR64:$src1, i64immZExt32:$src2),
 797                          (implicit PSW)]>;
 798
 799 def UCMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 800                       "cly\t$src1, $src2",
 801                       [(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
 802                        (implicit PSW)]>;
 803 def UCMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 804                       "clg\t$src1, $src2",
 805                       [(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
 806                        (implicit PSW)]>;
 807
 808 def CMPSX64rr32  : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 809                           "cgfr\t$src1, $src2",
 810                           [(SystemZucmp GR64:$src1, (sext GR32:$src2)),
 811                            (implicit PSW)]>;
 812 def UCMPZX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 813                           "clgfr\t$src1, $src2",
 814                           [(SystemZucmp GR64:$src1, (zext GR32:$src2)),
 815                            (implicit PSW)]>;
 816
 817 def CMPSX64rm32   : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 818                            "cgf\t$src1, $src2",
 819                            [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
 820                             (implicit PSW)]>;
 821 def UCMPZX64rm32  : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 822                            "clgf\t$src1, $src2",
 823                            [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
 824                             (implicit PSW)]>;
 825
 826 // FIXME: Add other crazy ucmp forms
 827
 828 } // Defs = [PSW]
 829
 830 //===----------------------------------------------------------------------===//
 831 // Non-Instruction Patterns.
 832 //===----------------------------------------------------------------------===//
 833
 834 // anyext
 835 def : Pat<(i64 (anyext GR32:$src)),
 836           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
 837
 838 //===----------------------------------------------------------------------===//
 839 // Peepholes.
 840 //===----------------------------------------------------------------------===//
 841
 842 // FIXME: use add/sub tricks with 32678/-32768
 843
 844 // trunc patterns
 845 def : Pat<(i32 (trunc GR64:$src)),
 846           (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
 847
 848 // sext_inreg patterns
 849 def : Pat<(sext_inreg GR64:$src, i32),
 850           (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
 851
 852 // extload patterns
 853 def : Pat<(extloadi32i8  rriaddr:$src), (MOVZX32rm8  rriaddr:$src)>;
 854 def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>;
 855 def : Pat<(extloadi64i8  rriaddr:$src), (MOVZX64rm8  rriaddr:$src)>;
 856 def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
 857 def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
 858
 859 // calls
 860 def : Pat<(SystemZcall (i64 tglobaladdr:$dst)),
 861           (CALLi tglobaladdr:$dst)>;
 862 def : Pat<(SystemZcall (i64 texternalsym:$dst)),
 863           (CALLi texternalsym:$dst)>;
 864
 865 // muls
 866 def : Pat<(mulhs GR32:$src1, GR32:$src2),
 867           (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 868                                                    GR32:$src1, subreg_odd),
 869                                     GR32:$src2),
 870                           subreg_even)>;
 871
 872 def : Pat<(mulhu GR32:$src1, GR32:$src2),
 873           (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 874                                                     GR32:$src1, subreg_odd),
 875                                      GR32:$src2),
 876                           subreg_even)>;
 877 def : Pat<(mulhu GR64:$src1, GR64:$src2),
 878           (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 879                                                      GR64:$src1, subreg_odd),
 880                                       GR64:$src2),
 881                           subreg_even)>;
 882
 883 // divs
 884 // FIXME: Add memory versions
 885 def : Pat<(sdiv GR32:$src1, GR32:$src2),
 886           (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 887                                                        GR32:$src1, subreg_odd),
 888                                          GR32:$src2),
 889                           subreg_odd)>;
 890 def : Pat<(sdiv GR64:$src1, GR64:$src2),
 891           (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 892                                                         GR64:$src1, subreg_odd),
 893                                          GR64:$src2),
 894                           subreg_odd)>;
 895 def : Pat<(udiv GR32:$src1, GR32:$src2),
 896           (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 897                                                        GR32:$src1, subreg_odd),
 898                                          GR32:$src2),
 899                           subreg_odd)>;
 900 def : Pat<(udiv GR64:$src1, GR64:$src2),
 901           (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 902                                                         GR64:$src1, subreg_odd),
 903                                          GR64:$src2),
 904                           subreg_odd)>;
 905
 906 // rems
 907 // FIXME: Add memory versions
 908 def : Pat<(srem GR32:$src1, GR32:$src2),
 909           (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 910                                                        GR32:$src1, subreg_odd),
 911                                          GR32:$src2),
 912                           subreg_even)>;
 913 def : Pat<(srem GR64:$src1, GR64:$src2),
 914           (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 915                                                         GR64:$src1, subreg_odd),
 916                                          GR64:$src2),
 917                           subreg_even)>;
 918 def : Pat<(urem GR32:$src1, GR32:$src2),
 919           (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 920                                                        GR32:$src1, subreg_odd),
 921                                          GR32:$src2),
 922                           subreg_even)>;
 923 def : Pat<(urem GR64:$src1, GR64:$src2),
 924           (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 925                                                         GR64:$src1, subreg_odd),
 926                                          GR64:$src2),
 927                           subreg_even)>;