lib/Target/SystemZ/SystemZInstrInfo.td

   1 //===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the SystemZ instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 include "SystemZInstrFormats.td"
  15
  16 //===----------------------------------------------------------------------===//
  17 // Type Constraints.
  18 //===----------------------------------------------------------------------===//
  19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
  20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
  21 class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>;
  22 class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
  23
  24 //===----------------------------------------------------------------------===//
  25 // Type Profiles.
  26 //===----------------------------------------------------------------------===//
  27 def SDT_SystemZCall         : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
  28 def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
  29 def SDT_SystemZCallSeqEnd   : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
  30 def SDT_CmpTest             : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
  31 def SDT_BrCond              : SDTypeProfile<0, 2,
  32                                            [SDTCisVT<0, OtherVT>,
  33                                             SDTCisI8<1>]>;
  34 def SDT_SelectCC            : SDTypeProfile<1, 3,
  35                                            [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  36                                             SDTCisI8<3>]>;
  37 def SDT_Address             : SDTypeProfile<1, 1,
  38                                             [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
  39
  40 //===----------------------------------------------------------------------===//
  41 // SystemZ Specific Node Definitions.
  42 //===----------------------------------------------------------------------===//
  43 def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
  44                      [SDNPHasChain, SDNPOptInFlag]>;
  45 def SystemZcall    : SDNode<"SystemZISD::CALL", SDT_SystemZCall,
  46                      [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
  47 def SystemZcallseq_start :
  48                  SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart,
  49                         [SDNPHasChain, SDNPOutFlag]>;
  50 def SystemZcallseq_end :
  51                  SDNode<"ISD::CALLSEQ_END",   SDT_SystemZCallSeqEnd,
  52                         [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
  53 def SystemZcmp     : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>;
  54 def SystemZucmp    : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>;
  55 def SystemZbrcond  : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
  56                             [SDNPHasChain, SDNPInFlag]>;
  57 def SystemZselect  : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>;
  58 def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
  59
  60 //===----------------------------------------------------------------------===//
  61 // Instruction Pattern Stuff.
  62 //===----------------------------------------------------------------------===//
  63
  64 // SystemZ specific condition code. These correspond to CondCode in
  65 // SystemZ.h. They must be kept in synch.
  66 def SYSTEMZ_COND_E  : PatLeaf<(i8 0)>;
  67 def SYSTEMZ_COND_NE : PatLeaf<(i8 1)>;
  68 def SYSTEMZ_COND_H  : PatLeaf<(i8 2)>;
  69 def SYSTEMZ_COND_L  : PatLeaf<(i8 3)>;
  70 def SYSTEMZ_COND_HE : PatLeaf<(i8 4)>;
  71 def SYSTEMZ_COND_LE : PatLeaf<(i8 5)>;
  72
  73 def LL16 : SDNodeXForm<imm, [{
  74   // Transformation function: return low 16 bits.
  75   return getI16Imm(N->getZExtValue() & 0x000000000000FFFFULL);
  76 }]>;
  77
  78 def LH16 : SDNodeXForm<imm, [{
  79   // Transformation function: return bits 16-31.
  80   return getI16Imm((N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16);
  81 }]>;
  82
  83 def HL16 : SDNodeXForm<imm, [{
  84   // Transformation function: return bits 32-47.
  85   return getI16Imm((N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32);
  86 }]>;
  87
  88 def HH16 : SDNodeXForm<imm, [{
  89   // Transformation function: return bits 48-63.
  90   return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48);
  91 }]>;
  92
  93 def LO32 : SDNodeXForm<imm, [{
  94   // Transformation function: return low 32 bits.
  95   return getI32Imm(N->getZExtValue() & 0x00000000FFFFFFFFULL);
  96 }]>;
  97
  98 def HI32 : SDNodeXForm<imm, [{
  99   // Transformation function: return bits 32-63.
 100   return getI32Imm(N->getZExtValue() >> 32);
 101 }]>;
 102
 103 def i64ll16 : PatLeaf<(imm), [{
 104   // i64ll16 predicate - true if the 64-bit immediate has only rightmost 16
 105   // bits set.
 106   return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
 107 }], LL16>;
 108
 109 def i64lh16 : PatLeaf<(imm), [{
 110   // i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set.
 111   return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
 112 }], LH16>;
 113
 114 def i64hl16 : PatLeaf<(i64 imm), [{
 115   // i64hl16 predicate - true if the 64-bit immediate has only bits 32-47 set.
 116   return ((N->getZExtValue() & 0x0000FFFF00000000ULL) == N->getZExtValue());
 117 }], HL16>;
 118
 119 def i64hh16 : PatLeaf<(i64 imm), [{
 120   // i64hh16 predicate - true if the 64-bit immediate has only bits 48-63 set.
 121   return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue());
 122 }], HH16>;
 123
 124 def immSExt16 : PatLeaf<(imm), [{
 125   // immSExt16 predicate - true if the immediate fits in a 16-bit sign extended
 126   // field.
 127   if (N->getValueType(0) == MVT::i64) {
 128     uint64_t val = N->getZExtValue();
 129     return ((int64_t)val == (int16_t)val);
 130   } else if (N->getValueType(0) == MVT::i32) {
 131     uint32_t val = N->getZExtValue();
 132     return ((int32_t)val == (int16_t)val);
 133   }
 134
 135   return false;
 136 }]>;
 137
 138 def immSExt32 : PatLeaf<(i64 imm), [{
 139   // immSExt32 predicate - true if the immediate fits in a 32-bit sign extended
 140   // field.
 141   uint64_t val = N->getZExtValue();
 142   return ((int64_t)val == (int32_t)val);
 143 }]>;
 144
 145 def i64lo32 : PatLeaf<(i64 imm), [{
 146   // i64lo32 predicate - true if the 64-bit immediate has only rightmost 32
 147   // bits set.
 148   return ((N->getZExtValue() & 0x00000000FFFFFFFFULL) == N->getZExtValue());
 149 }], LO32>;
 150
 151 def i64hi32 : PatLeaf<(i64 imm), [{
 152   // i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set.
 153   return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue());
 154 }], HI32>;
 155
 156 def i32immSExt8  : PatLeaf<(i32 imm), [{
 157   // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
 158   // sign extended field.
 159   return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
 160 }]>;
 161
 162 def i32immSExt16 : PatLeaf<(i32 imm), [{
 163   // i32immSExt16 predicate - True if the 32-bit immediate fits in a 16-bit
 164   // sign extended field.
 165   return (int32_t)N->getZExtValue() == (int16_t)N->getZExtValue();
 166 }]>;
 167
 168 def i64immSExt32 : PatLeaf<(i64 imm), [{
 169   // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
 170   // sign extended field.
 171   return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
 172 }]>;
 173
 174 def i64immZExt32 : PatLeaf<(i64 imm), [{
 175   // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
 176   // zero extended field.
 177   return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
 178 }]>;
 179
 180 // extloads
 181 def extloadi32i8   : PatFrag<(ops node:$ptr), (i32 (extloadi8  node:$ptr))>;
 182 def extloadi32i16  : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
 183 def extloadi64i8   : PatFrag<(ops node:$ptr), (i64 (extloadi8  node:$ptr))>;
 184 def extloadi64i16  : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
 185 def extloadi64i32  : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
 186
 187 def sextloadi32i8   : PatFrag<(ops node:$ptr), (i32 (sextloadi8  node:$ptr))>;
 188 def sextloadi32i16  : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
 189 def sextloadi64i8   : PatFrag<(ops node:$ptr), (i64 (sextloadi8  node:$ptr))>;
 190 def sextloadi64i16  : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
 191 def sextloadi64i32  : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
 192
 193 def zextloadi32i8   : PatFrag<(ops node:$ptr), (i32 (zextloadi8  node:$ptr))>;
 194 def zextloadi32i16  : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
 195 def zextloadi64i8   : PatFrag<(ops node:$ptr), (i64 (zextloadi8  node:$ptr))>;
 196 def zextloadi64i16  : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
 197 def zextloadi64i32  : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
 198
 199 // A couple of more descriptive operand definitions.
 200 // 32-bits but only 8 bits are significant.
 201 def i32i8imm  : Operand<i32>;
 202 // 32-bits but only 16 bits are significant.
 203 def i32i16imm : Operand<i32>;
 204 // 64-bits but only 32 bits are significant.
 205 def i64i32imm : Operand<i64>;
 206 // Branch targets have OtherVT type.
 207 def brtarget : Operand<OtherVT>;
 208
 209 // Unigned i12
 210 def u12imm : Operand<i32> {
 211   let PrintMethod = "printU16ImmOperand";
 212 }
 213 // Signed i16
 214 def s16imm : Operand<i32> {
 215   let PrintMethod = "printS16ImmOperand";
 216 }
 217 def s16imm64 : Operand<i64> {
 218   let PrintMethod = "printS16ImmOperand";
 219 }
 220 // Signed i20
 221 def s20imm : Operand<i32> {
 222   let PrintMethod = "printS20ImmOperand";
 223 }
 224 def s20imm64 : Operand<i64> {
 225   let PrintMethod = "printS20ImmOperand";
 226 }
 227 // Signed i32
 228 def s32imm : Operand<i32> {
 229   let PrintMethod = "printS32ImmOperand";
 230 }
 231 def s32imm64 : Operand<i64> {
 232   let PrintMethod = "printS32ImmOperand";
 233 }
 234
 235 //===----------------------------------------------------------------------===//
 236 // SystemZ Operand Definitions.
 237 //===----------------------------------------------------------------------===//
 238
 239 // Address operands
 240
 241 // riaddr := reg + imm
 242 def riaddr32 : Operand<i32>,
 243                ComplexPattern<i32, 2, "SelectAddrRI32", []> {
 244   let PrintMethod = "printRIAddrOperand";
 245   let MIOperandInfo = (ops ADDR32:$base, u12imm:$disp);
 246 }
 247
 248 def riaddr : Operand<i64>,
 249              ComplexPattern<i64, 2, "SelectAddrRI", []> {
 250   let PrintMethod = "printRIAddrOperand";
 251   let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp);
 252 }
 253
 254 //===----------------------------------------------------------------------===//
 255
 256 // rriaddr := reg + reg + imm
 257 def rriaddr : Operand<i64>,
 258               ComplexPattern<i64, 3, "SelectAddrRRI", [], []> {
 259   let PrintMethod = "printRRIAddrOperand";
 260   let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
 261 }
 262 def laaddr : Operand<i64>,
 263              ComplexPattern<i64, 3, "SelectLAAddr", [add, sub, or, frameindex], []> {
 264   let PrintMethod = "printRRIAddrOperand";
 265   let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
 266 }
 267
 268 //===----------------------------------------------------------------------===//
 269 // Instruction list..
 270
 271 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
 272                               "#ADJCALLSTACKDOWN",
 273                               [(SystemZcallseq_start timm:$amt)]>;
 274 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
 275                               "#ADJCALLSTACKUP",
 276                               [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
 277
 278 let usesCustomDAGSchedInserter = 1 in {
 279   def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
 280                         "# Select32 PSEUDO",
 281                         [(set GR32:$dst,
 282                               (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>;
 283   def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
 284                         "# Select64 PSEUDO",
 285                         [(set GR64:$dst,
 286                               (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>;
 287 }
 288
 289
 290 //===----------------------------------------------------------------------===//
 291 //  Control Flow Instructions...
 292 //
 293
 294 // FIXME: Provide proper encoding!
 295 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
 296   def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
 297 }
 298
 299 let isBranch = 1, isTerminator = 1 in {
 300   let isBarrier = 1 in
 301     def JMP  : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
 302
 303   let Uses = [PSW] in {
 304     def JE  : Pseudo<(outs), (ins brtarget:$dst),
 305                      "je\t$dst",
 306                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>;
 307     def JNE : Pseudo<(outs), (ins brtarget:$dst),
 308                      "jne\t$dst",
 309                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>;
 310     def JH  : Pseudo<(outs), (ins brtarget:$dst),
 311                      "jh\t$dst",
 312                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>;
 313     def JL  : Pseudo<(outs), (ins brtarget:$dst),
 314                      "jl\t$dst",
 315                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>;
 316     def JHE : Pseudo<(outs), (ins brtarget:$dst),
 317                      "jhe\t$dst",
 318                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>;
 319     def JLE : Pseudo<(outs), (ins brtarget:$dst),
 320                      "jle\t$dst",
 321                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>;
 322
 323   } // Uses = [PSW]
 324 } // isBranch = 1
 325
 326 //===----------------------------------------------------------------------===//
 327 //  Call Instructions...
 328 //
 329
 330 let isCall = 1 in
 331   // All calls clobber the non-callee saved registers (except R14 which we
 332   // handle separately). Uses for argument registers are added manually.
 333   let Defs = [R0D, R1D, R2D, R3D, R4D, R5D] in {
 334     def CALLi     : Pseudo<(outs), (ins i64imm:$dst, variable_ops),
 335                            "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
 336     def CALLr     : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
 337                            "brasl\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>;
 338   }
 339
 340 //===----------------------------------------------------------------------===//
 341 //  Miscellaneous Instructions.
 342 //
 343
 344 let isReMaterializable = 1 in
 345 // FIXME: Provide imm12 variant
 346 // FIXME: Address should be halfword aligned...
 347 def LA64r  : Pseudo<(outs GR64:$dst), (ins laaddr:$src),
 348                     "lay\t{$dst, $src}",
 349                     [(set GR64:$dst, laaddr:$src)]>;
 350 def LA64rm : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 351                     "larl\t{$dst, $src}",
 352                     [(set GR64:$dst,
 353                           (SystemZpcrelwrapper tglobaladdr:$src))]>;
 354
 355 let neverHasSideEffects = 1 in
 356 def NOP : Pseudo<(outs), (ins), "# no-op", []>;
 357
 358 //===----------------------------------------------------------------------===//
 359 // Move Instructions
 360
 361 // FIXME: Provide proper encoding!
 362 let neverHasSideEffects = 1 in {
 363 def MOV32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 364                      "lr\t{$dst, $src}",
 365                      []>;
 366 def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 367                      "lgr\t{$dst, $src}",
 368                      []>;
 369 def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
 370                      "# MOV128 PSEUDO!\n"
 371                      "\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 372                      "\tlgr\t${dst:subreg_even}, ${src:subreg_even}",
 373                      []>;
 374 def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
 375                      "# MOV64P PSEUDO!\n"
 376                      "\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 377                      "\tlr\t${dst:subreg_even}, ${src:subreg_even}",
 378                      []>;
 379 }
 380
 381 def MOVSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 382                          "lgfr\t{$dst, $src}",
 383                          [(set GR64:$dst, (sext GR32:$src))]>;
 384 def MOVZX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 385                          "llgfr\t{$dst, $src}",
 386                          [(set GR64:$dst, (zext GR32:$src))]>;
 387
 388 // FIXME: Provide proper encoding!
 389 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 390 def MOV32ri16 : Pseudo<(outs GR32:$dst), (ins s16imm:$src),
 391                        "lhi\t{$dst, $src}",
 392                        [(set GR32:$dst, immSExt16:$src)]>;
 393 def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins s16imm64:$src),
 394                        "lghi\t{$dst, $src}",
 395                        [(set GR64:$dst, immSExt16:$src)]>;
 396
 397 def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 398                          "llill\t{$dst, $src}",
 399                          [(set GR64:$dst, i64ll16:$src)]>;
 400 def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 401                          "llilh\t{$dst, $src}",
 402                          [(set GR64:$dst, i64lh16:$src)]>;
 403 def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 404                          "llihl\t{$dst, $src}",
 405                          [(set GR64:$dst, i64hl16:$src)]>;
 406 def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 407                          "llihh\t{$dst, $src}",
 408                          [(set GR64:$dst, i64hh16:$src)]>;
 409 // FIXME: these 3 instructions seem to require extimm facility
 410 def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins s32imm64:$src),
 411                        "lgfi\t{$dst, $src}",
 412                        [(set GR64:$dst, immSExt32:$src)]>;
 413 def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 414                          "llilf\t{$dst, $src}",
 415                          [(set GR64:$dst, i64lo32:$src)]>;
 416 def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 417                          "llihf\t{$dst, $src}",
 418                          [(set GR64:$dst, i64hi32:$src)]>;
 419 }
 420
 421 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
 422 def MOV32rm : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 423                      "ly\t{$dst, $src}",
 424                      [(set GR32:$dst, (load rriaddr:$src))]>;
 425 def MOV64rm : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 426                      "lg\t{$dst, $src}",
 427                      [(set GR64:$dst, (load rriaddr:$src))]>;
 428
 429 }
 430
 431 def MOV32mr : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 432                      "sty\t{$src, $dst}",
 433                      [(store GR32:$src, rriaddr:$dst)]>;
 434 def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 435                      "stg\t{$src, $dst}",
 436                      [(store GR64:$src, rriaddr:$dst)]>;
 437
 438 // FIXME: displacements here are really 12 bit, not 20!
 439 def MOV8mi    : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src),
 440                        "mviy\t{$dst, $src}",
 441                        [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
 442 def MOV16mi   : Pseudo<(outs), (ins riaddr:$dst, s16imm:$src),
 443                        "mvhhi\t{$dst, $src}",
 444                        [(truncstorei16 (i32 i32immSExt16:$src), riaddr:$dst)]>;
 445 def MOV32mi16 : Pseudo<(outs), (ins riaddr:$dst, s32imm:$src),
 446                        "mvhi\t{$dst, $src}",
 447                        [(store (i32 immSExt16:$src), riaddr:$dst)]>;
 448 def MOV64mi16 : Pseudo<(outs), (ins riaddr:$dst, s32imm64:$src),
 449                        "mvghi\t{$dst, $src}",
 450                        [(store (i64 immSExt16:$src), riaddr:$dst)]>;
 451
 452 // sexts
 453 def MOVSX32rr8  : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 454                          "lbr\t{$dst, $src}",
 455                          [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>;
 456 def MOVSX64rr8  : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 457                          "lgbr\t{$dst, $src}",
 458                          [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>;
 459 def MOVSX32rr16 : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 460                          "lhr\t{$dst, $src}",
 461                          [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>;
 462 def MOVSX64rr16 : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 463                          "lghr\t{$dst, $src}",
 464                          [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>;
 465
 466 // extloads
 467 def MOVSX32rm8  : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 468                          "lb\t{$dst, $src}",
 469                          [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
 470 def MOVSX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 471                          "lhy\t{$dst, $src}",
 472                          [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
 473 def MOVSX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 474                          "lgb\t{$dst, $src}",
 475                          [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
 476 def MOVSX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 477                          "lgh\t{$dst, $src}",
 478                          [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
 479 def MOVSX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 480                          "lgf\t{$dst, $src}",
 481                          [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
 482
 483 def MOVZX32rm8  : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 484                          "llc\t{$dst, $src}",
 485                          [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
 486 def MOVZX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 487                          "llh\t{$dst, $src}",
 488                          [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
 489 def MOVZX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 490                          "llgc\t{$dst, $src}",
 491                          [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
 492 def MOVZX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 493                          "llgh\t{$dst, $src}",
 494                          [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
 495 def MOVZX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 496                          "llgf\t{$dst, $src}",
 497                          [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
 498
 499 // truncstores
 500 // FIXME: Implement 12-bit displacement stuff someday
 501 def MOV32m8r  : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 502                        "stcy\t{$src, $dst}",
 503                        [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
 504
 505 def MOV32m16r : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 506                        "sthy\t{$src, $dst}",
 507                        [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
 508
 509 def MOV64m8r  : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 510                        "stcy\t{$src, $dst}",
 511                        [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
 512
 513 def MOV64m16r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 514                        "sthy\t{$src, $dst}",
 515                        [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
 516
 517 def MOV64m32r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 518                        "sty\t{$src, $dst}",
 519                        [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
 520
 521 // multiple regs moves
 522 // FIXME: should we use multiple arg nodes?
 523 def MOV32mrm  : Pseudo<(outs), (ins riaddr:$dst, GR32:$from, GR32:$to),
 524                        "stmy\t{$from, $to, $dst}",
 525                        []>;
 526 def MOV64mrm  : Pseudo<(outs), (ins riaddr:$dst, GR64:$from, GR64:$to),
 527                        "stmg\t{$from, $to, $dst}",
 528                        []>;
 529 def MOV32rmm  : Pseudo<(outs GR32:$from, GR32:$to), (ins riaddr:$dst),
 530                        "lmy\t{$from, $to, $dst}",
 531                        []>;
 532 def MOV64rmm  : Pseudo<(outs GR64:$from, GR64:$to), (ins riaddr:$dst),
 533                        "lmg\t{$from, $to, $dst}",
 534                        []>;
 535
 536
 537 //===----------------------------------------------------------------------===//
 538 // Arithmetic Instructions
 539
 540 let isTwoAddress = 1 in {
 541
 542 let Defs = [PSW] in {
 543
 544 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
 545 // FIXME: Provide proper encoding!
 546 def ADD32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 547                      "ar\t{$dst, $src2}",
 548                      [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 549                       (implicit PSW)]>;
 550 def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 551                      "agr\t{$dst, $src2}",
 552                      [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
 553                       (implicit PSW)]>;
 554 }
 555
 556 // FIXME: Provide proper encoding!
 557 def ADD32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 558                        "ahi\t{$dst, $src2}",
 559                        [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
 560                         (implicit PSW)]>;
 561 def ADD32ri   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 562                        "afi\t{$dst, $src2}",
 563                        [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
 564                         (implicit PSW)]>;
 565 def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 566                        "aghi\t{$dst, $src2}",
 567                        [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
 568                         (implicit PSW)]>;
 569 def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 570                        "agfi\t{$dst, $src2}",
 571                        [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
 572                         (implicit PSW)]>;
 573
 574 let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
 575 // FIXME: Provide proper encoding!
 576 def AND32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 577                      "nr\t{$dst, $src2}",
 578                      [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
 579 def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 580                      "ngr\t{$dst, $src2}",
 581                      [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
 582 }
 583
 584 // FIXME: Provide proper encoding!
 585 def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 586                          "nill\t{$dst, $src2}",
 587                          [(set GR64:$dst, (and GR64:$src1, i64ll16:$src2))]>;
 588 def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 589                          "nilh\t{$dst, $src2}",
 590                          [(set GR64:$dst, (and GR64:$src1, i64lh16:$src2))]>;
 591 def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 592                          "nihl\t{$dst, $src2}",
 593                          [(set GR64:$dst, (and GR64:$src1, i64hl16:$src2))]>;
 594 def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 595                          "nihh\t{$dst, $src2}",
 596                          [(set GR64:$dst, (and GR64:$src1, i64hh16:$src2))]>;
 597 // FIXME: these 2 instructions seem to require extimm facility
 598 def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 599                          "nilf\t{$dst, $src2}",
 600                          [(set GR64:$dst, (and GR64:$src1, i64lo32:$src2))]>;
 601 def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 602                          "nihf\t{$dst, $src2}",
 603                          [(set GR64:$dst, (and GR64:$src1, i64hi32:$src2))]>;
 604
 605 let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
 606 // FIXME: Provide proper encoding!
 607 def OR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 608                     "or\t{$dst, $src2}",
 609                     [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
 610 def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 611                     "ogr\t{$dst, $src2}",
 612                     [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
 613 }
 614
 615 def OR32ri16  : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2),
 616                       "oill\t{$dst, $src2}",
 617                       [(set GR32:$dst, (or GR32:$src1, i64ll16:$src2))]>;
 618 def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2),
 619                       "oilh\t{$dst, $src2}",
 620                       [(set GR32:$dst, (or GR32:$src1, i64lh16:$src2))]>;
 621 def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 622                     "oilf\t{$dst, $src2}",
 623                     [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
 624
 625 def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 626                         "oill\t{$dst, $src2}",
 627                         [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
 628 def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 629                         "oilh\t{$dst, $src2}",
 630                         [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
 631 def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 632                         "oihl\t{$dst, $src2}",
 633                         [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
 634 def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 635                         "oihh\t{$dst, $src2}",
 636                         [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
 637 // FIXME: these 2 instructions seem to require extimm facility
 638 def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 639                         "oilf\t{$dst, $src2}",
 640                         [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
 641 def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 642                         "oihf\t{$dst, $src2}",
 643                         [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
 644
 645 // FIXME: Provide proper encoding!
 646 def SUB32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 647                      "sr\t{$dst, $src2}",
 648                      [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
 649 def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 650                      "sgr\t{$dst, $src2}",
 651                      [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
 652
 653
 654 let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
 655 // FIXME: Provide proper encoding!
 656 def XOR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 657                      "xr\t{$dst, $src2}",
 658                      [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
 659 def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 660                      "xgr\t{$dst, $src2}",
 661                      [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
 662 }
 663
 664 def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 665                      "xilf\t{$dst, $src2}",
 666                      [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
 667
 668 // FIXME: these 2 instructions seem to require extimm facility
 669 def XOR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 670                          "xilf\t{$dst, $src2}",
 671                          [(set GR64:$dst, (xor GR64:$src1, i64lo32:$src2))]>;
 672 def XOR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 673                          "xihf\t{$dst, $src2}",
 674                          [(set GR64:$dst, (xor GR64:$src1, i64hi32:$src2))]>;
 675
 676 } // Defs = [PSW]
 677
 678 let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
 679 def MUL32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 680                      "msr\t{$dst, $src2}",
 681                      [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
 682 def MUL64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 683                      "msgr\t{$dst, $src2}",
 684                      [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
 685
 686 def MUL64rrP   : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 687                         "mr\t{$dst, $src2}",
 688                         []>;
 689 def UMUL64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 690                          "mlr\t{$dst, $src2}",
 691                          []>;
 692 def UMUL128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 693                         "mlgr\t{$dst, $src2}",
 694                         []>;
 695 }
 696
 697
 698 def MUL32ri16   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 699                          "mhi\t{$dst, $src2}",
 700                          [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
 701 def MUL32ri     : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 702                          "msfi\t{$dst, $src2}",
 703                          [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>;
 704 def MUL64ri16   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 705                          "mghi\t{$dst, $src2}",
 706                          [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
 707 def MUL64ri32   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 708                          "msgfi\t{$dst, $src2}",
 709                          [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>;
 710
 711 def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 712                      "msy\t{$dst, $src2}",
 713                      [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
 714 def MUL64rm : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 715                      "msg\t{$dst, $src2}",
 716                      [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
 717
 718 def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
 719                          "msgfr\t{$dst, $src2}",
 720                          [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
 721
 722 def SDIVREM64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 723                            "dr\t{$dst, $src2}",
 724                            []>;
 725
 726 def SDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 727                            "dsgr\t{$dst, $src2}",
 728                            []>;
 729
 730 def UDIVREM64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 731                            "dlr\t{$dst, $src2}",
 732                            []>;
 733
 734 def UDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 735                            "dlgr\t{$dst, $src2}",
 736                            []>;
 737
 738 } // isTwoAddress = 1
 739
 740 //===----------------------------------------------------------------------===//
 741 // Shifts
 742
 743 let isTwoAddress = 1 in
 744 def SRL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 745                       "srl\t{$src, $amt}",
 746                       [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
 747 def SRL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 748                       "srlg\t{$dst, $src, $amt}",
 749                       [(set GR64:$dst, (srl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 750 def SRLA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 751                       "srlg\t{$dst, $src, $amt}",
 752                       [(set GR64:$dst, (srl GR64:$src, (i32 imm:$amt)))]>;
 753
 754 let isTwoAddress = 1 in
 755 def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 756                       "sll\t{$src, $amt}",
 757                       [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
 758 def SHL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 759                       "sllg\t{$dst, $src, $amt}",
 760                       [(set GR64:$dst, (shl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 761 def SHL64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 762                       "sllg\t{$dst, $src, $amt}",
 763                       [(set GR64:$dst, (shl GR64:$src, (i32 imm:$amt)))]>;
 764
 765
 766 let Defs = [PSW] in {
 767 let isTwoAddress = 1 in
 768 def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 769                       "sra\t{$src, $amt}",
 770                       [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
 771                        (implicit PSW)]>;
 772 def SRA64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 773                       "srag\t{$dst, $src, $amt}",
 774                       [(set GR64:$dst, (sra GR64:$src, (i32 (trunc riaddr:$amt)))),
 775                        (implicit PSW)]>;
 776 def SRA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 777                       "srag\t{$dst, $src, $amt}",
 778                       [(set GR64:$dst, (sra GR64:$src, (i32 imm:$amt))),
 779                        (implicit PSW)]>;
 780 } // Defs = [PSW]
 781
 782 //===----------------------------------------------------------------------===//
 783 // Test instructions (like AND but do not produce any result
 784
 785 // Integer comparisons
 786 let Defs = [PSW] in {
 787 def CMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 788                      "cr\t$src1, $src2",
 789                      [(SystemZcmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 790 def CMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 791                      "cgr\t$src1, $src2",
 792                      [(SystemZcmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 793
 794 def CMP32ri   : Pseudo<(outs), (ins GR32:$src1, s32imm:$src2),
 795                        "cfi\t$src1, $src2",
 796                        [(SystemZcmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 797 def CMP64ri32 : Pseudo<(outs), (ins GR64:$src1, s32imm64:$src2),
 798                        "cgfi\t$src1, $src2",
 799                        [(SystemZcmp GR64:$src1, i64immSExt32:$src2),
 800                         (implicit PSW)]>;
 801
 802 def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 803                      "cy\t$src1, $src2",
 804                      [(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
 805                       (implicit PSW)]>;
 806 def CMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 807                      "cg\t$src1, $src2",
 808                      [(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
 809                       (implicit PSW)]>;
 810
 811 def UCMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 812                       "clr\t$src1, $src2",
 813                       [(SystemZucmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 814 def UCMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 815                       "clgr\t$src1, $src2",
 816                       [(SystemZucmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 817
 818 def UCMP32ri   : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2),
 819                         "clfi\t$src1, $src2",
 820                         [(SystemZucmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 821 def UCMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2),
 822                         "clgfi\t$src1, $src2",
 823                         [(SystemZucmp GR64:$src1, i64immZExt32:$src2),
 824                          (implicit PSW)]>;
 825
 826 def UCMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 827                       "cly\t$src1, $src2",
 828                       [(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
 829                        (implicit PSW)]>;
 830 def UCMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 831                       "clg\t$src1, $src2",
 832                       [(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
 833                        (implicit PSW)]>;
 834
 835 def CMPSX64rr32  : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 836                           "cgfr\t$src1, $src2",
 837                           [(SystemZucmp GR64:$src1, (sext GR32:$src2)),
 838                            (implicit PSW)]>;
 839 def UCMPZX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 840                           "clgfr\t$src1, $src2",
 841                           [(SystemZucmp GR64:$src1, (zext GR32:$src2)),
 842                            (implicit PSW)]>;
 843
 844 def CMPSX64rm32   : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 845                            "cgf\t$src1, $src2",
 846                            [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
 847                             (implicit PSW)]>;
 848 def UCMPZX64rm32  : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 849                            "clgf\t$src1, $src2",
 850                            [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
 851                             (implicit PSW)]>;
 852
 853 // FIXME: Add other crazy ucmp forms
 854
 855 } // Defs = [PSW]
 856
 857 //===----------------------------------------------------------------------===//
 858 // Non-Instruction Patterns.
 859 //===----------------------------------------------------------------------===//
 860
 861 // anyext
 862 def : Pat<(i64 (anyext GR32:$src)),
 863           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
 864
 865 //===----------------------------------------------------------------------===//
 866 // Peepholes.
 867 //===----------------------------------------------------------------------===//
 868
 869 // FIXME: use add/sub tricks with 32678/-32768
 870
 871 // trunc patterns
 872 def : Pat<(i32 (trunc GR64:$src)),
 873           (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
 874
 875 // sext_inreg patterns
 876 def : Pat<(sext_inreg GR64:$src, i32),
 877           (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
 878
 879 // extload patterns
 880 def : Pat<(extloadi32i8  rriaddr:$src), (MOVZX32rm8  rriaddr:$src)>;
 881 def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>;
 882 def : Pat<(extloadi64i8  rriaddr:$src), (MOVZX64rm8  rriaddr:$src)>;
 883 def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
 884 def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
 885
 886 // calls
 887 def : Pat<(SystemZcall (i64 tglobaladdr:$dst)),
 888           (CALLi tglobaladdr:$dst)>;
 889 def : Pat<(SystemZcall (i64 texternalsym:$dst)),
 890           (CALLi texternalsym:$dst)>;
 891
 892 // muls
 893 def : Pat<(mulhs GR32:$src1, GR32:$src2),
 894           (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 895                                                    GR32:$src1, subreg_odd),
 896                                     GR32:$src2),
 897                           subreg_even)>;
 898
 899 def : Pat<(mulhu GR32:$src1, GR32:$src2),
 900           (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 901                                                     GR32:$src1, subreg_odd),
 902                                      GR32:$src2),
 903                           subreg_even)>;
 904 def : Pat<(mulhu GR64:$src1, GR64:$src2),
 905           (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 906                                                      GR64:$src1, subreg_odd),
 907                                       GR64:$src2),
 908                           subreg_even)>;
 909
 910 // divs
 911 // FIXME: Add memory versions
 912 def : Pat<(sdiv GR32:$src1, GR32:$src2),
 913           (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 914                                                        GR32:$src1, subreg_odd),
 915                                          GR32:$src2),
 916                           subreg_odd)>;
 917 def : Pat<(sdiv GR64:$src1, GR64:$src2),
 918           (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 919                                                         GR64:$src1, subreg_odd),
 920                                          GR64:$src2),
 921                           subreg_odd)>;
 922 def : Pat<(udiv GR32:$src1, GR32:$src2),
 923           (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 924                                                        GR32:$src1, subreg_odd),
 925                                          GR32:$src2),
 926                           subreg_odd)>;
 927 def : Pat<(udiv GR64:$src1, GR64:$src2),
 928           (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 929                                                         GR64:$src1, subreg_odd),
 930                                          GR64:$src2),
 931                           subreg_odd)>;
 932
 933 // rems
 934 // FIXME: Add memory versions
 935 def : Pat<(srem GR32:$src1, GR32:$src2),
 936           (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 937                                                        GR32:$src1, subreg_odd),
 938                                          GR32:$src2),
 939                           subreg_even)>;
 940 def : Pat<(srem GR64:$src1, GR64:$src2),
 941           (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 942                                                         GR64:$src1, subreg_odd),
 943                                          GR64:$src2),
 944                           subreg_even)>;
 945 def : Pat<(urem GR32:$src1, GR32:$src2),
 946           (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 947                                                        GR32:$src1, subreg_odd),
 948                                          GR32:$src2),
 949                           subreg_even)>;
 950 def : Pat<(urem GR64:$src1, GR64:$src2),
 951           (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 952                                                         GR64:$src1, subreg_odd),
 953                                          GR64:$src2),
 954                           subreg_even)>;
 955
 956 def : Pat<(i32 imm:$src),
 957           (EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;