lib/Target/SystemZ/SystemZInstrInfo.td

   1 //===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the SystemZ instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // SystemZ Instruction Predicate Definitions.
  16 def IsZ10 : Predicate<"Subtarget.isZ10()">;
  17
  18 include "SystemZInstrFormats.td"
  19
  20 //===----------------------------------------------------------------------===//
  21 // Type Constraints.
  22 //===----------------------------------------------------------------------===//
  23 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
  24 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
  25 class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>;
  26 class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
  27
  28 //===----------------------------------------------------------------------===//
  29 // Type Profiles.
  30 //===----------------------------------------------------------------------===//
  31 def SDT_SystemZCall         : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
  32 def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
  33 def SDT_SystemZCallSeqEnd   : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
  34 def SDT_CmpTest             : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
  35 def SDT_BrCond              : SDTypeProfile<0, 2,
  36                                            [SDTCisVT<0, OtherVT>,
  37                                             SDTCisI8<1>]>;
  38 def SDT_SelectCC            : SDTypeProfile<1, 3,
  39                                            [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  40                                             SDTCisI8<3>]>;
  41 def SDT_Address             : SDTypeProfile<1, 1,
  42                                             [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
  43
  44 //===----------------------------------------------------------------------===//
  45 // SystemZ Specific Node Definitions.
  46 //===----------------------------------------------------------------------===//
  47 def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
  48                      [SDNPHasChain, SDNPOptInFlag]>;
  49 def SystemZcall    : SDNode<"SystemZISD::CALL", SDT_SystemZCall,
  50                      [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
  51 def SystemZcallseq_start :
  52                  SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart,
  53                         [SDNPHasChain, SDNPOutFlag]>;
  54 def SystemZcallseq_end :
  55                  SDNode<"ISD::CALLSEQ_END",   SDT_SystemZCallSeqEnd,
  56                         [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
  57 def SystemZcmp     : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>;
  58 def SystemZucmp    : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>;
  59 def SystemZbrcond  : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
  60                             [SDNPHasChain, SDNPInFlag]>;
  61 def SystemZselect  : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>;
  62 def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
  63
  64
  65 include "SystemZOperands.td"
  66
  67 //===----------------------------------------------------------------------===//
  68 // Instruction list..
  69
  70 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
  71                               "#ADJCALLSTACKDOWN",
  72                               [(SystemZcallseq_start timm:$amt)]>;
  73 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
  74                               "#ADJCALLSTACKUP",
  75                               [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
  76
  77 let usesCustomDAGSchedInserter = 1 in {
  78   def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
  79                         "# Select32 PSEUDO",
  80                         [(set GR32:$dst,
  81                               (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>;
  82   def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
  83                         "# Select64 PSEUDO",
  84                         [(set GR64:$dst,
  85                               (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>;
  86 }
  87
  88
  89 //===----------------------------------------------------------------------===//
  90 //  Control Flow Instructions...
  91 //
  92
  93 // FIXME: Provide proper encoding!
  94 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
  95   def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
  96 }
  97
  98 let isBranch = 1, isTerminator = 1 in {
  99   let isBarrier = 1 in {
 100     def JMP  : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
 101
 102     let isIndirectBranch = 1 in
 103       def JMPr   : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
 104   }
 105
 106   let Uses = [PSW] in {
 107     def JE  : Pseudo<(outs), (ins brtarget:$dst),
 108                      "je\t$dst",
 109                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>;
 110     def JNE : Pseudo<(outs), (ins brtarget:$dst),
 111                      "jne\t$dst",
 112                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>;
 113     def JH  : Pseudo<(outs), (ins brtarget:$dst),
 114                      "jh\t$dst",
 115                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>;
 116     def JL  : Pseudo<(outs), (ins brtarget:$dst),
 117                      "jl\t$dst",
 118                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>;
 119     def JHE : Pseudo<(outs), (ins brtarget:$dst),
 120                      "jhe\t$dst",
 121                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>;
 122     def JLE : Pseudo<(outs), (ins brtarget:$dst),
 123                      "jle\t$dst",
 124                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>;
 125
 126   } // Uses = [PSW]
 127 } // isBranch = 1
 128
 129 //===----------------------------------------------------------------------===//
 130 //  Call Instructions...
 131 //
 132
 133 let isCall = 1 in
 134   // All calls clobber the non-callee saved registers (except R14 which we
 135   // handle separately). Uses for argument registers are added manually.
 136   let Defs = [R0D, R1D, R2D, R3D, R4D, R5D] in {
 137     def CALLi     : Pseudo<(outs), (ins i64imm:$dst, variable_ops),
 138                            "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
 139     def CALLr     : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
 140                            "brasl\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>;
 141   }
 142
 143 //===----------------------------------------------------------------------===//
 144 //  Miscellaneous Instructions.
 145 //
 146
 147 let isReMaterializable = 1 in
 148 // FIXME: Provide imm12 variant
 149 // FIXME: Address should be halfword aligned...
 150 def LA64r  : Pseudo<(outs GR64:$dst), (ins laaddr:$src),
 151                     "lay\t{$dst, $src}",
 152                     [(set GR64:$dst, laaddr:$src)]>;
 153 def LA64rm : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 154                     "larl\t{$dst, $src}",
 155                     [(set GR64:$dst,
 156                           (SystemZpcrelwrapper tglobaladdr:$src))]>;
 157
 158 let neverHasSideEffects = 1 in
 159 def NOP : Pseudo<(outs), (ins), "# no-op", []>;
 160
 161 //===----------------------------------------------------------------------===//
 162 // Move Instructions
 163
 164 // FIXME: Provide proper encoding!
 165 let neverHasSideEffects = 1 in {
 166 def MOV32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 167                      "lr\t{$dst, $src}",
 168                      []>;
 169 def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 170                      "lgr\t{$dst, $src}",
 171                      []>;
 172 def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
 173                      "# MOV128 PSEUDO!\n"
 174                      "\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 175                      "\tlgr\t${dst:subreg_even}, ${src:subreg_even}",
 176                      []>;
 177 def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
 178                      "# MOV64P PSEUDO!\n"
 179                      "\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 180                      "\tlr\t${dst:subreg_even}, ${src:subreg_even}",
 181                      []>;
 182 }
 183
 184 def MOVSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 185                          "lgfr\t{$dst, $src}",
 186                          [(set GR64:$dst, (sext GR32:$src))]>;
 187 def MOVZX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 188                          "llgfr\t{$dst, $src}",
 189                          [(set GR64:$dst, (zext GR32:$src))]>;
 190
 191 // FIXME: Provide proper encoding!
 192 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 193 def MOV32ri16 : Pseudo<(outs GR32:$dst), (ins s16imm:$src),
 194                        "lhi\t{$dst, $src}",
 195                        [(set GR32:$dst, immSExt16:$src)]>;
 196 def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins s16imm64:$src),
 197                        "lghi\t{$dst, $src}",
 198                        [(set GR64:$dst, immSExt16:$src)]>;
 199
 200 def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 201                          "llill\t{$dst, $src}",
 202                          [(set GR64:$dst, i64ll16:$src)]>;
 203 def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 204                          "llilh\t{$dst, $src}",
 205                          [(set GR64:$dst, i64lh16:$src)]>;
 206 def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 207                          "llihl\t{$dst, $src}",
 208                          [(set GR64:$dst, i64hl16:$src)]>;
 209 def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 210                          "llihh\t{$dst, $src}",
 211                          [(set GR64:$dst, i64hh16:$src)]>;
 212
 213 def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins s32imm64:$src),
 214                        "lgfi\t{$dst, $src}",
 215                        [(set GR64:$dst, immSExt32:$src)]>;
 216 def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 217                          "llilf\t{$dst, $src}",
 218                          [(set GR64:$dst, i64lo32:$src)]>;
 219 def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 220                          "llihf\t{$dst, $src}",
 221                          [(set GR64:$dst, i64hi32:$src)]>;
 222 }
 223
 224 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
 225 def MOV32rm : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 226                      "ly\t{$dst, $src}",
 227                      [(set GR32:$dst, (load rriaddr:$src))]>;
 228 def MOV64rm : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 229                      "lg\t{$dst, $src}",
 230                      [(set GR64:$dst, (load rriaddr:$src))]>;
 231
 232 }
 233
 234 def MOV32mr : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 235                      "sty\t{$src, $dst}",
 236                      [(store GR32:$src, rriaddr:$dst)]>;
 237 def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 238                      "stg\t{$src, $dst}",
 239                      [(store GR64:$src, rriaddr:$dst)]>;
 240
 241 // FIXME: displacements here are really 12 bit, not 20!
 242 def MOV8mi    : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src),
 243                        "mviy\t{$dst, $src}",
 244                        [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
 245
 246 def MOV16mi   : Pseudo<(outs), (ins riaddr:$dst, s16imm:$src),
 247                        "mvhhi\t{$dst, $src}",
 248                        [(truncstorei16 (i32 i32immSExt16:$src), riaddr:$dst)]>,
 249                        Requires<[IsZ10]>;
 250 def MOV32mi16 : Pseudo<(outs), (ins riaddr:$dst, s32imm:$src),
 251                        "mvhi\t{$dst, $src}",
 252                        [(store (i32 immSExt16:$src), riaddr:$dst)]>,
 253                        Requires<[IsZ10]>;
 254 def MOV64mi16 : Pseudo<(outs), (ins riaddr:$dst, s32imm64:$src),
 255                        "mvghi\t{$dst, $src}",
 256                        [(store (i64 immSExt16:$src), riaddr:$dst)]>,
 257                        Requires<[IsZ10]>;
 258
 259 // sexts
 260 def MOVSX32rr8  : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 261                          "lbr\t{$dst, $src}",
 262                          [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>;
 263 def MOVSX64rr8  : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 264                          "lgbr\t{$dst, $src}",
 265                          [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>;
 266 def MOVSX32rr16 : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 267                          "lhr\t{$dst, $src}",
 268                          [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>;
 269 def MOVSX64rr16 : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 270                          "lghr\t{$dst, $src}",
 271                          [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>;
 272
 273 // extloads
 274 def MOVSX32rm8  : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 275                          "lb\t{$dst, $src}",
 276                          [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
 277 def MOVSX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 278                          "lhy\t{$dst, $src}",
 279                          [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
 280 def MOVSX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 281                          "lgb\t{$dst, $src}",
 282                          [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
 283 def MOVSX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 284                          "lgh\t{$dst, $src}",
 285                          [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
 286 def MOVSX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 287                          "lgf\t{$dst, $src}",
 288                          [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
 289
 290 def MOVZX32rm8  : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 291                          "llc\t{$dst, $src}",
 292                          [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
 293 def MOVZX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 294                          "llh\t{$dst, $src}",
 295                          [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
 296 def MOVZX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 297                          "llgc\t{$dst, $src}",
 298                          [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
 299 def MOVZX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 300                          "llgh\t{$dst, $src}",
 301                          [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
 302 def MOVZX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 303                          "llgf\t{$dst, $src}",
 304                          [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
 305
 306 // truncstores
 307 // FIXME: Implement 12-bit displacement stuff someday
 308 def MOV32m8r  : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 309                        "stcy\t{$src, $dst}",
 310                        [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
 311
 312 def MOV32m16r : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 313                        "sthy\t{$src, $dst}",
 314                        [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
 315
 316 def MOV64m8r  : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 317                        "stcy\t{$src, $dst}",
 318                        [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
 319
 320 def MOV64m16r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 321                        "sthy\t{$src, $dst}",
 322                        [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
 323
 324 def MOV64m32r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 325                        "sty\t{$src, $dst}",
 326                        [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
 327
 328 // multiple regs moves
 329 // FIXME: should we use multiple arg nodes?
 330 def MOV32mrm  : Pseudo<(outs), (ins riaddr:$dst, GR32:$from, GR32:$to),
 331                        "stmy\t{$from, $to, $dst}",
 332                        []>;
 333 def MOV64mrm  : Pseudo<(outs), (ins riaddr:$dst, GR64:$from, GR64:$to),
 334                        "stmg\t{$from, $to, $dst}",
 335                        []>;
 336 def MOV32rmm  : Pseudo<(outs GR32:$from, GR32:$to), (ins riaddr:$dst),
 337                        "lmy\t{$from, $to, $dst}",
 338                        []>;
 339 def MOV64rmm  : Pseudo<(outs GR64:$from, GR64:$to), (ins riaddr:$dst),
 340                        "lmg\t{$from, $to, $dst}",
 341                        []>;
 342
 343
 344 //===----------------------------------------------------------------------===//
 345 // Arithmetic Instructions
 346
 347 let Defs = [PSW] in {
 348 def NEG32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 349                      "lcr\t{$dst, $src}",
 350                      [(set GR32:$dst, (ineg GR32:$src)),
 351                       (implicit PSW)]>;
 352 def NEG64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 353                      "lcgr\t{$dst, $src}",
 354                      [(set GR64:$dst, (ineg GR64:$src)),
 355                       (implicit PSW)]>;
 356 def NEG64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 357                        "lcgfr\t{$dst, $src}",
 358                        [(set GR64:$dst, (ineg (sext GR32:$src))),
 359                         (implicit PSW)]>;
 360 }
 361
 362 let isTwoAddress = 1 in {
 363
 364 let Defs = [PSW] in {
 365
 366 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
 367 // FIXME: Provide proper encoding!
 368 def ADD32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 369                      "ar\t{$dst, $src2}",
 370                      [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 371                       (implicit PSW)]>;
 372 def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 373                      "agr\t{$dst, $src2}",
 374                      [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
 375                       (implicit PSW)]>;
 376 }
 377
 378 // FIXME: Provide proper encoding!
 379 def ADD32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 380                        "ahi\t{$dst, $src2}",
 381                        [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
 382                         (implicit PSW)]>;
 383 def ADD32ri   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 384                        "afi\t{$dst, $src2}",
 385                        [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
 386                         (implicit PSW)]>;
 387 def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 388                        "aghi\t{$dst, $src2}",
 389                        [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
 390                         (implicit PSW)]>;
 391 def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 392                        "agfi\t{$dst, $src2}",
 393                        [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
 394                         (implicit PSW)]>;
 395
 396 let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
 397 // FIXME: Provide proper encoding!
 398 def AND32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 399                      "nr\t{$dst, $src2}",
 400                      [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
 401 def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 402                      "ngr\t{$dst, $src2}",
 403                      [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
 404 }
 405
 406 // FIXME: Provide proper encoding!
 407 // FIXME: Compute masked bits properly!
 408 def AND32rill16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 409                          "nill\t{$dst, $src2}",
 410                         [(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>;
 411 def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 412                          "nill\t{$dst, $src2}",
 413                          [(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>;
 414
 415 def AND32rilh16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 416                          "nilh\t{$dst, $src2}",
 417                          [(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>;
 418 def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 419                          "nilh\t{$dst, $src2}",
 420                          [(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>;
 421
 422 def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 423                          "nihl\t{$dst, $src2}",
 424                          [(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>;
 425 def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 426                          "nihh\t{$dst, $src2}",
 427                          [(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>;
 428
 429 def AND32ri     : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 430                          "nilf\t{$dst, $src2}",
 431                          [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
 432 def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 433                          "nilf\t{$dst, $src2}",
 434                          [(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>;
 435 def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 436                          "nihf\t{$dst, $src2}",
 437                          [(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>;
 438
 439 let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
 440 // FIXME: Provide proper encoding!
 441 def OR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 442                     "or\t{$dst, $src2}",
 443                     [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
 444 def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 445                     "ogr\t{$dst, $src2}",
 446                     [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
 447 }
 448
 449 def OR32ri16  : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 450                       "oill\t{$dst, $src2}",
 451                       [(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>;
 452 def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 453                       "oilh\t{$dst, $src2}",
 454                       [(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>;
 455 def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 456                     "oilf\t{$dst, $src2}",
 457                     [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
 458
 459 def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 460                         "oill\t{$dst, $src2}",
 461                         [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
 462 def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 463                         "oilh\t{$dst, $src2}",
 464                         [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
 465 def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 466                         "oihl\t{$dst, $src2}",
 467                         [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
 468 def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 469                         "oihh\t{$dst, $src2}",
 470                         [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
 471
 472 def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 473                         "oilf\t{$dst, $src2}",
 474                         [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
 475 def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 476                         "oihf\t{$dst, $src2}",
 477                         [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
 478
 479 // FIXME: Provide proper encoding!
 480 def SUB32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 481                      "sr\t{$dst, $src2}",
 482                      [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
 483 def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 484                      "sgr\t{$dst, $src2}",
 485                      [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
 486
 487
 488 let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
 489 // FIXME: Provide proper encoding!
 490 def XOR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 491                      "xr\t{$dst, $src2}",
 492                      [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
 493 def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 494                      "xgr\t{$dst, $src2}",
 495                      [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
 496 }
 497
 498 def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 499                      "xilf\t{$dst, $src2}",
 500                      [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
 501
 502 } // Defs = [PSW]
 503
 504 let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
 505 def MUL32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 506                      "msr\t{$dst, $src2}",
 507                      [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
 508 def MUL64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 509                      "msgr\t{$dst, $src2}",
 510                      [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
 511
 512 def MUL64rrP   : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 513                         "mr\t{$dst, $src2}",
 514                         []>;
 515 def UMUL64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 516                          "mlr\t{$dst, $src2}",
 517                          []>;
 518 def UMUL128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 519                         "mlgr\t{$dst, $src2}",
 520                         []>;
 521 }
 522
 523
 524 def MUL32ri16   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 525                          "mhi\t{$dst, $src2}",
 526                          [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
 527 def MUL64ri16   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 528                          "mghi\t{$dst, $src2}",
 529                          [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
 530
 531 def MUL32ri     : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 532                          "msfi\t{$dst, $src2}",
 533                          [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>,
 534                          Requires<[IsZ10]>;
 535 def MUL64ri32   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 536                          "msgfi\t{$dst, $src2}",
 537                          [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
 538                          Requires<[IsZ10]>;
 539
 540 def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 541                      "msy\t{$dst, $src2}",
 542                      [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
 543 def MUL64rm : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 544                      "msg\t{$dst, $src2}",
 545                      [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
 546
 547 def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
 548                          "msgfr\t{$dst, $src2}",
 549                          [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
 550
 551 def SDIVREM64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 552                            "dr\t{$dst, $src2}",
 553                            []>;
 554
 555 def SDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 556                            "dsgr\t{$dst, $src2}",
 557                            []>;
 558
 559 def UDIVREM64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 560                            "dlr\t{$dst, $src2}",
 561                            []>;
 562
 563 def UDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 564                            "dlgr\t{$dst, $src2}",
 565                            []>;
 566
 567 } // isTwoAddress = 1
 568
 569 //===----------------------------------------------------------------------===//
 570 // Shifts
 571
 572 let isTwoAddress = 1 in
 573 def SRL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 574                       "srl\t{$src, $amt}",
 575                       [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
 576 def SRL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 577                       "srlg\t{$dst, $src, $amt}",
 578                       [(set GR64:$dst, (srl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 579 def SRLA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 580                       "srlg\t{$dst, $src, $amt}",
 581                       [(set GR64:$dst, (srl GR64:$src, (i32 imm:$amt)))]>;
 582
 583 let isTwoAddress = 1 in
 584 def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 585                       "sll\t{$src, $amt}",
 586                       [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
 587 def SHL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 588                       "sllg\t{$dst, $src, $amt}",
 589                       [(set GR64:$dst, (shl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 590 def SHL64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 591                       "sllg\t{$dst, $src, $amt}",
 592                       [(set GR64:$dst, (shl GR64:$src, (i32 imm:$amt)))]>;
 593
 594 let Defs = [PSW] in {
 595 let isTwoAddress = 1 in
 596 def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 597                       "sra\t{$src, $amt}",
 598                       [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
 599                        (implicit PSW)]>;
 600 def SRA64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 601                       "srag\t{$dst, $src, $amt}",
 602                       [(set GR64:$dst, (sra GR64:$src, (i32 (trunc riaddr:$amt)))),
 603                        (implicit PSW)]>;
 604 def SRA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 605                       "srag\t{$dst, $src, $amt}",
 606                       [(set GR64:$dst, (sra GR64:$src, (i32 imm:$amt))),
 607                        (implicit PSW)]>;
 608 } // Defs = [PSW]
 609
 610 let isTwoAddress = 1 in
 611 def ROTL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 612                        "rll\t{$src, $amt}",
 613                        [(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>;
 614 def ROTL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 615                        "rllg\t{$dst, $src, $amt}",
 616                        [(set GR64:$dst, (rotl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 617 def ROTL64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 618                        "rllg\t{$dst, $src, $amt}",
 619                        [(set GR64:$dst, (rotl GR64:$src, (i32 imm:$amt)))]>;
 620
 621 //===----------------------------------------------------------------------===//
 622 // Test instructions (like AND but do not produce any result
 623
 624 // Integer comparisons
 625 let Defs = [PSW] in {
 626 def CMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 627                      "cr\t$src1, $src2",
 628                      [(SystemZcmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 629 def CMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 630                      "cgr\t$src1, $src2",
 631                      [(SystemZcmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 632
 633 def CMP32ri   : Pseudo<(outs), (ins GR32:$src1, s32imm:$src2),
 634                        "cfi\t$src1, $src2",
 635                        [(SystemZcmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 636 def CMP64ri32 : Pseudo<(outs), (ins GR64:$src1, s32imm64:$src2),
 637                        "cgfi\t$src1, $src2",
 638                        [(SystemZcmp GR64:$src1, i64immSExt32:$src2),
 639                         (implicit PSW)]>;
 640
 641 def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 642                      "cy\t$src1, $src2",
 643                      [(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
 644                       (implicit PSW)]>;
 645 def CMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 646                      "cg\t$src1, $src2",
 647                      [(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
 648                       (implicit PSW)]>;
 649
 650 def UCMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 651                       "clr\t$src1, $src2",
 652                       [(SystemZucmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 653 def UCMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 654                       "clgr\t$src1, $src2",
 655                       [(SystemZucmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 656
 657 def UCMP32ri   : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2),
 658                         "clfi\t$src1, $src2",
 659                         [(SystemZucmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 660 def UCMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2),
 661                         "clgfi\t$src1, $src2",
 662                         [(SystemZucmp GR64:$src1, i64immZExt32:$src2),
 663                          (implicit PSW)]>;
 664
 665 def UCMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 666                       "cly\t$src1, $src2",
 667                       [(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
 668                        (implicit PSW)]>;
 669 def UCMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 670                       "clg\t$src1, $src2",
 671                       [(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
 672                        (implicit PSW)]>;
 673
 674 def CMPSX64rr32  : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 675                           "cgfr\t$src1, $src2",
 676                           [(SystemZucmp GR64:$src1, (sext GR32:$src2)),
 677                            (implicit PSW)]>;
 678 def UCMPZX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 679                           "clgfr\t$src1, $src2",
 680                           [(SystemZucmp GR64:$src1, (zext GR32:$src2)),
 681                            (implicit PSW)]>;
 682
 683 def CMPSX64rm32   : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 684                            "cgf\t$src1, $src2",
 685                            [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
 686                             (implicit PSW)]>;
 687 def UCMPZX64rm32  : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 688                            "clgf\t$src1, $src2",
 689                            [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
 690                             (implicit PSW)]>;
 691
 692 // FIXME: Add other crazy ucmp forms
 693
 694 } // Defs = [PSW]
 695
 696 //===----------------------------------------------------------------------===//
 697 // Non-Instruction Patterns.
 698 //===----------------------------------------------------------------------===//
 699
 700 // JumpTable
 701 def : Pat<(SystemZpcrelwrapper tjumptable:$src), (LA64rm tjumptable:$src)>;
 702
 703 // anyext
 704 def : Pat<(i64 (anyext GR32:$src)),
 705           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
 706
 707 // calls
 708 def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), (CALLi tglobaladdr:$dst)>;
 709 def : Pat<(SystemZcall (i64 texternalsym:$dst)), (CALLi texternalsym:$dst)>;
 710
 711 //===----------------------------------------------------------------------===//
 712 // Peepholes.
 713 //===----------------------------------------------------------------------===//
 714
 715 // FIXME: use add/sub tricks with 32678/-32768
 716
 717 // Arbitrary immediate support.  Implement in terms of LLIHF/OILF.
 718 def : Pat<(i64 imm:$imm),
 719           (OR64rilo32 (MOV64rihi32 (HI32 imm:$imm)), (LO32 imm:$imm))>;
 720
 721 // trunc patterns
 722 def : Pat<(i32 (trunc GR64:$src)),
 723           (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
 724
 725 // sext_inreg patterns
 726 def : Pat<(sext_inreg GR64:$src, i32),
 727           (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
 728
 729 // extload patterns
 730 def : Pat<(extloadi32i8  rriaddr:$src), (MOVZX32rm8  rriaddr:$src)>;
 731 def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>;
 732 def : Pat<(extloadi64i8  rriaddr:$src), (MOVZX64rm8  rriaddr:$src)>;
 733 def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
 734 def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
 735
 736 // muls
 737 def : Pat<(mulhs GR32:$src1, GR32:$src2),
 738           (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 739                                                    GR32:$src1, subreg_odd),
 740                                     GR32:$src2),
 741                           subreg_even)>;
 742
 743 def : Pat<(mulhu GR32:$src1, GR32:$src2),
 744           (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 745                                                     GR32:$src1, subreg_odd),
 746                                      GR32:$src2),
 747                           subreg_even)>;
 748 def : Pat<(mulhu GR64:$src1, GR64:$src2),
 749           (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 750                                                      GR64:$src1, subreg_odd),
 751                                       GR64:$src2),
 752                           subreg_even)>;
 753
 754 // divs
 755 // FIXME: Add memory versions
 756 def : Pat<(sdiv GR32:$src1, GR32:$src2),
 757           (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 758                                                        GR32:$src1, subreg_odd),
 759                                          GR32:$src2),
 760                           subreg_odd)>;
 761 def : Pat<(sdiv GR64:$src1, GR64:$src2),
 762           (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 763                                                         GR64:$src1, subreg_odd),
 764                                          GR64:$src2),
 765                           subreg_odd)>;
 766 def : Pat<(udiv GR32:$src1, GR32:$src2),
 767           (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 768                                                        GR32:$src1, subreg_odd),
 769                                          GR32:$src2),
 770                           subreg_odd)>;
 771 def : Pat<(udiv GR64:$src1, GR64:$src2),
 772           (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 773                                                         GR64:$src1, subreg_odd),
 774                                          GR64:$src2),
 775                           subreg_odd)>;
 776
 777 // rems
 778 // FIXME: Add memory versions
 779 def : Pat<(srem GR32:$src1, GR32:$src2),
 780           (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 781                                                        GR32:$src1, subreg_odd),
 782                                          GR32:$src2),
 783                           subreg_even)>;
 784 def : Pat<(srem GR64:$src1, GR64:$src2),
 785           (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 786                                                         GR64:$src1, subreg_odd),
 787                                          GR64:$src2),
 788                           subreg_even)>;
 789 def : Pat<(urem GR32:$src1, GR32:$src2),
 790           (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 791                                                        GR32:$src1, subreg_odd),
 792                                          GR32:$src2),
 793                           subreg_even)>;
 794 def : Pat<(urem GR64:$src1, GR64:$src2),
 795           (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 796                                                         GR64:$src1, subreg_odd),
 797                                          GR64:$src2),
 798                           subreg_even)>;
 799
 800 def : Pat<(i32 imm:$src),
 801           (EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;