lib/Target/SystemZ/SystemZInstrInfo.td

   1 //===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the SystemZ instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // SystemZ Instruction Predicate Definitions.
  16 def IsZ10 : Predicate<"Subtarget.isZ10()">;
  17
  18 include "SystemZInstrFormats.td"
  19
  20 //===----------------------------------------------------------------------===//
  21 // Type Constraints.
  22 //===----------------------------------------------------------------------===//
  23 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
  24 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
  25 class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>;
  26 class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
  27
  28 //===----------------------------------------------------------------------===//
  29 // Type Profiles.
  30 //===----------------------------------------------------------------------===//
  31 def SDT_SystemZCall         : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
  32 def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
  33 def SDT_SystemZCallSeqEnd   : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
  34 def SDT_CmpTest             : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
  35 def SDT_BrCond              : SDTypeProfile<0, 2,
  36                                            [SDTCisVT<0, OtherVT>,
  37                                             SDTCisI8<1>]>;
  38 def SDT_SelectCC            : SDTypeProfile<1, 3,
  39                                            [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  40                                             SDTCisI8<3>]>;
  41 def SDT_Address             : SDTypeProfile<1, 1,
  42                                             [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
  43
  44 //===----------------------------------------------------------------------===//
  45 // SystemZ Specific Node Definitions.
  46 //===----------------------------------------------------------------------===//
  47 def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
  48                      [SDNPHasChain, SDNPOptInFlag]>;
  49 def SystemZcall    : SDNode<"SystemZISD::CALL", SDT_SystemZCall,
  50                      [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
  51 def SystemZcallseq_start :
  52                  SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart,
  53                         [SDNPHasChain, SDNPOutFlag]>;
  54 def SystemZcallseq_end :
  55                  SDNode<"ISD::CALLSEQ_END",   SDT_SystemZCallSeqEnd,
  56                         [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
  57 def SystemZcmp     : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>;
  58 def SystemZucmp    : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>;
  59 def SystemZbrcond  : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
  60                             [SDNPHasChain, SDNPInFlag]>;
  61 def SystemZselect  : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>;
  62 def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
  63
  64 //===----------------------------------------------------------------------===//
  65 // Instruction Pattern Stuff.
  66 //===----------------------------------------------------------------------===//
  67
  68 // SystemZ specific condition code. These correspond to CondCode in
  69 // SystemZ.h. They must be kept in synch.
  70 def SYSTEMZ_COND_E  : PatLeaf<(i8 0)>;
  71 def SYSTEMZ_COND_NE : PatLeaf<(i8 1)>;
  72 def SYSTEMZ_COND_H  : PatLeaf<(i8 2)>;
  73 def SYSTEMZ_COND_L  : PatLeaf<(i8 3)>;
  74 def SYSTEMZ_COND_HE : PatLeaf<(i8 4)>;
  75 def SYSTEMZ_COND_LE : PatLeaf<(i8 5)>;
  76
  77 def LL16 : SDNodeXForm<imm, [{
  78   // Transformation function: return low 16 bits.
  79   return getI16Imm(N->getZExtValue() & 0x000000000000FFFFULL);
  80 }]>;
  81
  82 def LH16 : SDNodeXForm<imm, [{
  83   // Transformation function: return bits 16-31.
  84   return getI16Imm((N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16);
  85 }]>;
  86
  87 def HL16 : SDNodeXForm<imm, [{
  88   // Transformation function: return bits 32-47.
  89   return getI16Imm((N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32);
  90 }]>;
  91
  92 def HH16 : SDNodeXForm<imm, [{
  93   // Transformation function: return bits 48-63.
  94   return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48);
  95 }]>;
  96
  97 def LO32 : SDNodeXForm<imm, [{
  98   // Transformation function: return low 32 bits.
  99   return getI32Imm(N->getZExtValue() & 0x00000000FFFFFFFFULL);
 100 }]>;
 101
 102 def HI32 : SDNodeXForm<imm, [{
 103   // Transformation function: return bits 32-63.
 104   return getI32Imm(N->getZExtValue() >> 32);
 105 }]>;
 106
 107 def i64ll16 : PatLeaf<(imm), [{
 108   // i64ll16 predicate - true if the 64-bit immediate has only rightmost 16
 109   // bits set.
 110   return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue());
 111 }], LL16>;
 112
 113 def i64lh16 : PatLeaf<(imm), [{
 114   // i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set.
 115   return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue());
 116 }], LH16>;
 117
 118 def i64hl16 : PatLeaf<(i64 imm), [{
 119   // i64hl16 predicate - true if the 64-bit immediate has only bits 32-47 set.
 120   return ((N->getZExtValue() & 0x0000FFFF00000000ULL) == N->getZExtValue());
 121 }], HL16>;
 122
 123 def i64hh16 : PatLeaf<(i64 imm), [{
 124   // i64hh16 predicate - true if the 64-bit immediate has only bits 48-63 set.
 125   return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue());
 126 }], HH16>;
 127
 128 def immSExt16 : PatLeaf<(imm), [{
 129   // immSExt16 predicate - true if the immediate fits in a 16-bit sign extended
 130   // field.
 131   if (N->getValueType(0) == MVT::i64) {
 132     uint64_t val = N->getZExtValue();
 133     return ((int64_t)val == (int16_t)val);
 134   } else if (N->getValueType(0) == MVT::i32) {
 135     uint32_t val = N->getZExtValue();
 136     return ((int32_t)val == (int16_t)val);
 137   }
 138
 139   return false;
 140 }]>;
 141
 142 def immSExt32 : PatLeaf<(i64 imm), [{
 143   // immSExt32 predicate - true if the immediate fits in a 32-bit sign extended
 144   // field.
 145   uint64_t val = N->getZExtValue();
 146   return ((int64_t)val == (int32_t)val);
 147 }]>;
 148
 149 def i64lo32 : PatLeaf<(i64 imm), [{
 150   // i64lo32 predicate - true if the 64-bit immediate has only rightmost 32
 151   // bits set.
 152   return ((N->getZExtValue() & 0x00000000FFFFFFFFULL) == N->getZExtValue());
 153 }], LO32>;
 154
 155 def i64hi32 : PatLeaf<(i64 imm), [{
 156   // i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set.
 157   return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue());
 158 }], HI32>;
 159
 160 def i32immSExt8  : PatLeaf<(i32 imm), [{
 161   // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit
 162   // sign extended field.
 163   return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
 164 }]>;
 165
 166 def i32immSExt16 : PatLeaf<(i32 imm), [{
 167   // i32immSExt16 predicate - True if the 32-bit immediate fits in a 16-bit
 168   // sign extended field.
 169   return (int32_t)N->getZExtValue() == (int16_t)N->getZExtValue();
 170 }]>;
 171
 172 def i64immSExt32 : PatLeaf<(i64 imm), [{
 173   // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
 174   // sign extended field.
 175   return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue();
 176 }]>;
 177
 178 def i64immZExt32 : PatLeaf<(i64 imm), [{
 179   // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
 180   // zero extended field.
 181   return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue();
 182 }]>;
 183
 184 // extloads
 185 def extloadi32i8   : PatFrag<(ops node:$ptr), (i32 (extloadi8  node:$ptr))>;
 186 def extloadi32i16  : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>;
 187 def extloadi64i8   : PatFrag<(ops node:$ptr), (i64 (extloadi8  node:$ptr))>;
 188 def extloadi64i16  : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
 189 def extloadi64i32  : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
 190
 191 def sextloadi32i8   : PatFrag<(ops node:$ptr), (i32 (sextloadi8  node:$ptr))>;
 192 def sextloadi32i16  : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>;
 193 def sextloadi64i8   : PatFrag<(ops node:$ptr), (i64 (sextloadi8  node:$ptr))>;
 194 def sextloadi64i16  : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
 195 def sextloadi64i32  : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
 196
 197 def zextloadi32i8   : PatFrag<(ops node:$ptr), (i32 (zextloadi8  node:$ptr))>;
 198 def zextloadi32i16  : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>;
 199 def zextloadi64i8   : PatFrag<(ops node:$ptr), (i64 (zextloadi8  node:$ptr))>;
 200 def zextloadi64i16  : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
 201 def zextloadi64i32  : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
 202
 203 // A couple of more descriptive operand definitions.
 204 // 32-bits but only 8 bits are significant.
 205 def i32i8imm  : Operand<i32>;
 206 // 32-bits but only 16 bits are significant.
 207 def i32i16imm : Operand<i32>;
 208 // 64-bits but only 32 bits are significant.
 209 def i64i32imm : Operand<i64>;
 210 // Branch targets have OtherVT type.
 211 def brtarget : Operand<OtherVT>;
 212
 213 // Unigned i12
 214 def u12imm : Operand<i32> {
 215   let PrintMethod = "printU16ImmOperand";
 216 }
 217 // Signed i16
 218 def s16imm : Operand<i32> {
 219   let PrintMethod = "printS16ImmOperand";
 220 }
 221 def s16imm64 : Operand<i64> {
 222   let PrintMethod = "printS16ImmOperand";
 223 }
 224 // Signed i20
 225 def s20imm : Operand<i32> {
 226   let PrintMethod = "printS20ImmOperand";
 227 }
 228 def s20imm64 : Operand<i64> {
 229   let PrintMethod = "printS20ImmOperand";
 230 }
 231 // Signed i32
 232 def s32imm : Operand<i32> {
 233   let PrintMethod = "printS32ImmOperand";
 234 }
 235 def s32imm64 : Operand<i64> {
 236   let PrintMethod = "printS32ImmOperand";
 237 }
 238
 239 //===----------------------------------------------------------------------===//
 240 // SystemZ Operand Definitions.
 241 //===----------------------------------------------------------------------===//
 242
 243 // Address operands
 244
 245 // riaddr := reg + imm
 246 def riaddr32 : Operand<i32>,
 247                ComplexPattern<i32, 2, "SelectAddrRI32", []> {
 248   let PrintMethod = "printRIAddrOperand";
 249   let MIOperandInfo = (ops ADDR32:$base, u12imm:$disp);
 250 }
 251
 252 def riaddr : Operand<i64>,
 253              ComplexPattern<i64, 2, "SelectAddrRI", []> {
 254   let PrintMethod = "printRIAddrOperand";
 255   let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp);
 256 }
 257
 258 //===----------------------------------------------------------------------===//
 259
 260 // rriaddr := reg + reg + imm
 261 def rriaddr : Operand<i64>,
 262               ComplexPattern<i64, 3, "SelectAddrRRI", [], []> {
 263   let PrintMethod = "printRRIAddrOperand";
 264   let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
 265 }
 266 def laaddr : Operand<i64>,
 267              ComplexPattern<i64, 3, "SelectLAAddr", [add, sub, or, frameindex], []> {
 268   let PrintMethod = "printRRIAddrOperand";
 269   let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index);
 270 }
 271
 272 //===----------------------------------------------------------------------===//
 273 // Instruction list..
 274
 275 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
 276                               "#ADJCALLSTACKDOWN",
 277                               [(SystemZcallseq_start timm:$amt)]>;
 278 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
 279                               "#ADJCALLSTACKUP",
 280                               [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
 281
 282 let usesCustomDAGSchedInserter = 1 in {
 283   def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
 284                         "# Select32 PSEUDO",
 285                         [(set GR32:$dst,
 286                               (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>;
 287   def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
 288                         "# Select64 PSEUDO",
 289                         [(set GR64:$dst,
 290                               (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>;
 291 }
 292
 293
 294 //===----------------------------------------------------------------------===//
 295 //  Control Flow Instructions...
 296 //
 297
 298 // FIXME: Provide proper encoding!
 299 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
 300   def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
 301 }
 302
 303 let isBranch = 1, isTerminator = 1 in {
 304   let isBarrier = 1 in
 305     def JMP  : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
 306
 307   let Uses = [PSW] in {
 308     def JE  : Pseudo<(outs), (ins brtarget:$dst),
 309                      "je\t$dst",
 310                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>;
 311     def JNE : Pseudo<(outs), (ins brtarget:$dst),
 312                      "jne\t$dst",
 313                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>;
 314     def JH  : Pseudo<(outs), (ins brtarget:$dst),
 315                      "jh\t$dst",
 316                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>;
 317     def JL  : Pseudo<(outs), (ins brtarget:$dst),
 318                      "jl\t$dst",
 319                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>;
 320     def JHE : Pseudo<(outs), (ins brtarget:$dst),
 321                      "jhe\t$dst",
 322                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>;
 323     def JLE : Pseudo<(outs), (ins brtarget:$dst),
 324                      "jle\t$dst",
 325                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>;
 326
 327   } // Uses = [PSW]
 328 } // isBranch = 1
 329
 330 //===----------------------------------------------------------------------===//
 331 //  Call Instructions...
 332 //
 333
 334 let isCall = 1 in
 335   // All calls clobber the non-callee saved registers (except R14 which we
 336   // handle separately). Uses for argument registers are added manually.
 337   let Defs = [R0D, R1D, R2D, R3D, R4D, R5D] in {
 338     def CALLi     : Pseudo<(outs), (ins i64imm:$dst, variable_ops),
 339                            "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
 340     def CALLr     : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
 341                            "brasl\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>;
 342   }
 343
 344 //===----------------------------------------------------------------------===//
 345 //  Miscellaneous Instructions.
 346 //
 347
 348 let isReMaterializable = 1 in
 349 // FIXME: Provide imm12 variant
 350 // FIXME: Address should be halfword aligned...
 351 def LA64r  : Pseudo<(outs GR64:$dst), (ins laaddr:$src),
 352                     "lay\t{$dst, $src}",
 353                     [(set GR64:$dst, laaddr:$src)]>;
 354 def LA64rm : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 355                     "larl\t{$dst, $src}",
 356                     [(set GR64:$dst,
 357                           (SystemZpcrelwrapper tglobaladdr:$src))]>;
 358
 359 let neverHasSideEffects = 1 in
 360 def NOP : Pseudo<(outs), (ins), "# no-op", []>;
 361
 362 //===----------------------------------------------------------------------===//
 363 // Move Instructions
 364
 365 // FIXME: Provide proper encoding!
 366 let neverHasSideEffects = 1 in {
 367 def MOV32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 368                      "lr\t{$dst, $src}",
 369                      []>;
 370 def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 371                      "lgr\t{$dst, $src}",
 372                      []>;
 373 def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
 374                      "# MOV128 PSEUDO!\n"
 375                      "\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 376                      "\tlgr\t${dst:subreg_even}, ${src:subreg_even}",
 377                      []>;
 378 def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
 379                      "# MOV64P PSEUDO!\n"
 380                      "\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 381                      "\tlr\t${dst:subreg_even}, ${src:subreg_even}",
 382                      []>;
 383 }
 384
 385 def MOVSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 386                          "lgfr\t{$dst, $src}",
 387                          [(set GR64:$dst, (sext GR32:$src))]>;
 388 def MOVZX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 389                          "llgfr\t{$dst, $src}",
 390                          [(set GR64:$dst, (zext GR32:$src))]>;
 391
 392 // FIXME: Provide proper encoding!
 393 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 394 def MOV32ri16 : Pseudo<(outs GR32:$dst), (ins s16imm:$src),
 395                        "lhi\t{$dst, $src}",
 396                        [(set GR32:$dst, immSExt16:$src)]>;
 397 def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins s16imm64:$src),
 398                        "lghi\t{$dst, $src}",
 399                        [(set GR64:$dst, immSExt16:$src)]>;
 400
 401 def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 402                          "llill\t{$dst, $src}",
 403                          [(set GR64:$dst, i64ll16:$src)]>;
 404 def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 405                          "llilh\t{$dst, $src}",
 406                          [(set GR64:$dst, i64lh16:$src)]>;
 407 def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 408                          "llihl\t{$dst, $src}",
 409                          [(set GR64:$dst, i64hl16:$src)]>;
 410 def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 411                          "llihh\t{$dst, $src}",
 412                          [(set GR64:$dst, i64hh16:$src)]>;
 413
 414 def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins s32imm64:$src),
 415                        "lgfi\t{$dst, $src}",
 416                        [(set GR64:$dst, immSExt32:$src)]>;
 417 def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 418                          "llilf\t{$dst, $src}",
 419                          [(set GR64:$dst, i64lo32:$src)]>;
 420 def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 421                          "llihf\t{$dst, $src}",
 422                          [(set GR64:$dst, i64hi32:$src)]>;
 423 }
 424
 425 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
 426 def MOV32rm : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 427                      "ly\t{$dst, $src}",
 428                      [(set GR32:$dst, (load rriaddr:$src))]>;
 429 def MOV64rm : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 430                      "lg\t{$dst, $src}",
 431                      [(set GR64:$dst, (load rriaddr:$src))]>;
 432
 433 }
 434
 435 def MOV32mr : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 436                      "sty\t{$src, $dst}",
 437                      [(store GR32:$src, rriaddr:$dst)]>;
 438 def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 439                      "stg\t{$src, $dst}",
 440                      [(store GR64:$src, rriaddr:$dst)]>;
 441
 442 // FIXME: displacements here are really 12 bit, not 20!
 443 def MOV8mi    : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src),
 444                        "mviy\t{$dst, $src}",
 445                        [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
 446
 447 def MOV16mi   : Pseudo<(outs), (ins riaddr:$dst, s16imm:$src),
 448                        "mvhhi\t{$dst, $src}",
 449                        [(truncstorei16 (i32 i32immSExt16:$src), riaddr:$dst)]>,
 450                        Requires<[IsZ10]>;
 451 def MOV32mi16 : Pseudo<(outs), (ins riaddr:$dst, s32imm:$src),
 452                        "mvhi\t{$dst, $src}",
 453                        [(store (i32 immSExt16:$src), riaddr:$dst)]>,
 454                        Requires<[IsZ10]>;
 455 def MOV64mi16 : Pseudo<(outs), (ins riaddr:$dst, s32imm64:$src),
 456                        "mvghi\t{$dst, $src}",
 457                        [(store (i64 immSExt16:$src), riaddr:$dst)]>,
 458                        Requires<[IsZ10]>;
 459
 460 // sexts
 461 def MOVSX32rr8  : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 462                          "lbr\t{$dst, $src}",
 463                          [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>;
 464 def MOVSX64rr8  : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 465                          "lgbr\t{$dst, $src}",
 466                          [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>;
 467 def MOVSX32rr16 : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 468                          "lhr\t{$dst, $src}",
 469                          [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>;
 470 def MOVSX64rr16 : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 471                          "lghr\t{$dst, $src}",
 472                          [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>;
 473
 474 // extloads
 475 def MOVSX32rm8  : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 476                          "lb\t{$dst, $src}",
 477                          [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
 478 def MOVSX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 479                          "lhy\t{$dst, $src}",
 480                          [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
 481 def MOVSX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 482                          "lgb\t{$dst, $src}",
 483                          [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
 484 def MOVSX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 485                          "lgh\t{$dst, $src}",
 486                          [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
 487 def MOVSX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 488                          "lgf\t{$dst, $src}",
 489                          [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
 490
 491 def MOVZX32rm8  : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 492                          "llc\t{$dst, $src}",
 493                          [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
 494 def MOVZX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 495                          "llh\t{$dst, $src}",
 496                          [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
 497 def MOVZX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 498                          "llgc\t{$dst, $src}",
 499                          [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
 500 def MOVZX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 501                          "llgh\t{$dst, $src}",
 502                          [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
 503 def MOVZX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 504                          "llgf\t{$dst, $src}",
 505                          [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
 506
 507 // truncstores
 508 // FIXME: Implement 12-bit displacement stuff someday
 509 def MOV32m8r  : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 510                        "stcy\t{$src, $dst}",
 511                        [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
 512
 513 def MOV32m16r : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 514                        "sthy\t{$src, $dst}",
 515                        [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
 516
 517 def MOV64m8r  : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 518                        "stcy\t{$src, $dst}",
 519                        [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
 520
 521 def MOV64m16r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 522                        "sthy\t{$src, $dst}",
 523                        [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
 524
 525 def MOV64m32r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 526                        "sty\t{$src, $dst}",
 527                        [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
 528
 529 // multiple regs moves
 530 // FIXME: should we use multiple arg nodes?
 531 def MOV32mrm  : Pseudo<(outs), (ins riaddr:$dst, GR32:$from, GR32:$to),
 532                        "stmy\t{$from, $to, $dst}",
 533                        []>;
 534 def MOV64mrm  : Pseudo<(outs), (ins riaddr:$dst, GR64:$from, GR64:$to),
 535                        "stmg\t{$from, $to, $dst}",
 536                        []>;
 537 def MOV32rmm  : Pseudo<(outs GR32:$from, GR32:$to), (ins riaddr:$dst),
 538                        "lmy\t{$from, $to, $dst}",
 539                        []>;
 540 def MOV64rmm  : Pseudo<(outs GR64:$from, GR64:$to), (ins riaddr:$dst),
 541                        "lmg\t{$from, $to, $dst}",
 542                        []>;
 543
 544
 545 //===----------------------------------------------------------------------===//
 546 // Arithmetic Instructions
 547
 548 let isTwoAddress = 1 in {
 549
 550 let Defs = [PSW] in {
 551
 552 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
 553 // FIXME: Provide proper encoding!
 554 def ADD32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 555                      "ar\t{$dst, $src2}",
 556                      [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 557                       (implicit PSW)]>;
 558 def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 559                      "agr\t{$dst, $src2}",
 560                      [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
 561                       (implicit PSW)]>;
 562 }
 563
 564 // FIXME: Provide proper encoding!
 565 def ADD32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 566                        "ahi\t{$dst, $src2}",
 567                        [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
 568                         (implicit PSW)]>;
 569 def ADD32ri   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 570                        "afi\t{$dst, $src2}",
 571                        [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
 572                         (implicit PSW)]>;
 573 def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 574                        "aghi\t{$dst, $src2}",
 575                        [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
 576                         (implicit PSW)]>;
 577 def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 578                        "agfi\t{$dst, $src2}",
 579                        [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
 580                         (implicit PSW)]>;
 581
 582 let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
 583 // FIXME: Provide proper encoding!
 584 def AND32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 585                      "nr\t{$dst, $src2}",
 586                      [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
 587 def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 588                      "ngr\t{$dst, $src2}",
 589                      [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
 590 }
 591
 592 // FIXME: Provide proper encoding!
 593 def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 594                          "nill\t{$dst, $src2}",
 595                          [(set GR64:$dst, (and GR64:$src1, i64ll16:$src2))]>;
 596 def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 597                          "nilh\t{$dst, $src2}",
 598                          [(set GR64:$dst, (and GR64:$src1, i64lh16:$src2))]>;
 599 def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 600                          "nihl\t{$dst, $src2}",
 601                          [(set GR64:$dst, (and GR64:$src1, i64hl16:$src2))]>;
 602 def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 603                          "nihh\t{$dst, $src2}",
 604                          [(set GR64:$dst, (and GR64:$src1, i64hh16:$src2))]>;
 605 // FIXME: these 2 instructions seem to require extimm facility
 606 def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 607                          "nilf\t{$dst, $src2}",
 608                          [(set GR64:$dst, (and GR64:$src1, i64lo32:$src2))]>;
 609 def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 610                          "nihf\t{$dst, $src2}",
 611                          [(set GR64:$dst, (and GR64:$src1, i64hi32:$src2))]>;
 612
 613 let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
 614 // FIXME: Provide proper encoding!
 615 def OR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 616                     "or\t{$dst, $src2}",
 617                     [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
 618 def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 619                     "ogr\t{$dst, $src2}",
 620                     [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
 621 }
 622
 623 def OR32ri16  : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2),
 624                       "oill\t{$dst, $src2}",
 625                       [(set GR32:$dst, (or GR32:$src1, i64ll16:$src2))]>;
 626 def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2),
 627                       "oilh\t{$dst, $src2}",
 628                       [(set GR32:$dst, (or GR32:$src1, i64lh16:$src2))]>;
 629 def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 630                     "oilf\t{$dst, $src2}",
 631                     [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
 632
 633 def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 634                         "oill\t{$dst, $src2}",
 635                         [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
 636 def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 637                         "oilh\t{$dst, $src2}",
 638                         [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
 639 def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 640                         "oihl\t{$dst, $src2}",
 641                         [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
 642 def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 643                         "oihh\t{$dst, $src2}",
 644                         [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
 645
 646 def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 647                         "oilf\t{$dst, $src2}",
 648                         [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
 649 def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 650                         "oihf\t{$dst, $src2}",
 651                         [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
 652
 653 // FIXME: Provide proper encoding!
 654 def SUB32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 655                      "sr\t{$dst, $src2}",
 656                      [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
 657 def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 658                      "sgr\t{$dst, $src2}",
 659                      [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
 660
 661
 662 let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
 663 // FIXME: Provide proper encoding!
 664 def XOR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 665                      "xr\t{$dst, $src2}",
 666                      [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
 667 def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 668                      "xgr\t{$dst, $src2}",
 669                      [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
 670 }
 671
 672 def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 673                      "xilf\t{$dst, $src2}",
 674                      [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
 675
 676 // FIXME: these 2 instructions seem to require extimm facility
 677 def XOR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 678                          "xilf\t{$dst, $src2}",
 679                          [(set GR64:$dst, (xor GR64:$src1, i64lo32:$src2))]>;
 680 def XOR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 681                          "xihf\t{$dst, $src2}",
 682                          [(set GR64:$dst, (xor GR64:$src1, i64hi32:$src2))]>;
 683
 684 } // Defs = [PSW]
 685
 686 let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
 687 def MUL32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 688                      "msr\t{$dst, $src2}",
 689                      [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
 690 def MUL64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 691                      "msgr\t{$dst, $src2}",
 692                      [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
 693
 694 def MUL64rrP   : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 695                         "mr\t{$dst, $src2}",
 696                         []>;
 697 def UMUL64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 698                          "mlr\t{$dst, $src2}",
 699                          []>;
 700 def UMUL128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 701                         "mlgr\t{$dst, $src2}",
 702                         []>;
 703 }
 704
 705
 706 def MUL32ri16   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 707                          "mhi\t{$dst, $src2}",
 708                          [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
 709 def MUL64ri16   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 710                          "mghi\t{$dst, $src2}",
 711                          [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
 712
 713 def MUL32ri     : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 714                          "msfi\t{$dst, $src2}",
 715                          [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>,
 716                          Requires<[IsZ10]>;
 717 def MUL64ri32   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 718                          "msgfi\t{$dst, $src2}",
 719                          [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
 720                          Requires<[IsZ10]>;
 721
 722 def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 723                      "msy\t{$dst, $src2}",
 724                      [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
 725 def MUL64rm : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 726                      "msg\t{$dst, $src2}",
 727                      [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
 728
 729 def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
 730                          "msgfr\t{$dst, $src2}",
 731                          [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
 732
 733 def SDIVREM64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 734                            "dr\t{$dst, $src2}",
 735                            []>;
 736
 737 def SDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 738                            "dsgr\t{$dst, $src2}",
 739                            []>;
 740
 741 def UDIVREM64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 742                            "dlr\t{$dst, $src2}",
 743                            []>;
 744
 745 def UDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 746                            "dlgr\t{$dst, $src2}",
 747                            []>;
 748
 749 } // isTwoAddress = 1
 750
 751 //===----------------------------------------------------------------------===//
 752 // Shifts
 753
 754 let isTwoAddress = 1 in
 755 def SRL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 756                       "srl\t{$src, $amt}",
 757                       [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
 758 def SRL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 759                       "srlg\t{$dst, $src, $amt}",
 760                       [(set GR64:$dst, (srl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 761 def SRLA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 762                       "srlg\t{$dst, $src, $amt}",
 763                       [(set GR64:$dst, (srl GR64:$src, (i32 imm:$amt)))]>;
 764
 765 let isTwoAddress = 1 in
 766 def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 767                       "sll\t{$src, $amt}",
 768                       [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
 769 def SHL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 770                       "sllg\t{$dst, $src, $amt}",
 771                       [(set GR64:$dst, (shl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 772 def SHL64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 773                       "sllg\t{$dst, $src, $amt}",
 774                       [(set GR64:$dst, (shl GR64:$src, (i32 imm:$amt)))]>;
 775
 776
 777 let Defs = [PSW] in {
 778 let isTwoAddress = 1 in
 779 def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 780                       "sra\t{$src, $amt}",
 781                       [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
 782                        (implicit PSW)]>;
 783 def SRA64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 784                       "srag\t{$dst, $src, $amt}",
 785                       [(set GR64:$dst, (sra GR64:$src, (i32 (trunc riaddr:$amt)))),
 786                        (implicit PSW)]>;
 787 def SRA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 788                       "srag\t{$dst, $src, $amt}",
 789                       [(set GR64:$dst, (sra GR64:$src, (i32 imm:$amt))),
 790                        (implicit PSW)]>;
 791 } // Defs = [PSW]
 792
 793 //===----------------------------------------------------------------------===//
 794 // Test instructions (like AND but do not produce any result
 795
 796 // Integer comparisons
 797 let Defs = [PSW] in {
 798 def CMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 799                      "cr\t$src1, $src2",
 800                      [(SystemZcmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 801 def CMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 802                      "cgr\t$src1, $src2",
 803                      [(SystemZcmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 804
 805 def CMP32ri   : Pseudo<(outs), (ins GR32:$src1, s32imm:$src2),
 806                        "cfi\t$src1, $src2",
 807                        [(SystemZcmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 808 def CMP64ri32 : Pseudo<(outs), (ins GR64:$src1, s32imm64:$src2),
 809                        "cgfi\t$src1, $src2",
 810                        [(SystemZcmp GR64:$src1, i64immSExt32:$src2),
 811                         (implicit PSW)]>;
 812
 813 def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 814                      "cy\t$src1, $src2",
 815                      [(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
 816                       (implicit PSW)]>;
 817 def CMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 818                      "cg\t$src1, $src2",
 819                      [(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
 820                       (implicit PSW)]>;
 821
 822 def UCMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 823                       "clr\t$src1, $src2",
 824                       [(SystemZucmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 825 def UCMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 826                       "clgr\t$src1, $src2",
 827                       [(SystemZucmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 828
 829 def UCMP32ri   : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2),
 830                         "clfi\t$src1, $src2",
 831                         [(SystemZucmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 832 def UCMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2),
 833                         "clgfi\t$src1, $src2",
 834                         [(SystemZucmp GR64:$src1, i64immZExt32:$src2),
 835                          (implicit PSW)]>;
 836
 837 def UCMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 838                       "cly\t$src1, $src2",
 839                       [(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
 840                        (implicit PSW)]>;
 841 def UCMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 842                       "clg\t$src1, $src2",
 843                       [(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
 844                        (implicit PSW)]>;
 845
 846 def CMPSX64rr32  : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 847                           "cgfr\t$src1, $src2",
 848                           [(SystemZucmp GR64:$src1, (sext GR32:$src2)),
 849                            (implicit PSW)]>;
 850 def UCMPZX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 851                           "clgfr\t$src1, $src2",
 852                           [(SystemZucmp GR64:$src1, (zext GR32:$src2)),
 853                            (implicit PSW)]>;
 854
 855 def CMPSX64rm32   : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 856                            "cgf\t$src1, $src2",
 857                            [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
 858                             (implicit PSW)]>;
 859 def UCMPZX64rm32  : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 860                            "clgf\t$src1, $src2",
 861                            [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
 862                             (implicit PSW)]>;
 863
 864 // FIXME: Add other crazy ucmp forms
 865
 866 } // Defs = [PSW]
 867
 868 //===----------------------------------------------------------------------===//
 869 // Non-Instruction Patterns.
 870 //===----------------------------------------------------------------------===//
 871
 872 // anyext
 873 def : Pat<(i64 (anyext GR32:$src)),
 874           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
 875
 876 //===----------------------------------------------------------------------===//
 877 // Peepholes.
 878 //===----------------------------------------------------------------------===//
 879
 880 // FIXME: use add/sub tricks with 32678/-32768
 881
 882 // trunc patterns
 883 def : Pat<(i32 (trunc GR64:$src)),
 884           (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
 885
 886 // sext_inreg patterns
 887 def : Pat<(sext_inreg GR64:$src, i32),
 888           (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
 889
 890 // extload patterns
 891 def : Pat<(extloadi32i8  rriaddr:$src), (MOVZX32rm8  rriaddr:$src)>;
 892 def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>;
 893 def : Pat<(extloadi64i8  rriaddr:$src), (MOVZX64rm8  rriaddr:$src)>;
 894 def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
 895 def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
 896
 897 // calls
 898 def : Pat<(SystemZcall (i64 tglobaladdr:$dst)),
 899           (CALLi tglobaladdr:$dst)>;
 900 def : Pat<(SystemZcall (i64 texternalsym:$dst)),
 901           (CALLi texternalsym:$dst)>;
 902
 903 // muls
 904 def : Pat<(mulhs GR32:$src1, GR32:$src2),
 905           (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 906                                                    GR32:$src1, subreg_odd),
 907                                     GR32:$src2),
 908                           subreg_even)>;
 909
 910 def : Pat<(mulhu GR32:$src1, GR32:$src2),
 911           (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 912                                                     GR32:$src1, subreg_odd),
 913                                      GR32:$src2),
 914                           subreg_even)>;
 915 def : Pat<(mulhu GR64:$src1, GR64:$src2),
 916           (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 917                                                      GR64:$src1, subreg_odd),
 918                                       GR64:$src2),
 919                           subreg_even)>;
 920
 921 // divs
 922 // FIXME: Add memory versions
 923 def : Pat<(sdiv GR32:$src1, GR32:$src2),
 924           (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 925                                                        GR32:$src1, subreg_odd),
 926                                          GR32:$src2),
 927                           subreg_odd)>;
 928 def : Pat<(sdiv GR64:$src1, GR64:$src2),
 929           (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 930                                                         GR64:$src1, subreg_odd),
 931                                          GR64:$src2),
 932                           subreg_odd)>;
 933 def : Pat<(udiv GR32:$src1, GR32:$src2),
 934           (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 935                                                        GR32:$src1, subreg_odd),
 936                                          GR32:$src2),
 937                           subreg_odd)>;
 938 def : Pat<(udiv GR64:$src1, GR64:$src2),
 939           (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 940                                                         GR64:$src1, subreg_odd),
 941                                          GR64:$src2),
 942                           subreg_odd)>;
 943
 944 // rems
 945 // FIXME: Add memory versions
 946 def : Pat<(srem GR32:$src1, GR32:$src2),
 947           (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 948                                                        GR32:$src1, subreg_odd),
 949                                          GR32:$src2),
 950                           subreg_even)>;
 951 def : Pat<(srem GR64:$src1, GR64:$src2),
 952           (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 953                                                         GR64:$src1, subreg_odd),
 954                                          GR64:$src2),
 955                           subreg_even)>;
 956 def : Pat<(urem GR32:$src1, GR32:$src2),
 957           (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 958                                                        GR32:$src1, subreg_odd),
 959                                          GR32:$src2),
 960                           subreg_even)>;
 961 def : Pat<(urem GR64:$src1, GR64:$src2),
 962           (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 963                                                         GR64:$src1, subreg_odd),
 964                                          GR64:$src2),
 965                           subreg_even)>;
 966
 967 def : Pat<(i32 imm:$src),
 968           (EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;