1 //===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15 [(callseq_start timm:$amt)]>;
16 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17 [(callseq_end timm:$amt1, timm:$amt2)]>;
19 let hasSideEffects = 0 in {
20 // Takes as input the value of the stack pointer after a dynamic allocation
21 // has been made. Sets the output to the address of the dynamically-
22 // allocated area itself, skipping the outgoing arguments.
24 // This expands to an LA or LAY instruction. We restrict the offset
25 // to the range of LA and keep the LAY range in reserve for when
26 // the size of the outgoing arguments is added.
27 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28 [(set GR64:$dst, dynalloc12only:$src)]>;
31 //===----------------------------------------------------------------------===//
32 // Control flow instructions
33 //===----------------------------------------------------------------------===//
35 // A return instruction (br %r14).
36 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
37 def Return : Alias<2, (outs), (ins), [(z_retflag)]>;
39 // Unconditional branches. R1 is the condition-code mask (all 1s).
40 let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
41 let isIndirectBranch = 1 in
42 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
43 "br\t$R2", [(brind ADDR64:$R2)]>;
45 // An assembler extended mnemonic for BRC.
46 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
49 // An assembler extended mnemonic for BRCL. (The extension is "G"
50 // rather than "L" because "JL" is "Jump if Less".)
51 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
54 // Conditional branches. It's easier for LLVM to handle these branches
55 // in their raw BRC/BRCL form, with the 4-bit condition-code mask being
56 // the first operand. It seems friendlier to use mnemonic forms like
57 // JE and JLH when writing out the assembly though.
58 let isBranch = 1, isTerminator = 1, Uses = [CC] in {
59 let isCodeGenOnly = 1, CCMaskFirst = 1 in {
60 def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1,
61 brtarget16:$I2), "j$R1\t$I2",
62 [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>;
63 def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1,
64 brtarget32:$I2), "jg$R1\t$I2", []>;
66 def AsmBRC : InstRI<0xA74, (outs), (ins imm32zx4:$R1, brtarget16:$I2),
68 def AsmBRCL : InstRIL<0xC04, (outs), (ins imm32zx4:$R1, brtarget32:$I2),
69 "brcl\t$R1, $I2", []>;
70 def AsmBCR : InstRR<0x07, (outs), (ins imm32zx4:$R1, GR64:$R2),
74 // Fused compare-and-branch instructions. As for normal branches,
75 // we handle these instructions internally in their raw CRJ-like form,
76 // but use assembly macros like CRJE when writing them out.
78 // These instructions do not use or clobber the condition codes.
79 // We nevertheless pretend that they clobber CC, so that we can lower
80 // them to separate comparisons and BRCLs if the branch ends up being
82 multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
83 let isBranch = 1, isTerminator = 1, Defs = [CC] in {
84 def RJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
86 "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
87 def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
89 "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
90 def IJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
92 "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
93 def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
95 "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
96 def LRJ : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
98 "clrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
99 def LGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
101 "clgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
102 def LIJ : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
104 "clij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
105 def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
107 "clgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
110 let isCodeGenOnly = 1 in
111 defm C : CompareBranches<cond4, "$M3", "">;
112 defm AsmC : CompareBranches<imm32zx4, "", "$M3, ">;
114 // Define AsmParser mnemonics for each general condition-code mask
115 // (integer or floating-point)
116 multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
118 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
119 "j"##name##"\t$I2", []>;
120 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
121 "jg"##name##"\t$I2", []>;
122 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2), "b"##name##"r\t$R2", []>;
124 def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>;
125 def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
126 def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>;
127 def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>;
128 def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>;
129 def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
131 defm AsmO : CondExtendedMnemonic<1, "o">;
132 defm AsmH : CondExtendedMnemonic<2, "h">;
133 defm AsmNLE : CondExtendedMnemonic<3, "nle">;
134 defm AsmL : CondExtendedMnemonic<4, "l">;
135 defm AsmNHE : CondExtendedMnemonic<5, "nhe">;
136 defm AsmLH : CondExtendedMnemonic<6, "lh">;
137 defm AsmNE : CondExtendedMnemonic<7, "ne">;
138 defm AsmE : CondExtendedMnemonic<8, "e">;
139 defm AsmNLH : CondExtendedMnemonic<9, "nlh">;
140 defm AsmHE : CondExtendedMnemonic<10, "he">;
141 defm AsmNL : CondExtendedMnemonic<11, "nl">;
142 defm AsmLE : CondExtendedMnemonic<12, "le">;
143 defm AsmNH : CondExtendedMnemonic<13, "nh">;
144 defm AsmNO : CondExtendedMnemonic<14, "no">;
146 // Define AsmParser mnemonics for each integer condition-code mask.
147 // This is like the list above, except that condition 3 is not possible
148 // and that the low bit of the mask is therefore always 0. This means
149 // that each condition has two names. Conditions "o" and "no" are not used.
151 // We don't make one of the two names an alias of the other because
152 // we need the custom parsing routines to select the correct register class.
153 multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
155 def CR : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
157 "crj"##name##"\t$R1, $R2, $RI4", []>;
158 def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
160 "cgrj"##name##"\t$R1, $R2, $RI4", []>;
161 def CI : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
163 "cij"##name##"\t$R1, $I2, $RI4", []>;
164 def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
166 "cgij"##name##"\t$R1, $I2, $RI4", []>;
167 def CLR : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2,
169 "clrj"##name##"\t$R1, $R2, $RI4", []>;
170 def CLGR : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2,
172 "clgrj"##name##"\t$R1, $R2, $RI4", []>;
173 def CLI : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2,
175 "clij"##name##"\t$R1, $I2, $RI4", []>;
176 def CLGI : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2,
178 "clgij"##name##"\t$R1, $I2, $RI4", []>;
181 multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
182 : IntCondExtendedMnemonicA<ccmask, name1> {
183 let isAsmParserOnly = 1 in
184 defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
186 defm AsmJH : IntCondExtendedMnemonic<2, "h", "nle">;
187 defm AsmJL : IntCondExtendedMnemonic<4, "l", "nhe">;
188 defm AsmJLH : IntCondExtendedMnemonic<6, "lh", "ne">;
189 defm AsmJE : IntCondExtendedMnemonic<8, "e", "nlh">;
190 defm AsmJHE : IntCondExtendedMnemonic<10, "he", "nl">;
191 defm AsmJLE : IntCondExtendedMnemonic<12, "le", "nh">;
193 // Decrement a register and branch if it is nonzero. These don't clobber CC,
194 // but we might need to split long branches into sequences that do.
196 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>;
197 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>;
200 //===----------------------------------------------------------------------===//
201 // Select instructions
202 //===----------------------------------------------------------------------===//
204 def Select32Mux : SelectWrapper<GRX32>, Requires<[FeatureHighWord]>;
205 def Select32 : SelectWrapper<GR32>;
206 def Select64 : SelectWrapper<GR64>;
208 // We don't define 32-bit Mux stores because the low-only STOC should
209 // always be used if possible.
210 defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8,
211 nonvolatile_anyextloadi8, bdxaddr20only>,
212 Requires<[FeatureHighWord]>;
213 defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16,
214 nonvolatile_anyextloadi16, bdxaddr20only>,
215 Requires<[FeatureHighWord]>;
216 defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8,
217 nonvolatile_anyextloadi8, bdxaddr20only>;
218 defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16,
219 nonvolatile_anyextloadi16, bdxaddr20only>;
220 defm CondStore32 : CondStores<GR32, nonvolatile_store,
221 nonvolatile_load, bdxaddr20only>;
223 defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8,
224 nonvolatile_anyextloadi8, bdxaddr20only>;
225 defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16,
226 nonvolatile_anyextloadi16, bdxaddr20only>;
227 defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32,
228 nonvolatile_anyextloadi32, bdxaddr20only>;
229 defm CondStore64 : CondStores<GR64, nonvolatile_store,
230 nonvolatile_load, bdxaddr20only>;
232 //===----------------------------------------------------------------------===//
234 //===----------------------------------------------------------------------===//
236 let isCall = 1, Defs = [R14D, CC] in {
237 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops),
238 [(z_call pcrel32:$I2)]>;
239 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops),
240 [(z_call ADDR64:$R2)]>;
243 // Sibling calls. Indirect sibling calls must be via R1, since R2 upwards
244 // are argument registers and since branching to R0 is a no-op.
245 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
246 def CallJG : Alias<6, (outs), (ins pcrel32:$I2),
247 [(z_sibcall pcrel32:$I2)]>;
249 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>;
252 // TLS calls. These will be lowered into a call to __tls_get_offset,
253 // with an extra relocation specifying the TLS symbol.
254 let isCall = 1, Defs = [R14D, CC] in {
255 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops),
256 [(z_tls_gdcall tglobaltlsaddr:$I2)]>;
257 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops),
258 [(z_tls_ldcall tglobaltlsaddr:$I2)]>;
261 // Define the general form of the call instructions for the asm parser.
262 // These instructions don't hard-code %r14 as the return address register.
263 // Allow an optional TLS marker symbol to generate TLS call relocations.
264 def BRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16tls:$I2),
265 "bras\t$R1, $I2", []>;
266 def BRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32tls:$I2),
267 "brasl\t$R1, $I2", []>;
268 def BASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
269 "basr\t$R1, $R2", []>;
271 //===----------------------------------------------------------------------===//
273 //===----------------------------------------------------------------------===//
276 let hasSideEffects = 0 in {
277 // Expands to LR, RISBHG or RISBLG, depending on the choice of registers.
278 def LRMux : UnaryRRPseudo<"l", null_frag, GRX32, GRX32>,
279 Requires<[FeatureHighWord]>;
280 def LR : UnaryRR <"l", 0x18, null_frag, GR32, GR32>;
281 def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
283 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
284 def LTR : UnaryRR <"lt", 0x12, null_frag, GR32, GR32>;
285 def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>;
288 // Move on condition.
289 let isCodeGenOnly = 1, Uses = [CC] in {
290 def LOCR : CondUnaryRRF<"loc", 0xB9F2, GR32, GR32>;
291 def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
294 def AsmLOCR : AsmCondUnaryRRF<"loc", 0xB9F2, GR32, GR32>;
295 def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
299 let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
300 isReMaterializable = 1 in {
301 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF,
302 // deopending on the choice of register.
303 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>,
304 Requires<[FeatureHighWord]>;
305 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>;
306 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
308 // Other 16-bit immediates.
309 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
310 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
311 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
312 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
314 // 32-bit immediates.
315 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>;
316 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
317 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
321 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
322 // Expands to L, LY or LFH, depending on the choice of register.
323 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>,
324 Requires<[FeatureHighWord]>;
325 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
326 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>,
327 Requires<[FeatureHighWord]>;
328 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
330 // These instructions are split after register allocation, so we don't
331 // want a custom inserter.
332 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
333 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
334 [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
337 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
338 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>;
339 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>;
342 let canFoldAsLoad = 1 in {
343 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;
344 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
347 // Load on condition.
348 let isCodeGenOnly = 1, Uses = [CC] in {
349 def LOC : CondUnaryRSY<"loc", 0xEBF2, nonvolatile_load, GR32, 4>;
350 def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>;
353 def AsmLOC : AsmCondUnaryRSY<"loc", 0xEBF2, GR32, 4>;
354 def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
358 let SimpleBDXStore = 1 in {
359 // Expands to ST, STY or STFH, depending on the choice of register.
360 def STMux : StoreRXYPseudo<store, GRX32, 4>,
361 Requires<[FeatureHighWord]>;
362 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
363 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>,
364 Requires<[FeatureHighWord]>;
365 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
367 // These instructions are split after register allocation, so we don't
368 // want a custom inserter.
369 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
370 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
371 [(store GR128:$src, bdxaddr20only128:$dst)]>;
374 def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
375 def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
377 // Store on condition.
378 let isCodeGenOnly = 1, Uses = [CC] in {
379 def STOC : CondStoreRSY<"stoc", 0xEBF3, GR32, 4>;
380 def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
383 def AsmSTOC : AsmCondStoreRSY<"stoc", 0xEBF3, GR32, 4>;
384 def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
387 // 8-bit immediate stores to 8-bit fields.
388 defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
390 // 16-bit immediate stores to 16-, 32- or 64-bit fields.
391 def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
392 def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>;
393 def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>;
395 // Memory-to-memory moves.
396 let mayLoad = 1, mayStore = 1 in
397 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>;
400 let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L] in
401 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
403 //===----------------------------------------------------------------------===//
405 //===----------------------------------------------------------------------===//
407 // Note that putting these before zero extensions mean that we will prefer
408 // them for anyextload*. There's not really much to choose between the two
409 // either way, but signed-extending loads have a short LH and a long LHY,
410 // while zero-extending loads have only the long LLH.
412 //===----------------------------------------------------------------------===//
414 // 32-bit extensions from registers.
415 let hasSideEffects = 0 in {
416 def LBR : UnaryRRE<"lb", 0xB926, sext8, GR32, GR32>;
417 def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
420 // 64-bit extensions from registers.
421 let hasSideEffects = 0 in {
422 def LGBR : UnaryRRE<"lgb", 0xB906, sext8, GR64, GR64>;
423 def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
424 def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
426 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
427 def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR64>;
429 // Match 32-to-64-bit sign extensions in which the source is already
430 // in a 64-bit register.
431 def : Pat<(sext_inreg GR64:$src, i32),
432 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
434 // 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH,
435 // depending on the choice of register.
436 def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>,
437 Requires<[FeatureHighWord]>;
438 def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>;
439 def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>,
440 Requires<[FeatureHighWord]>;
442 // 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH,
443 // depending on the choice of register.
444 def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>,
445 Requires<[FeatureHighWord]>;
446 defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>;
447 def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>,
448 Requires<[FeatureHighWord]>;
449 def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>;
451 // 64-bit extensions from memory.
452 def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>;
453 def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>;
454 def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>;
455 def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>;
456 def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>;
457 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
458 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>;
460 //===----------------------------------------------------------------------===//
462 //===----------------------------------------------------------------------===//
464 // 32-bit extensions from registers.
465 let hasSideEffects = 0 in {
466 // Expands to LLCR or RISB[LH]G, depending on the choice of registers.
467 def LLCRMux : UnaryRRPseudo<"llc", zext8, GRX32, GRX32>,
468 Requires<[FeatureHighWord]>;
469 def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>;
470 // Expands to LLHR or RISB[LH]G, depending on the choice of registers.
471 def LLHRMux : UnaryRRPseudo<"llh", zext16, GRX32, GRX32>,
472 Requires<[FeatureHighWord]>;
473 def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
476 // 64-bit extensions from registers.
477 let hasSideEffects = 0 in {
478 def LLGCR : UnaryRRE<"llgc", 0xB984, zext8, GR64, GR64>;
479 def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
480 def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
483 // Match 32-to-64-bit zero extensions in which the source is already
484 // in a 64-bit register.
485 def : Pat<(and GR64:$src, 0xffffffff),
486 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
488 // 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH,
489 // depending on the choice of register.
490 def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>,
491 Requires<[FeatureHighWord]>;
492 def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>;
493 def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GR32, 1>,
494 Requires<[FeatureHighWord]>;
496 // 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH,
497 // depending on the choice of register.
498 def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>,
499 Requires<[FeatureHighWord]>;
500 def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>;
501 def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GR32, 2>,
502 Requires<[FeatureHighWord]>;
503 def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>;
505 // 64-bit extensions from memory.
506 def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>;
507 def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>;
508 def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>;
509 def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>;
510 def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>;
512 //===----------------------------------------------------------------------===//
514 //===----------------------------------------------------------------------===//
516 // Truncations of 64-bit registers to 32-bit registers.
517 def : Pat<(i32 (trunc GR64:$src)),
518 (EXTRACT_SUBREG GR64:$src, subreg_l32)>;
520 // Truncations of 32-bit registers to 8-bit memory. STCMux expands to
521 // STC, STCY or STCH, depending on the choice of register.
522 def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>,
523 Requires<[FeatureHighWord]>;
524 defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
525 def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>,
526 Requires<[FeatureHighWord]>;
528 // Truncations of 32-bit registers to 16-bit memory. STHMux expands to
529 // STH, STHY or STHH, depending on the choice of register.
530 def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>,
531 Requires<[FeatureHighWord]>;
532 defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
533 def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>,
534 Requires<[FeatureHighWord]>;
535 def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
537 // Truncations of 64-bit registers to memory.
538 defm : StoreGR64Pair<STC, STCY, truncstorei8>;
539 defm : StoreGR64Pair<STH, STHY, truncstorei16>;
540 def : StoreGR64PC<STHRL, aligned_truncstorei16>;
541 defm : StoreGR64Pair<ST, STY, truncstorei32>;
542 def : StoreGR64PC<STRL, aligned_truncstorei32>;
544 //===----------------------------------------------------------------------===//
545 // Multi-register moves
546 //===----------------------------------------------------------------------===//
548 // Multi-register loads.
549 def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
551 // Multi-register stores.
552 def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
554 //===----------------------------------------------------------------------===//
556 //===----------------------------------------------------------------------===//
558 // Byte-swapping register moves.
559 let hasSideEffects = 0 in {
560 def LRVR : UnaryRRE<"lrv", 0xB91F, bswap, GR32, GR32>;
561 def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
564 // Byte-swapping loads. Unlike normal loads, these instructions are
565 // allowed to access storage more than once.
566 def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>;
567 def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>;
569 // Likewise byte-swapping stores.
570 def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>;
571 def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>,
574 //===----------------------------------------------------------------------===//
575 // Load address instructions
576 //===----------------------------------------------------------------------===//
578 // Load BDX-style addresses.
579 let hasSideEffects = 0, isAsCheapAsAMove = 1, isReMaterializable = 1,
581 let DispSize = "12" in
582 def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
584 [(set GR64:$R1, laaddr12pair:$XBD2)]>;
585 let DispSize = "20" in
586 def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
588 [(set GR64:$R1, laaddr20pair:$XBD2)]>;
591 // Load a PC-relative address. There's no version of this instruction
592 // with a 16-bit offset, so there's no relaxation.
593 let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
594 isReMaterializable = 1 in {
595 def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
597 [(set GR64:$R1, pcrel32:$I2)]>;
600 // Load the Global Offset Table address. This will be lowered into a
601 // larl $R1, _GLOBAL_OFFSET_TABLE_
603 def GOT : Alias<6, (outs GR64:$R1), (ins),
604 [(set GR64:$R1, (global_offset_table))]>;
606 //===----------------------------------------------------------------------===//
607 // Absolute and Negation
608 //===----------------------------------------------------------------------===//
611 let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
612 def LPR : UnaryRR <"lp", 0x10, z_iabs, GR32, GR32>;
613 def LPGR : UnaryRRE<"lpg", 0xB900, z_iabs, GR64, GR64>;
615 let CCValues = 0xE, CompareZeroCCMask = 0xE in
616 def LPGFR : UnaryRRE<"lpgf", 0xB910, null_frag, GR64, GR32>;
618 def : Pat<(z_iabs32 GR32:$src), (LPR GR32:$src)>;
619 def : Pat<(z_iabs64 GR64:$src), (LPGR GR64:$src)>;
620 defm : SXU<z_iabs, LPGFR>;
621 defm : SXU<z_iabs64, LPGFR>;
624 let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
625 def LNR : UnaryRR <"ln", 0x11, z_inegabs, GR32, GR32>;
626 def LNGR : UnaryRRE<"lng", 0xB901, z_inegabs, GR64, GR64>;
628 let CCValues = 0xE, CompareZeroCCMask = 0xE in
629 def LNGFR : UnaryRRE<"lngf", 0xB911, null_frag, GR64, GR32>;
631 def : Pat<(z_inegabs32 GR32:$src), (LNR GR32:$src)>;
632 def : Pat<(z_inegabs64 GR64:$src), (LNGR GR64:$src)>;
633 defm : SXU<z_inegabs, LNGFR>;
634 defm : SXU<z_inegabs64, LNGFR>;
637 let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
638 def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>;
639 def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
641 let CCValues = 0xE, CompareZeroCCMask = 0xE in
642 def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>;
644 defm : SXU<ineg, LCGFR>;
646 //===----------------------------------------------------------------------===//
648 //===----------------------------------------------------------------------===//
650 let isCodeGenOnly = 1 in
651 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>;
652 defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>;
654 defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>;
655 defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>;
657 defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>;
658 defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>;
660 // Insertions of a 16-bit immediate, leaving other bits unaffected.
661 // We don't have or_as_insert equivalents of these operations because
662 // OI is available instead.
664 // IIxMux expands to II[LH]x, depending on the choice of register.
665 def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>,
666 Requires<[FeatureHighWord]>;
667 def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>,
668 Requires<[FeatureHighWord]>;
669 def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
670 def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
671 def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>;
672 def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>;
673 def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>;
674 def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>;
675 def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>;
676 def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>;
678 // ...likewise for 32-bit immediates. For GR32s this is a general
679 // full-width move. (We use IILF rather than something like LLILF
680 // for 32-bit moves because IILF leaves the upper 32 bits of the
682 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
683 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>,
684 Requires<[FeatureHighWord]>;
685 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
686 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>;
688 def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;
689 def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>;
691 // An alternative model of inserthf, with the first operand being
692 // a zero-extended value.
693 def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
694 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
697 //===----------------------------------------------------------------------===//
699 //===----------------------------------------------------------------------===//
702 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
703 // Addition of a register.
704 let isCommutable = 1 in {
705 defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
706 defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
708 def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
710 // Addition of signed 16-bit immediates.
711 defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>;
712 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>;
713 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
715 // Addition of signed 32-bit immediates.
716 def AFIMux : BinaryRIPseudo<add, GRX32, simm32>,
717 Requires<[FeatureHighWord]>;
718 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>;
719 def AIH : BinaryRIL<"aih", 0xCC8, add, GRH32, simm32>,
720 Requires<[FeatureHighWord]>;
721 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
723 // Addition of memory.
724 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>;
725 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>;
726 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>;
727 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>;
729 // Addition to memory.
730 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>;
731 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
733 defm : SXB<add, GR64, AGFR>;
735 // Addition producing a carry.
737 // Addition of a register.
738 let isCommutable = 1 in {
739 defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>;
740 defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>;
742 def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
744 // Addition of signed 16-bit immediates.
745 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>,
746 Requires<[FeatureDistinctOps]>;
747 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>,
748 Requires<[FeatureDistinctOps]>;
750 // Addition of unsigned 32-bit immediates.
751 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>;
752 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
754 // Addition of memory.
755 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>;
756 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>;
757 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>;
759 defm : ZXB<addc, GR64, ALGFR>;
761 // Addition producing and using a carry.
762 let Defs = [CC], Uses = [CC] in {
763 // Addition of a register.
764 def ALCR : BinaryRRE<"alc", 0xB998, adde, GR32, GR32>;
765 def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>;
767 // Addition of memory.
768 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>;
769 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>;
772 //===----------------------------------------------------------------------===//
774 //===----------------------------------------------------------------------===//
776 // Plain subtraction. Although immediate forms exist, we use the
777 // add-immediate instruction instead.
778 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
779 // Subtraction of a register.
780 defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
781 def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
782 defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
784 // Subtraction of memory.
785 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>;
786 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>;
787 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>;
788 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>;
790 defm : SXB<sub, GR64, SGFR>;
792 // Subtraction producing a carry.
794 // Subtraction of a register.
795 defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
796 def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
797 defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
799 // Subtraction of unsigned 32-bit immediates. These don't match
800 // subc because we prefer addc for constants.
801 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>;
802 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
804 // Subtraction of memory.
805 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
806 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>;
807 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>;
809 defm : ZXB<subc, GR64, SLGFR>;
811 // Subtraction producing and using a carry.
812 let Defs = [CC], Uses = [CC] in {
813 // Subtraction of a register.
814 def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>;
815 def SLGBR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
817 // Subtraction of memory.
818 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>;
819 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
822 //===----------------------------------------------------------------------===//
824 //===----------------------------------------------------------------------===//
827 // ANDs of a register.
828 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
829 defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>;
830 defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>;
833 let isConvertibleToThreeAddress = 1 in {
834 // ANDs of a 16-bit immediate, leaving other bits unaffected.
835 // The CC result only reflects the 16-bit field, not the full register.
837 // NIxMux expands to NI[LH]x, depending on the choice of register.
838 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>,
839 Requires<[FeatureHighWord]>;
840 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>,
841 Requires<[FeatureHighWord]>;
842 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
843 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
844 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>;
845 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>;
846 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>;
847 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>;
848 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>;
849 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>;
851 // ANDs of a 32-bit immediate, leaving other bits unaffected.
852 // The CC result only reflects the 32-bit field, which means we can
853 // use it as a zero indicator for i32 operations but not otherwise.
854 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
855 // Expands to NILF or NIHF, depending on the choice of register.
856 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>,
857 Requires<[FeatureHighWord]>;
858 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
859 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>;
861 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>;
862 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>;
866 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
867 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>;
868 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>;
872 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>;
875 let mayLoad = 1, mayStore = 1 in
876 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>;
878 defm : RMWIByte<and, bdaddr12pair, NI>;
879 defm : RMWIByte<and, bdaddr20pair, NIY>;
881 //===----------------------------------------------------------------------===//
883 //===----------------------------------------------------------------------===//
886 // ORs of a register.
887 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
888 defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>;
889 defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>;
892 // ORs of a 16-bit immediate, leaving other bits unaffected.
893 // The CC result only reflects the 16-bit field, not the full register.
895 // OIxMux expands to OI[LH]x, depending on the choice of register.
896 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>,
897 Requires<[FeatureHighWord]>;
898 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>,
899 Requires<[FeatureHighWord]>;
900 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
901 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
902 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>;
903 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>;
904 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>;
905 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>;
906 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>;
907 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>;
909 // ORs of a 32-bit immediate, leaving other bits unaffected.
910 // The CC result only reflects the 32-bit field, which means we can
911 // use it as a zero indicator for i32 operations but not otherwise.
912 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
913 // Expands to OILF or OIHF, depending on the choice of register.
914 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>,
915 Requires<[FeatureHighWord]>;
916 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
917 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>;
919 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>;
920 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>;
923 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
924 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>;
925 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>;
929 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>;
932 let mayLoad = 1, mayStore = 1 in
933 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>;
935 defm : RMWIByte<or, bdaddr12pair, OI>;
936 defm : RMWIByte<or, bdaddr20pair, OIY>;
938 //===----------------------------------------------------------------------===//
940 //===----------------------------------------------------------------------===//
943 // XORs of a register.
944 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
945 defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>;
946 defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>;
949 // XORs of a 32-bit immediate, leaving other bits unaffected.
950 // The CC result only reflects the 32-bit field, which means we can
951 // use it as a zero indicator for i32 operations but not otherwise.
952 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
953 // Expands to XILF or XIHF, depending on the choice of register.
954 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>,
955 Requires<[FeatureHighWord]>;
956 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
957 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>;
959 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>;
960 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>;
963 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
964 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>;
965 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>;
969 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>;
972 let mayLoad = 1, mayStore = 1 in
973 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>;
975 defm : RMWIByte<xor, bdaddr12pair, XI>;
976 defm : RMWIByte<xor, bdaddr20pair, XIY>;
978 //===----------------------------------------------------------------------===//
980 //===----------------------------------------------------------------------===//
982 // Multiplication of a register.
983 let isCommutable = 1 in {
984 def MSR : BinaryRRE<"ms", 0xB252, mul, GR32, GR32>;
985 def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>;
987 def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>;
988 defm : SXB<mul, GR64, MSGFR>;
990 // Multiplication of a signed 16-bit immediate.
991 def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>;
992 def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
994 // Multiplication of a signed 32-bit immediate.
995 def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>;
996 def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
998 // Multiplication of memory.
999 defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>;
1000 defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
1001 def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>;
1002 def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>;
1004 // Multiplication of a register, producing two results.
1005 def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>;
1007 // Multiplication of memory, producing two results.
1008 def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
1010 //===----------------------------------------------------------------------===//
1011 // Division and remainder
1012 //===----------------------------------------------------------------------===//
1014 // Division and remainder, from registers.
1015 def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>;
1016 def DSGR : BinaryRRE<"dsg", 0xB90D, z_sdivrem64, GR128, GR64>;
1017 def DLR : BinaryRRE<"dl", 0xB997, z_udivrem32, GR128, GR32>;
1018 def DLGR : BinaryRRE<"dlg", 0xB987, z_udivrem64, GR128, GR64>;
1020 // Division and remainder, from memory.
1021 def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
1022 def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load, 8>;
1023 def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load, 4>;
1024 def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>;
1026 //===----------------------------------------------------------------------===//
1028 //===----------------------------------------------------------------------===//
1031 let hasSideEffects = 0 in {
1032 defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
1033 def SLLG : BinaryRSY<"sllg", 0xEB0D, shl, GR64>;
1036 // Logical shift right.
1037 let hasSideEffects = 0 in {
1038 defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
1039 def SRLG : BinaryRSY<"srlg", 0xEB0C, srl, GR64>;
1042 // Arithmetic shift right.
1043 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
1044 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
1045 def SRAG : BinaryRSY<"srag", 0xEB0A, sra, GR64>;
1049 let hasSideEffects = 0 in {
1050 def RLL : BinaryRSY<"rll", 0xEB1D, rotl, GR32>;
1051 def RLLG : BinaryRSY<"rllg", 0xEB1C, rotl, GR64>;
1054 // Rotate second operand left and inserted selected bits into first operand.
1055 // These can act like 32-bit operands provided that the constant start and
1056 // end bits (operands 2 and 3) are in the range [32, 64).
1057 let Defs = [CC] in {
1058 let isCodeGenOnly = 1 in
1059 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
1060 let CCValues = 0xE, CompareZeroCCMask = 0xE in
1061 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
1064 // On zEC12 we have a variant of RISBG that does not set CC.
1065 let Predicates = [FeatureMiscellaneousExtensions] in
1066 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>;
1068 // Forms of RISBG that only affect one word of the destination register.
1069 // They do not set CC.
1070 let Predicates = [FeatureHighWord] in {
1071 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>;
1072 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>;
1073 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>;
1074 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>;
1075 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>;
1076 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>;
1077 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>;
1080 // Rotate second operand left and perform a logical operation with selected
1081 // bits of the first operand. The CC result only describes the selected bits,
1082 // so isn't useful for a full comparison against zero.
1083 let Defs = [CC] in {
1084 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
1085 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
1086 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
1089 //===----------------------------------------------------------------------===//
1091 //===----------------------------------------------------------------------===//
1093 // Signed comparisons. We put these before the unsigned comparisons because
1094 // some of the signed forms have COMPARE AND BRANCH equivalents whereas none
1095 // of the unsigned forms do.
1096 let Defs = [CC], CCValues = 0xE in {
1097 // Comparison with a register.
1098 def CR : CompareRR <"c", 0x19, z_scmp, GR32, GR32>;
1099 def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>;
1100 def CGR : CompareRRE<"cg", 0xB920, z_scmp, GR64, GR64>;
1102 // Comparison with a signed 16-bit immediate.
1103 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>;
1104 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>;
1106 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH,
1107 // depending on the choice of register.
1108 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>,
1109 Requires<[FeatureHighWord]>;
1110 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>;
1111 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>,
1112 Requires<[FeatureHighWord]>;
1113 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>;
1115 // Comparison with memory.
1116 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>;
1117 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>,
1118 Requires<[FeatureHighWord]>;
1119 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>;
1120 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>,
1121 Requires<[FeatureHighWord]>;
1122 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>;
1123 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>;
1124 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>;
1125 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>;
1126 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>;
1127 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>;
1128 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>;
1129 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>;
1131 // Comparison between memory and a signed 16-bit immediate.
1132 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>;
1133 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>;
1134 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>;
1136 defm : SXB<z_scmp, GR64, CGFR>;
1138 // Unsigned comparisons.
1139 let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
1140 // Comparison with a register.
1141 def CLR : CompareRR <"cl", 0x15, z_ucmp, GR32, GR32>;
1142 def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>;
1143 def CLGR : CompareRRE<"clg", 0xB921, z_ucmp, GR64, GR64>;
1145 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI
1146 // or CLIH, depending on the choice of register.
1147 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>,
1148 Requires<[FeatureHighWord]>;
1149 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>;
1150 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GR32, uimm32>,
1151 Requires<[FeatureHighWord]>;
1152 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
1154 // Comparison with memory.
1155 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>,
1156 Requires<[FeatureHighWord]>;
1157 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>;
1158 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>,
1159 Requires<[FeatureHighWord]>;
1160 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>;
1161 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>;
1162 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32,
1163 aligned_azextloadi16>;
1164 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32,
1166 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
1167 aligned_azextloadi16>;
1168 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
1169 aligned_azextloadi32>;
1170 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64,
1173 // Comparison between memory and an unsigned 8-bit immediate.
1174 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>;
1176 // Comparison between memory and an unsigned 16-bit immediate.
1177 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>;
1178 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
1179 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
1181 defm : ZXB<z_ucmp, GR64, CLGFR>;
1183 // Memory-to-memory comparison.
1184 let mayLoad = 1, Defs = [CC] in
1185 defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>;
1187 // String comparison.
1188 let mayLoad = 1, Defs = [CC], Uses = [R0L] in
1189 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>;
1192 let Defs = [CC] in {
1193 // TMxMux expands to TM[LH]x, depending on the choice of register.
1194 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>,
1195 Requires<[FeatureHighWord]>;
1196 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>,
1197 Requires<[FeatureHighWord]>;
1198 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>;
1199 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>;
1200 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>;
1201 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>;
1203 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>;
1204 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>;
1205 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>;
1206 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>;
1208 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
1211 //===----------------------------------------------------------------------===//
1213 //===----------------------------------------------------------------------===//
1215 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>;
1216 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>;
1218 //===----------------------------------------------------------------------===//
1219 // Atomic operations
1220 //===----------------------------------------------------------------------===//
1222 def Serialize : Alias<2, (outs), (ins), [(z_serialize)]>;
1224 let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in {
1225 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>;
1226 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>;
1227 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>;
1228 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>;
1229 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>;
1230 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>;
1231 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>;
1232 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>;
1233 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>;
1234 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>;
1237 def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>;
1238 def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>;
1239 def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>;
1241 def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
1242 def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
1243 let Predicates = [FeatureNoInterlockedAccess1] in {
1244 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>;
1245 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
1246 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
1247 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>;
1248 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
1249 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
1252 def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
1253 def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>;
1254 def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>;
1256 def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
1257 def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
1258 let Predicates = [FeatureNoInterlockedAccess1] in {
1259 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>;
1260 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32,
1262 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32,
1264 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
1265 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>;
1266 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1268 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1270 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1272 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1274 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1276 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64,
1280 def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
1281 def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
1282 let Predicates = [FeatureNoInterlockedAccess1] in {
1283 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>;
1284 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
1285 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
1286 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
1287 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>;
1288 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
1289 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
1290 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
1291 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
1292 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
1293 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
1296 def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
1297 def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
1298 let Predicates = [FeatureNoInterlockedAccess1] in {
1299 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>;
1300 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
1301 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>;
1302 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
1303 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
1306 def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
1307 def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
1309 def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>;
1310 def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32,
1312 def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32,
1314 def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
1315 def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>;
1316 def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1318 def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1320 def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1322 def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1324 def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1326 def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1329 def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
1330 def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>;
1331 def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>;
1333 def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
1334 def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>;
1335 def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>;
1337 def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
1338 def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
1339 def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
1341 def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
1342 def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
1343 def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
1345 def ATOMIC_CMP_SWAPW
1346 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1347 ADDR32:$bitshift, ADDR32:$negbitshift,
1350 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1351 ADDR32:$bitshift, ADDR32:$negbitshift,
1352 uimm32:$bitsize))]> {
1356 let usesCustomInserter = 1;
1359 let Defs = [CC] in {
1360 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
1361 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
1364 //===----------------------------------------------------------------------===//
1365 // Transactional execution
1366 //===----------------------------------------------------------------------===//
1368 let Predicates = [FeatureTransactionalExecution] in {
1369 // Transaction Begin
1370 let hasSideEffects = 1, mayStore = 1,
1371 usesCustomInserter = 1, Defs = [CC] in {
1372 def TBEGIN : InstSIL<0xE560,
1373 (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
1374 "tbegin\t$BD1, $I2",
1375 [(z_tbegin bdaddr12only:$BD1, imm32zx16:$I2)]>;
1376 def TBEGIN_nofloat : Pseudo<(outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
1377 [(z_tbegin_nofloat bdaddr12only:$BD1,
1379 def TBEGINC : InstSIL<0xE561,
1380 (outs), (ins bdaddr12only:$BD1, imm32zx16:$I2),
1381 "tbeginc\t$BD1, $I2",
1382 [(int_s390_tbeginc bdaddr12only:$BD1,
1387 let hasSideEffects = 1, Defs = [CC], BD2 = 0 in
1388 def TEND : InstS<0xB2F8, (outs), (ins), "tend", [(z_tend)]>;
1390 // Transaction Abort
1391 let hasSideEffects = 1, isTerminator = 1, isBarrier = 1 in
1392 def TABORT : InstS<0xB2FC, (outs), (ins bdaddr12only:$BD2),
1394 [(int_s390_tabort bdaddr12only:$BD2)]>;
1396 // Nontransactional Store
1397 let hasSideEffects = 1 in
1398 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>;
1400 // Extract Transaction Nesting Depth
1401 let hasSideEffects = 1 in
1402 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, (int_s390_etnd)>;
1405 //===----------------------------------------------------------------------===//
1407 //===----------------------------------------------------------------------===//
1409 let Predicates = [FeatureProcessorAssist] in {
1410 let hasSideEffects = 1, R4 = 0 in
1411 def PPA : InstRRF<0xB2E8, (outs), (ins GR64:$R1, GR64:$R2, imm32zx4:$R3),
1412 "ppa\t$R1, $R2, $R3", []>;
1413 def : Pat<(int_s390_ppa_txassist GR32:$src),
1414 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
1418 //===----------------------------------------------------------------------===//
1419 // Miscellaneous Instructions.
1420 //===----------------------------------------------------------------------===//
1422 // Extract CC into bits 29 and 28 of a register.
1424 def IPM : InherentRRE<"ipm", 0xB222, GR32, (z_ipm)>;
1426 // Read a 32-bit access register into a GR32. As with all GR32 operations,
1427 // the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
1428 // when a 64-bit address is stored in a pair of access registers.
1429 def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
1431 [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
1433 // Find leftmost one, AKA count leading zeros. The instruction actually
1434 // returns a pair of GR64s, the first giving the number of leading zeros
1435 // and the second giving a copy of the source with the leftmost one bit
1436 // cleared. We only use the first result here.
1437 let Defs = [CC] in {
1438 def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>;
1440 def : Pat<(ctlz GR64:$src),
1441 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>;
1443 // Population count. Counts bits set per byte.
1444 let Predicates = [FeaturePopulationCount], Defs = [CC] in {
1445 def POPCNT : InstRRE<0xB9E1, (outs GR64:$R1), (ins GR64:$R2),
1447 [(set GR64:$R1, (z_popcnt GR64:$R2))]>;
1450 // Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
1451 def : Pat<(i64 (anyext GR32:$src)),
1452 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
1454 // Extend GR32s and GR64s to GR128s.
1455 let usesCustomInserter = 1 in {
1456 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1457 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
1458 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1461 // Search a block of memory for a character.
1462 let mayLoad = 1, Defs = [CC], Uses = [R0L] in
1463 defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
1465 //===----------------------------------------------------------------------===//
1467 //===----------------------------------------------------------------------===//
1469 // Use AL* for GR64 additions of unsigned 32-bit values.
1470 defm : ZXB<add, GR64, ALGFR>;
1471 def : Pat<(add GR64:$src1, imm64zx32:$src2),
1472 (ALGFI GR64:$src1, imm64zx32:$src2)>;
1473 def : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1474 (ALGF GR64:$src1, bdxaddr20only:$addr)>;
1476 // Use SL* for GR64 subtractions of unsigned 32-bit values.
1477 defm : ZXB<sub, GR64, SLGFR>;
1478 def : Pat<(add GR64:$src1, imm64zx32n:$src2),
1479 (SLGFI GR64:$src1, imm64zx32n:$src2)>;
1480 def : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1481 (SLGF GR64:$src1, bdxaddr20only:$addr)>;
1483 // Optimize sign-extended 1/0 selects to -1/0 selects. This is important
1484 // for vector legalization.
1485 def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, imm32zx4:$valid, imm32zx4:$cc)),
1488 (Select32 (LHI -1), (LHI 0), imm32zx4:$valid, imm32zx4:$cc)>;
1489 def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm32zx4:$valid,
1493 (Select64 (LGHI -1), (LGHI 0), imm32zx4:$valid, imm32zx4:$cc)>;
1495 // Peepholes for turning scalar operations into block operations.
1496 defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
1498 defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence,
1500 defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence,
1502 defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence,
1503 OCSequence, XCSequence, 1>;
1504 defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence,
1506 defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence,
1508 defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence,