1 //===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15 [(callseq_start timm:$amt)]>;
16 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17 [(callseq_end timm:$amt1, timm:$amt2)]>;
19 let neverHasSideEffects = 1 in {
20 // Takes as input the value of the stack pointer after a dynamic allocation
21 // has been made. Sets the output to the address of the dynamically-
22 // allocated area itself, skipping the outgoing arguments.
24 // This expands to an LA or LAY instruction. We restrict the offset
25 // to the range of LA and keep the LAY range in reserve for when
26 // the size of the outgoing arguments is added.
27 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28 [(set GR64:$dst, dynalloc12only:$src)]>;
31 //===----------------------------------------------------------------------===//
32 // Control flow instructions
33 //===----------------------------------------------------------------------===//
35 // A return instruction (br %r14).
36 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
37 def Return : Alias<2, (outs), (ins), [(z_retflag)]>;
39 // Unconditional branches. R1 is the condition-code mask (all 1s).
40 let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
41 let isIndirectBranch = 1 in
42 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
43 "br\t$R2", [(brind ADDR64:$R2)]>;
45 // An assembler extended mnemonic for BRC.
46 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
49 // An assembler extended mnemonic for BRCL. (The extension is "G"
50 // rather than "L" because "JL" is "Jump if Less".)
51 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
54 // Conditional branches. It's easier for LLVM to handle these branches
55 // in their raw BRC/BRCL form, with the 4-bit condition-code mask being
56 // the first operand. It seems friendlier to use mnemonic forms like
57 // JE and JLH when writing out the assembly though.
58 let isBranch = 1, isTerminator = 1, Uses = [CC] in {
59 let isCodeGenOnly = 1, CCMaskFirst = 1 in {
60 def BRC : InstRI<0xA74, (outs), (ins cond4:$valid, cond4:$R1,
61 brtarget16:$I2), "j$R1\t$I2",
62 [(z_br_ccmask cond4:$valid, cond4:$R1, bb:$I2)]>;
63 def BRCL : InstRIL<0xC04, (outs), (ins cond4:$valid, cond4:$R1,
64 brtarget32:$I2), "jg$R1\t$I2", []>;
66 def AsmBRC : InstRI<0xA74, (outs), (ins uimm8zx4:$R1, brtarget16:$I2),
68 def AsmBRCL : InstRIL<0xC04, (outs), (ins uimm8zx4:$R1, brtarget32:$I2),
69 "brcl\t$R1, $I2", []>;
72 // Fused compare-and-branch instructions. As for normal branches,
73 // we handle these instructions internally in their raw CRJ-like form,
74 // but use assembly macros like CRJE when writing them out.
76 // These instructions do not use or clobber the condition codes.
77 // We nevertheless pretend that they clobber CC, so that we can lower
78 // them to separate comparisons and BRCLs if the branch ends up being
80 multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
81 let isBranch = 1, isTerminator = 1, Defs = [CC] in {
82 def RJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
84 "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
85 def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
87 "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
88 def IJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
90 "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
91 def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
93 "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
94 def LRJ : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
96 "clrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
97 def LGRJ : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
99 "clgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
100 def LIJ : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2, ccmask:$M3,
102 "clij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
103 def LGIJ : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2, ccmask:$M3,
105 "clgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
108 let isCodeGenOnly = 1 in
109 defm C : CompareBranches<cond4, "$M3", "">;
110 defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">;
112 // Define AsmParser mnemonics for each general condition-code mask
113 // (integer or floating-point)
114 multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
116 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
117 "j"##name##"\t$I2", []>;
118 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
119 "jg"##name##"\t$I2", []>;
121 def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>;
122 def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
123 def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>;
124 def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>;
125 def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>;
126 def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
128 defm AsmO : CondExtendedMnemonic<1, "o">;
129 defm AsmH : CondExtendedMnemonic<2, "h">;
130 defm AsmNLE : CondExtendedMnemonic<3, "nle">;
131 defm AsmL : CondExtendedMnemonic<4, "l">;
132 defm AsmNHE : CondExtendedMnemonic<5, "nhe">;
133 defm AsmLH : CondExtendedMnemonic<6, "lh">;
134 defm AsmNE : CondExtendedMnemonic<7, "ne">;
135 defm AsmE : CondExtendedMnemonic<8, "e">;
136 defm AsmNLH : CondExtendedMnemonic<9, "nlh">;
137 defm AsmHE : CondExtendedMnemonic<10, "he">;
138 defm AsmNL : CondExtendedMnemonic<11, "nl">;
139 defm AsmLE : CondExtendedMnemonic<12, "le">;
140 defm AsmNH : CondExtendedMnemonic<13, "nh">;
141 defm AsmNO : CondExtendedMnemonic<14, "no">;
143 // Define AsmParser mnemonics for each integer condition-code mask.
144 // This is like the list above, except that condition 3 is not possible
145 // and that the low bit of the mask is therefore always 0. This means
146 // that each condition has two names. Conditions "o" and "no" are not used.
148 // We don't make one of the two names an alias of the other because
149 // we need the custom parsing routines to select the correct register class.
150 multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
152 def CR : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
154 "crj"##name##"\t$R1, $R2, $RI4", []>;
155 def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
157 "cgrj"##name##"\t$R1, $R2, $RI4", []>;
158 def CI : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
160 "cij"##name##"\t$R1, $I2, $RI4", []>;
161 def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
163 "cgij"##name##"\t$R1, $I2, $RI4", []>;
164 def CLR : InstRIEb<0xEC77, (outs), (ins GR32:$R1, GR32:$R2,
166 "clrj"##name##"\t$R1, $R2, $RI4", []>;
167 def CLGR : InstRIEb<0xEC65, (outs), (ins GR64:$R1, GR64:$R2,
169 "clgrj"##name##"\t$R1, $R2, $RI4", []>;
170 def CLI : InstRIEc<0xEC7F, (outs), (ins GR32:$R1, imm32zx8:$I2,
172 "clij"##name##"\t$R1, $I2, $RI4", []>;
173 def CLGI : InstRIEc<0xEC7D, (outs), (ins GR64:$R1, imm64zx8:$I2,
175 "clgij"##name##"\t$R1, $I2, $RI4", []>;
178 multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
179 : IntCondExtendedMnemonicA<ccmask, name1> {
180 let isAsmParserOnly = 1 in
181 defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
183 defm AsmJH : IntCondExtendedMnemonic<2, "h", "nle">;
184 defm AsmJL : IntCondExtendedMnemonic<4, "l", "nhe">;
185 defm AsmJLH : IntCondExtendedMnemonic<6, "lh", "ne">;
186 defm AsmJE : IntCondExtendedMnemonic<8, "e", "nlh">;
187 defm AsmJHE : IntCondExtendedMnemonic<10, "he", "nl">;
188 defm AsmJLE : IntCondExtendedMnemonic<12, "le", "nh">;
190 // Decrement a register and branch if it is nonzero. These don't clobber CC,
191 // but we might need to split long branches into sequences that do.
193 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>;
194 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>;
197 //===----------------------------------------------------------------------===//
198 // Select instructions
199 //===----------------------------------------------------------------------===//
201 def Select32Mux : SelectWrapper<GRX32>, Requires<[FeatureHighWord]>;
202 def Select32 : SelectWrapper<GR32>;
203 def Select64 : SelectWrapper<GR64>;
205 // We don't define 32-bit Mux stores because the low-only STOC should
206 // always be used if possible.
207 defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8,
208 nonvolatile_anyextloadi8, bdxaddr20only>,
209 Requires<[FeatureHighWord]>;
210 defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16,
211 nonvolatile_anyextloadi16, bdxaddr20only>,
212 Requires<[FeatureHighWord]>;
213 defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8,
214 nonvolatile_anyextloadi8, bdxaddr20only>;
215 defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16,
216 nonvolatile_anyextloadi16, bdxaddr20only>;
217 defm CondStore32 : CondStores<GR32, nonvolatile_store,
218 nonvolatile_load, bdxaddr20only>;
220 defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8,
221 nonvolatile_anyextloadi8, bdxaddr20only>;
222 defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16,
223 nonvolatile_anyextloadi16, bdxaddr20only>;
224 defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32,
225 nonvolatile_anyextloadi32, bdxaddr20only>;
226 defm CondStore64 : CondStores<GR64, nonvolatile_store,
227 nonvolatile_load, bdxaddr20only>;
229 //===----------------------------------------------------------------------===//
231 //===----------------------------------------------------------------------===//
233 // The definitions here are for the call-clobbered registers.
234 let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
235 F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D, CC] in {
236 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops),
237 [(z_call pcrel32:$I2)]>;
238 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops),
239 [(z_call ADDR64:$R2)]>;
242 // Sibling calls. Indirect sibling calls must be via R1, since R2 upwards
243 // are argument registers and since branching to R0 is a no-op.
244 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
245 def CallJG : Alias<6, (outs), (ins pcrel32:$I2),
246 [(z_sibcall pcrel32:$I2)]>;
248 def CallBR : Alias<2, (outs), (ins), [(z_sibcall R1D)]>;
251 // Define the general form of the call instructions for the asm parser.
252 // These instructions don't hard-code %r14 as the return address register.
253 def BRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2),
254 "bras\t$R1, $I2", []>;
255 def BRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2),
256 "brasl\t$R1, $I2", []>;
257 def BASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
258 "basr\t$R1, $R2", []>;
260 //===----------------------------------------------------------------------===//
262 //===----------------------------------------------------------------------===//
265 let neverHasSideEffects = 1 in {
266 // Expands to LR, RISBHG or RISBLG, depending on the choice of registers.
267 def LRMux : UnaryRRPseudo<"l", null_frag, GRX32, GRX32>,
268 Requires<[FeatureHighWord]>;
269 def LR : UnaryRR <"l", 0x18, null_frag, GR32, GR32>;
270 def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
272 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
273 def LTR : UnaryRR <"lt", 0x12, null_frag, GR32, GR32>;
274 def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>;
277 // Move on condition.
278 let isCodeGenOnly = 1, Uses = [CC] in {
279 def LOCR : CondUnaryRRF<"loc", 0xB9F2, GR32, GR32>;
280 def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
283 def AsmLOCR : AsmCondUnaryRRF<"loc", 0xB9F2, GR32, GR32>;
284 def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
288 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
289 isReMaterializable = 1 in {
290 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF,
291 // deopending on the choice of register.
292 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>,
293 Requires<[FeatureHighWord]>;
294 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>;
295 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
297 // Other 16-bit immediates.
298 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
299 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
300 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
301 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
303 // 32-bit immediates.
304 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>;
305 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
306 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
310 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
311 // Expands to L, LY or LFH, depending on the choice of register.
312 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>,
313 Requires<[FeatureHighWord]>;
314 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
315 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>,
316 Requires<[FeatureHighWord]>;
317 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
319 // These instructions are split after register allocation, so we don't
320 // want a custom inserter.
321 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
322 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
323 [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
326 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
327 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>;
328 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>;
331 let canFoldAsLoad = 1 in {
332 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;
333 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
336 // Load on condition.
337 let isCodeGenOnly = 1, Uses = [CC] in {
338 def LOC : CondUnaryRSY<"loc", 0xEBF2, nonvolatile_load, GR32, 4>;
339 def LOCG : CondUnaryRSY<"locg", 0xEBE2, nonvolatile_load, GR64, 8>;
342 def AsmLOC : AsmCondUnaryRSY<"loc", 0xEBF2, GR32, 4>;
343 def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
347 let SimpleBDXStore = 1 in {
348 // Expands to ST, STY or STFH, depending on the choice of register.
349 def STMux : StoreRXYPseudo<store, GRX32, 4>,
350 Requires<[FeatureHighWord]>;
351 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
352 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>,
353 Requires<[FeatureHighWord]>;
354 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
356 // These instructions are split after register allocation, so we don't
357 // want a custom inserter.
358 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
359 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
360 [(store GR128:$src, bdxaddr20only128:$dst)]>;
363 def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
364 def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
366 // Store on condition.
367 let isCodeGenOnly = 1, Uses = [CC] in {
368 def STOC : CondStoreRSY<"stoc", 0xEBF3, GR32, 4>;
369 def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
372 def AsmSTOC : AsmCondStoreRSY<"stoc", 0xEBF3, GR32, 4>;
373 def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
376 // 8-bit immediate stores to 8-bit fields.
377 defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
379 // 16-bit immediate stores to 16-, 32- or 64-bit fields.
380 def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
381 def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>;
382 def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>;
384 // Memory-to-memory moves.
385 let mayLoad = 1, mayStore = 1 in
386 defm MVC : MemorySS<"mvc", 0xD2, z_mvc, z_mvc_loop>;
389 let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L] in
390 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>;
392 //===----------------------------------------------------------------------===//
394 //===----------------------------------------------------------------------===//
396 // Note that putting these before zero extensions mean that we will prefer
397 // them for anyextload*. There's not really much to choose between the two
398 // either way, but signed-extending loads have a short LH and a long LHY,
399 // while zero-extending loads have only the long LLH.
401 //===----------------------------------------------------------------------===//
403 // 32-bit extensions from registers.
404 let neverHasSideEffects = 1 in {
405 def LBR : UnaryRRE<"lb", 0xB926, sext8, GR32, GR32>;
406 def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
409 // 64-bit extensions from registers.
410 let neverHasSideEffects = 1 in {
411 def LGBR : UnaryRRE<"lgb", 0xB906, sext8, GR64, GR64>;
412 def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
413 def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
415 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
416 def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR64>;
418 // Match 32-to-64-bit sign extensions in which the source is already
419 // in a 64-bit register.
420 def : Pat<(sext_inreg GR64:$src, i32),
421 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
423 // 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH,
424 // depending on the choice of register.
425 def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>,
426 Requires<[FeatureHighWord]>;
427 def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>;
428 def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>,
429 Requires<[FeatureHighWord]>;
431 // 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH,
432 // depending on the choice of register.
433 def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>,
434 Requires<[FeatureHighWord]>;
435 defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>;
436 def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>,
437 Requires<[FeatureHighWord]>;
438 def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>;
440 // 64-bit extensions from memory.
441 def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>;
442 def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>;
443 def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>;
444 def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>;
445 def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>;
446 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
447 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>;
449 //===----------------------------------------------------------------------===//
451 //===----------------------------------------------------------------------===//
453 // 32-bit extensions from registers.
454 let neverHasSideEffects = 1 in {
455 // Expands to LLCR or RISB[LH]G, depending on the choice of registers.
456 def LLCRMux : UnaryRRPseudo<"llc", zext8, GRX32, GRX32>,
457 Requires<[FeatureHighWord]>;
458 def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>;
459 // Expands to LLHR or RISB[LH]G, depending on the choice of registers.
460 def LLHRMux : UnaryRRPseudo<"llh", zext16, GRX32, GRX32>,
461 Requires<[FeatureHighWord]>;
462 def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
465 // 64-bit extensions from registers.
466 let neverHasSideEffects = 1 in {
467 def LLGCR : UnaryRRE<"llgc", 0xB984, zext8, GR64, GR64>;
468 def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
469 def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
472 // Match 32-to-64-bit zero extensions in which the source is already
473 // in a 64-bit register.
474 def : Pat<(and GR64:$src, 0xffffffff),
475 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>;
477 // 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH,
478 // depending on the choice of register.
479 def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>,
480 Requires<[FeatureHighWord]>;
481 def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>;
482 def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GR32, 1>,
483 Requires<[FeatureHighWord]>;
485 // 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH,
486 // depending on the choice of register.
487 def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>,
488 Requires<[FeatureHighWord]>;
489 def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>;
490 def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GR32, 2>,
491 Requires<[FeatureHighWord]>;
492 def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>;
494 // 64-bit extensions from memory.
495 def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>;
496 def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>;
497 def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>;
498 def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>;
499 def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>;
501 //===----------------------------------------------------------------------===//
503 //===----------------------------------------------------------------------===//
505 // Truncations of 64-bit registers to 32-bit registers.
506 def : Pat<(i32 (trunc GR64:$src)),
507 (EXTRACT_SUBREG GR64:$src, subreg_l32)>;
509 // Truncations of 32-bit registers to 8-bit memory. STCMux expands to
510 // STC, STCY or STCH, depending on the choice of register.
511 def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>,
512 Requires<[FeatureHighWord]>;
513 defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
514 def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>,
515 Requires<[FeatureHighWord]>;
517 // Truncations of 32-bit registers to 16-bit memory. STHMux expands to
518 // STH, STHY or STHH, depending on the choice of register.
519 def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>,
520 Requires<[FeatureHighWord]>;
521 defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
522 def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>,
523 Requires<[FeatureHighWord]>;
524 def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
526 // Truncations of 64-bit registers to memory.
527 defm : StoreGR64Pair<STC, STCY, truncstorei8>;
528 defm : StoreGR64Pair<STH, STHY, truncstorei16>;
529 def : StoreGR64PC<STHRL, aligned_truncstorei16>;
530 defm : StoreGR64Pair<ST, STY, truncstorei32>;
531 def : StoreGR64PC<STRL, aligned_truncstorei32>;
533 //===----------------------------------------------------------------------===//
534 // Multi-register moves
535 //===----------------------------------------------------------------------===//
537 // Multi-register loads.
538 def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
540 // Multi-register stores.
541 def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
543 //===----------------------------------------------------------------------===//
545 //===----------------------------------------------------------------------===//
547 // Byte-swapping register moves.
548 let neverHasSideEffects = 1 in {
549 def LRVR : UnaryRRE<"lrv", 0xB91F, bswap, GR32, GR32>;
550 def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
553 // Byte-swapping loads. Unlike normal loads, these instructions are
554 // allowed to access storage more than once.
555 def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>;
556 def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>;
558 // Likewise byte-swapping stores.
559 def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>;
560 def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>,
563 //===----------------------------------------------------------------------===//
564 // Load address instructions
565 //===----------------------------------------------------------------------===//
567 // Load BDX-style addresses.
568 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
570 let DispSize = "12" in
571 def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
573 [(set GR64:$R1, laaddr12pair:$XBD2)]>;
574 let DispSize = "20" in
575 def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
577 [(set GR64:$R1, laaddr20pair:$XBD2)]>;
580 // Load a PC-relative address. There's no version of this instruction
581 // with a 16-bit offset, so there's no relaxation.
582 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
583 isReMaterializable = 1 in {
584 def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
586 [(set GR64:$R1, pcrel32:$I2)]>;
589 //===----------------------------------------------------------------------===//
590 // Absolute and Negation
591 //===----------------------------------------------------------------------===//
594 let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
595 def LPR : UnaryRR <"lp", 0x10, z_iabs32, GR32, GR32>;
596 def LPGR : UnaryRRE<"lpg", 0xB900, z_iabs64, GR64, GR64>;
598 let CCValues = 0xE, CompareZeroCCMask = 0xE in
599 def LPGFR : UnaryRRE<"lpgf", 0xB910, null_frag, GR64, GR32>;
601 defm : SXU<z_iabs64, LPGFR>;
604 let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
605 def LNR : UnaryRR <"ln", 0x11, z_inegabs32, GR32, GR32>;
606 def LNGR : UnaryRRE<"lng", 0xB901, z_inegabs64, GR64, GR64>;
608 let CCValues = 0xE, CompareZeroCCMask = 0xE in
609 def LNGFR : UnaryRRE<"lngf", 0xB911, null_frag, GR64, GR32>;
611 defm : SXU<z_inegabs64, LNGFR>;
614 let CCValues = 0xF, CompareZeroCCMask = 0x8 in {
615 def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>;
616 def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
618 let CCValues = 0xE, CompareZeroCCMask = 0xE in
619 def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>;
621 defm : SXU<ineg, LCGFR>;
623 //===----------------------------------------------------------------------===//
625 //===----------------------------------------------------------------------===//
627 let isCodeGenOnly = 1 in
628 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>;
629 defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>;
631 defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>;
632 defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>;
634 defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>;
635 defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>;
637 // Insertions of a 16-bit immediate, leaving other bits unaffected.
638 // We don't have or_as_insert equivalents of these operations because
639 // OI is available instead.
641 // IIxMux expands to II[LH]x, depending on the choice of register.
642 def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>,
643 Requires<[FeatureHighWord]>;
644 def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>,
645 Requires<[FeatureHighWord]>;
646 def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
647 def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
648 def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>;
649 def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>;
650 def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>;
651 def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>;
652 def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>;
653 def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>;
655 // ...likewise for 32-bit immediates. For GR32s this is a general
656 // full-width move. (We use IILF rather than something like LLILF
657 // for 32-bit moves because IILF leaves the upper 32 bits of the
659 let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
660 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>,
661 Requires<[FeatureHighWord]>;
662 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
663 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>;
665 def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>;
666 def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>;
668 // An alternative model of inserthf, with the first operand being
669 // a zero-extended value.
670 def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
671 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32),
674 //===----------------------------------------------------------------------===//
676 //===----------------------------------------------------------------------===//
679 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
680 // Addition of a register.
681 let isCommutable = 1 in {
682 defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
683 defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
685 def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
687 // Addition of signed 16-bit immediates.
688 defm AHIMux : BinaryRIAndKPseudo<"ahimux", add, GRX32, imm32sx16>;
689 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>;
690 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
692 // Addition of signed 32-bit immediates.
693 def AFIMux : BinaryRIPseudo<add, GRX32, simm32>,
694 Requires<[FeatureHighWord]>;
695 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>;
696 def AIH : BinaryRIL<"aih", 0xCC8, add, GRH32, simm32>,
697 Requires<[FeatureHighWord]>;
698 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
700 // Addition of memory.
701 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>;
702 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>;
703 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>;
704 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>;
706 // Addition to memory.
707 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>;
708 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
710 defm : SXB<add, GR64, AGFR>;
712 // Addition producing a carry.
714 // Addition of a register.
715 let isCommutable = 1 in {
716 defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>;
717 defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>;
719 def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
721 // Addition of signed 16-bit immediates.
722 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>,
723 Requires<[FeatureDistinctOps]>;
724 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>,
725 Requires<[FeatureDistinctOps]>;
727 // Addition of unsigned 32-bit immediates.
728 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>;
729 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
731 // Addition of memory.
732 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>;
733 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, azextloadi32, 4>;
734 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>;
736 defm : ZXB<addc, GR64, ALGFR>;
738 // Addition producing and using a carry.
739 let Defs = [CC], Uses = [CC] in {
740 // Addition of a register.
741 def ALCR : BinaryRRE<"alc", 0xB998, adde, GR32, GR32>;
742 def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>;
744 // Addition of memory.
745 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>;
746 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>;
749 //===----------------------------------------------------------------------===//
751 //===----------------------------------------------------------------------===//
753 // Plain substraction. Although immediate forms exist, we use the
754 // add-immediate instruction instead.
755 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in {
756 // Subtraction of a register.
757 defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
758 def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
759 defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
761 // Subtraction of memory.
762 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>;
763 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>;
764 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>;
765 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>;
767 defm : SXB<sub, GR64, SGFR>;
769 // Subtraction producing a carry.
771 // Subtraction of a register.
772 defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
773 def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
774 defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
776 // Subtraction of unsigned 32-bit immediates. These don't match
777 // subc because we prefer addc for constants.
778 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>;
779 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
781 // Subtraction of memory.
782 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
783 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, azextloadi32, 4>;
784 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>;
786 defm : ZXB<subc, GR64, SLGFR>;
788 // Subtraction producing and using a carry.
789 let Defs = [CC], Uses = [CC] in {
790 // Subtraction of a register.
791 def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>;
792 def SLGBR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
794 // Subtraction of memory.
795 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>;
796 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
799 //===----------------------------------------------------------------------===//
801 //===----------------------------------------------------------------------===//
804 // ANDs of a register.
805 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
806 defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>;
807 defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>;
810 let isConvertibleToThreeAddress = 1 in {
811 // ANDs of a 16-bit immediate, leaving other bits unaffected.
812 // The CC result only reflects the 16-bit field, not the full register.
814 // NIxMux expands to NI[LH]x, depending on the choice of register.
815 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>,
816 Requires<[FeatureHighWord]>;
817 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>,
818 Requires<[FeatureHighWord]>;
819 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
820 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
821 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>;
822 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>;
823 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>;
824 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>;
825 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>;
826 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>;
828 // ANDs of a 32-bit immediate, leaving other bits unaffected.
829 // The CC result only reflects the 32-bit field, which means we can
830 // use it as a zero indicator for i32 operations but not otherwise.
831 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
832 // Expands to NILF or NIHF, depending on the choice of register.
833 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>,
834 Requires<[FeatureHighWord]>;
835 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
836 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>;
838 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>;
839 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>;
843 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
844 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>;
845 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>;
849 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>;
852 let mayLoad = 1, mayStore = 1 in
853 defm NC : MemorySS<"nc", 0xD4, z_nc, z_nc_loop>;
855 defm : RMWIByte<and, bdaddr12pair, NI>;
856 defm : RMWIByte<and, bdaddr20pair, NIY>;
858 //===----------------------------------------------------------------------===//
860 //===----------------------------------------------------------------------===//
863 // ORs of a register.
864 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
865 defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>;
866 defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>;
869 // ORs of a 16-bit immediate, leaving other bits unaffected.
870 // The CC result only reflects the 16-bit field, not the full register.
872 // OIxMux expands to OI[LH]x, depending on the choice of register.
873 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>,
874 Requires<[FeatureHighWord]>;
875 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>,
876 Requires<[FeatureHighWord]>;
877 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
878 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
879 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>;
880 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>;
881 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>;
882 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>;
883 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>;
884 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>;
886 // ORs of a 32-bit immediate, leaving other bits unaffected.
887 // The CC result only reflects the 32-bit field, which means we can
888 // use it as a zero indicator for i32 operations but not otherwise.
889 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
890 // Expands to OILF or OIHF, depending on the choice of register.
891 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>,
892 Requires<[FeatureHighWord]>;
893 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
894 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>;
896 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>;
897 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>;
900 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
901 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>;
902 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>;
906 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>;
909 let mayLoad = 1, mayStore = 1 in
910 defm OC : MemorySS<"oc", 0xD6, z_oc, z_oc_loop>;
912 defm : RMWIByte<or, bdaddr12pair, OI>;
913 defm : RMWIByte<or, bdaddr20pair, OIY>;
915 //===----------------------------------------------------------------------===//
917 //===----------------------------------------------------------------------===//
920 // XORs of a register.
921 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in {
922 defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>;
923 defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>;
926 // XORs of a 32-bit immediate, leaving other bits unaffected.
927 // The CC result only reflects the 32-bit field, which means we can
928 // use it as a zero indicator for i32 operations but not otherwise.
929 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
930 // Expands to XILF or XIHF, depending on the choice of register.
931 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>,
932 Requires<[FeatureHighWord]>;
933 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
934 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>;
936 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>;
937 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>;
940 let CCValues = 0xC, CompareZeroCCMask = 0x8 in {
941 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>;
942 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>;
946 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>;
949 let mayLoad = 1, mayStore = 1 in
950 defm XC : MemorySS<"xc", 0xD7, z_xc, z_xc_loop>;
952 defm : RMWIByte<xor, bdaddr12pair, XI>;
953 defm : RMWIByte<xor, bdaddr20pair, XIY>;
955 //===----------------------------------------------------------------------===//
957 //===----------------------------------------------------------------------===//
959 // Multiplication of a register.
960 let isCommutable = 1 in {
961 def MSR : BinaryRRE<"ms", 0xB252, mul, GR32, GR32>;
962 def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>;
964 def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>;
965 defm : SXB<mul, GR64, MSGFR>;
967 // Multiplication of a signed 16-bit immediate.
968 def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>;
969 def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
971 // Multiplication of a signed 32-bit immediate.
972 def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>;
973 def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
975 // Multiplication of memory.
976 defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>;
977 defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
978 def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>;
979 def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>;
981 // Multiplication of a register, producing two results.
982 def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>;
984 // Multiplication of memory, producing two results.
985 def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
987 //===----------------------------------------------------------------------===//
988 // Division and remainder
989 //===----------------------------------------------------------------------===//
991 // Division and remainder, from registers.
992 def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>;
993 def DSGR : BinaryRRE<"dsg", 0xB90D, z_sdivrem64, GR128, GR64>;
994 def DLR : BinaryRRE<"dl", 0xB997, z_udivrem32, GR128, GR32>;
995 def DLGR : BinaryRRE<"dlg", 0xB987, z_udivrem64, GR128, GR64>;
997 // Division and remainder, from memory.
998 def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
999 def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load, 8>;
1000 def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load, 4>;
1001 def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>;
1003 //===----------------------------------------------------------------------===//
1005 //===----------------------------------------------------------------------===//
1008 let neverHasSideEffects = 1 in {
1009 defm SLL : ShiftRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
1010 def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64>;
1013 // Logical shift right.
1014 let neverHasSideEffects = 1 in {
1015 defm SRL : ShiftRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
1016 def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64>;
1019 // Arithmetic shift right.
1020 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
1021 defm SRA : ShiftRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
1022 def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64>;
1026 let neverHasSideEffects = 1 in {
1027 def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32>;
1028 def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64>;
1031 // Rotate second operand left and inserted selected bits into first operand.
1032 // These can act like 32-bit operands provided that the constant start and
1033 // end bits (operands 2 and 3) are in the range [32, 64).
1034 let Defs = [CC] in {
1035 let isCodeGenOnly = 1 in
1036 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
1037 let CCValues = 0xE, CompareZeroCCMask = 0xE in
1038 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
1041 // Forms of RISBG that only affect one word of the destination register.
1042 // They do not set CC.
1043 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>, Requires<[FeatureHighWord]>;
1044 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>, Requires<[FeatureHighWord]>;
1045 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>, Requires<[FeatureHighWord]>;
1046 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>, Requires<[FeatureHighWord]>;
1047 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>, Requires<[FeatureHighWord]>;
1048 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>,
1049 Requires<[FeatureHighWord]>;
1050 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>,
1051 Requires<[FeatureHighWord]>;
1053 // Rotate second operand left and perform a logical operation with selected
1054 // bits of the first operand. The CC result only describes the selected bits,
1055 // so isn't useful for a full comparison against zero.
1056 let Defs = [CC] in {
1057 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
1058 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
1059 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
1062 //===----------------------------------------------------------------------===//
1064 //===----------------------------------------------------------------------===//
1066 // Signed comparisons. We put these before the unsigned comparisons because
1067 // some of the signed forms have COMPARE AND BRANCH equivalents whereas none
1068 // of the unsigned forms do.
1069 let Defs = [CC], CCValues = 0xE in {
1070 // Comparison with a register.
1071 def CR : CompareRR <"c", 0x19, z_scmp, GR32, GR32>;
1072 def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>;
1073 def CGR : CompareRRE<"cg", 0xB920, z_scmp, GR64, GR64>;
1075 // Comparison with a signed 16-bit immediate.
1076 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>;
1077 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>;
1079 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH,
1080 // depending on the choice of register.
1081 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>,
1082 Requires<[FeatureHighWord]>;
1083 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>;
1084 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>,
1085 Requires<[FeatureHighWord]>;
1086 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>;
1088 // Comparison with memory.
1089 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>;
1090 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>,
1091 Requires<[FeatureHighWord]>;
1092 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>;
1093 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>,
1094 Requires<[FeatureHighWord]>;
1095 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>;
1096 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>;
1097 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>;
1098 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>;
1099 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>;
1100 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>;
1101 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>;
1102 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>;
1104 // Comparison between memory and a signed 16-bit immediate.
1105 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>;
1106 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>;
1107 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>;
1109 defm : SXB<z_scmp, GR64, CGFR>;
1111 // Unsigned comparisons.
1112 let Defs = [CC], CCValues = 0xE, IsLogical = 1 in {
1113 // Comparison with a register.
1114 def CLR : CompareRR <"cl", 0x15, z_ucmp, GR32, GR32>;
1115 def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>;
1116 def CLGR : CompareRRE<"clg", 0xB921, z_ucmp, GR64, GR64>;
1118 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI
1119 // or CLIH, depending on the choice of register.
1120 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>,
1121 Requires<[FeatureHighWord]>;
1122 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>;
1123 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GR32, uimm32>,
1124 Requires<[FeatureHighWord]>;
1125 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
1127 // Comparison with memory.
1128 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>,
1129 Requires<[FeatureHighWord]>;
1130 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>;
1131 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>,
1132 Requires<[FeatureHighWord]>;
1133 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>;
1134 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>;
1135 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32,
1136 aligned_azextloadi16>;
1137 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32,
1139 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
1140 aligned_azextloadi16>;
1141 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
1142 aligned_azextloadi32>;
1143 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64,
1146 // Comparison between memory and an unsigned 8-bit immediate.
1147 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>;
1149 // Comparison between memory and an unsigned 16-bit immediate.
1150 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>;
1151 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
1152 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
1154 defm : ZXB<z_ucmp, GR64, CLGFR>;
1156 // Memory-to-memory comparison.
1157 let mayLoad = 1, Defs = [CC] in
1158 defm CLC : MemorySS<"clc", 0xD5, z_clc, z_clc_loop>;
1160 // String comparison.
1161 let mayLoad = 1, Defs = [CC], Uses = [R0L] in
1162 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>;
1165 let Defs = [CC] in {
1166 // TMxMux expands to TM[LH]x, depending on the choice of register.
1167 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>,
1168 Requires<[FeatureHighWord]>;
1169 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>,
1170 Requires<[FeatureHighWord]>;
1171 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>;
1172 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>;
1173 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>;
1174 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>;
1176 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>;
1178 def : CompareGR64RI<TMLL, z_tm_reg, imm64ll16, subreg_l32>;
1179 def : CompareGR64RI<TMLH, z_tm_reg, imm64lh16, subreg_l32>;
1180 def : CompareGR64RI<TMHL, z_tm_reg, imm64hl16, subreg_h32>;
1181 def : CompareGR64RI<TMHH, z_tm_reg, imm64hh16, subreg_h32>;
1183 //===----------------------------------------------------------------------===//
1185 //===----------------------------------------------------------------------===//
1187 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>;
1188 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>;
1190 //===----------------------------------------------------------------------===//
1191 // Atomic operations
1192 //===----------------------------------------------------------------------===//
1194 def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>;
1195 def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>;
1196 def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>;
1198 def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
1199 def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
1200 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>;
1201 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
1202 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
1203 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>;
1204 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
1205 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
1207 def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
1208 def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>;
1209 def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>;
1211 def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
1212 def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
1213 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>;
1214 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>;
1215 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>;
1216 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
1217 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>;
1218 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>;
1219 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>;
1220 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>;
1221 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>;
1222 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>;
1223 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>;
1225 def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
1226 def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
1227 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>;
1228 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
1229 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
1230 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
1231 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>;
1232 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
1233 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
1234 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
1235 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
1236 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
1237 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
1239 def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
1240 def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
1241 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>;
1242 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
1243 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>;
1244 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
1245 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
1247 def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
1248 def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
1250 def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>;
1251 def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32,
1253 def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32,
1255 def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
1256 def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>;
1257 def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1259 def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1261 def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1263 def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1265 def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1267 def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64,
1270 def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
1271 def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>;
1272 def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>;
1274 def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
1275 def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>;
1276 def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>;
1278 def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
1279 def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
1280 def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
1282 def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
1283 def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
1284 def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
1286 def ATOMIC_CMP_SWAPW
1287 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1288 ADDR32:$bitshift, ADDR32:$negbitshift,
1291 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1292 ADDR32:$bitshift, ADDR32:$negbitshift,
1293 uimm32:$bitsize))]> {
1297 let usesCustomInserter = 1;
1300 let Defs = [CC] in {
1301 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
1302 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
1305 //===----------------------------------------------------------------------===//
1306 // Miscellaneous Instructions.
1307 //===----------------------------------------------------------------------===//
1309 // Extract CC into bits 29 and 28 of a register.
1311 def IPM : InherentRRE<"ipm", 0xB222, GR32, (z_ipm)>;
1313 // Read a 32-bit access register into a GR32. As with all GR32 operations,
1314 // the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
1315 // when a 64-bit address is stored in a pair of access registers.
1316 def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
1318 [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
1320 // Find leftmost one, AKA count leading zeros. The instruction actually
1321 // returns a pair of GR64s, the first giving the number of leading zeros
1322 // and the second giving a copy of the source with the leftmost one bit
1323 // cleared. We only use the first result here.
1324 let Defs = [CC] in {
1325 def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>;
1327 def : Pat<(ctlz GR64:$src),
1328 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>;
1330 // Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
1331 def : Pat<(i64 (anyext GR32:$src)),
1332 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
1334 // Extend GR32s and GR64s to GR128s.
1335 let usesCustomInserter = 1 in {
1336 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1337 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
1338 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1341 // Search a block of memory for a character.
1342 let mayLoad = 1, Defs = [CC], Uses = [R0L] in
1343 defm SRST : StringRRE<"srst", 0xb25e, z_search_string>;
1345 //===----------------------------------------------------------------------===//
1347 //===----------------------------------------------------------------------===//
1349 // Use AL* for GR64 additions of unsigned 32-bit values.
1350 defm : ZXB<add, GR64, ALGFR>;
1351 def : Pat<(add GR64:$src1, imm64zx32:$src2),
1352 (ALGFI GR64:$src1, imm64zx32:$src2)>;
1353 def : Pat<(add GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1354 (ALGF GR64:$src1, bdxaddr20only:$addr)>;
1356 // Use SL* for GR64 subtractions of unsigned 32-bit values.
1357 defm : ZXB<sub, GR64, SLGFR>;
1358 def : Pat<(add GR64:$src1, imm64zx32n:$src2),
1359 (SLGFI GR64:$src1, imm64zx32n:$src2)>;
1360 def : Pat<(sub GR64:$src1, (azextloadi32 bdxaddr20only:$addr)),
1361 (SLGF GR64:$src1, bdxaddr20only:$addr)>;
1363 // Optimize sign-extended 1/0 selects to -1/0 selects. This is important
1364 // for vector legalization.
1365 def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid, uimm8zx4:$cc)),
1368 (Select32 (LHI -1), (LHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
1369 def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, uimm8zx4:$valid,
1373 (Select64 (LGHI -1), (LGHI 0), uimm8zx4:$valid, uimm8zx4:$cc)>;
1375 // Peepholes for turning scalar operations into block operations.
1376 defm : BlockLoadStore<anyextloadi8, i32, MVCSequence, NCSequence, OCSequence,
1378 defm : BlockLoadStore<anyextloadi16, i32, MVCSequence, NCSequence, OCSequence,
1380 defm : BlockLoadStore<load, i32, MVCSequence, NCSequence, OCSequence,
1382 defm : BlockLoadStore<anyextloadi8, i64, MVCSequence, NCSequence,
1383 OCSequence, XCSequence, 1>;
1384 defm : BlockLoadStore<anyextloadi16, i64, MVCSequence, NCSequence, OCSequence,
1386 defm : BlockLoadStore<anyextloadi32, i64, MVCSequence, NCSequence, OCSequence,
1388 defm : BlockLoadStore<load, i64, MVCSequence, NCSequence, OCSequence,