1 //===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15 [(callseq_start timm:$amt)]>;
16 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17 [(callseq_end timm:$amt1, timm:$amt2)]>;
19 let neverHasSideEffects = 1 in {
20 // Takes as input the value of the stack pointer after a dynamic allocation
21 // has been made. Sets the output to the address of the dynamically-
22 // allocated area itself, skipping the outgoing arguments.
24 // This expands to an LA or LAY instruction. We restrict the offset
25 // to the range of LA and keep the LAY range in reserve for when
26 // the size of the outgoing arguments is added.
27 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28 [(set GR64:$dst, dynalloc12only:$src)]>;
31 //===----------------------------------------------------------------------===//
32 // Control flow instructions
33 //===----------------------------------------------------------------------===//
35 // A return instruction. R1 is the condition-code mask (all 1s)
36 // and R2 is the target address, which is always stored in %r14.
37 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1,
38 R1 = 15, R2 = 14, isCodeGenOnly = 1 in {
39 def RET : InstRR<0x07, (outs), (ins), "br\t%r14", [(z_retflag)]>;
42 // Unconditional branches. R1 is the condition-code mask (all 1s).
43 let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
44 let isIndirectBranch = 1 in
45 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
46 "br\t$R2", [(brind ADDR64:$R2)]>;
48 // An assembler extended mnemonic for BRC.
49 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
52 // An assembler extended mnemonic for BRCL. (The extension is "G"
53 // rather than "L" because "JL" is "Jump if Less".)
54 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
57 // Conditional branches. It's easier for LLVM to handle these branches
58 // in their raw BRC/BRCL form, with the 4-bit condition-code mask being
59 // the first operand. It seems friendlier to use mnemonic forms like
60 // JE and JLH when writing out the assembly though.
62 // Using a custom inserter for BRC gives us a chance to convert the BRC
63 // and a preceding compare into a single compare-and-branch instruction.
64 // The inserter makes no change in cases where a separate branch really
66 multiclass CondBranches<Operand ccmask, string short, string long> {
67 let isBranch = 1, isTerminator = 1, Uses = [CC] in {
68 def "" : InstRI<0xA74, (outs), (ins ccmask:$R1, brtarget16:$I2), short, []>;
69 def L : InstRIL<0xC04, (outs), (ins ccmask:$R1, brtarget32:$I2), long, []>;
72 let isCodeGenOnly = 1, usesCustomInserter = 1 in
73 defm BRC : CondBranches<cond4, "j$R1\t$I2", "jg$R1\t$I2">;
74 defm AsmBRC : CondBranches<uimm8zx4, "brc\t$R1, $I2", "brcl\t$R1, $I2">;
76 def : Pat<(z_br_ccmask cond4:$cond, bb:$dst), (BRC cond4:$cond, bb:$dst)>;
78 // Fused compare-and-branch instructions. As for normal branches,
79 // we handle these instructions internally in their raw CRJ-like form,
80 // but use assembly macros like CRJE when writing them out.
82 // These instructions do not use or clobber the condition codes.
83 // We nevertheless pretend that they clobber CC, so that we can lower
84 // them to separate comparisons and BRCLs if the branch ends up being
86 multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
87 let isBranch = 1, isTerminator = 1, Defs = [CC] in {
88 def RJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
90 "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
91 def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
93 "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
94 def IJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
96 "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
97 def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
99 "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
102 let isCodeGenOnly = 1 in
103 defm C : CompareBranches<cond4, "$M3", "">;
104 defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">;
106 // Define AsmParser mnemonics for each general condition-code mask
107 // (integer or floating-point)
108 multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
110 def "" : InstRI<0xA74, (outs), (ins brtarget16:$I2),
111 "j"##name##"\t$I2", []>;
112 def L : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
113 "jg"##name##"\t$I2", []>;
116 defm AsmJO : CondExtendedMnemonic<1, "o">;
117 defm AsmJH : CondExtendedMnemonic<2, "h">;
118 defm AsmJNLE : CondExtendedMnemonic<3, "nle">;
119 defm AsmJL : CondExtendedMnemonic<4, "l">;
120 defm AsmJNHE : CondExtendedMnemonic<5, "nhe">;
121 defm AsmJLH : CondExtendedMnemonic<6, "lh">;
122 defm AsmJNE : CondExtendedMnemonic<7, "ne">;
123 defm AsmJE : CondExtendedMnemonic<8, "e">;
124 defm AsmJNLH : CondExtendedMnemonic<9, "nlh">;
125 defm AsmJHE : CondExtendedMnemonic<10, "he">;
126 defm AsmJNL : CondExtendedMnemonic<11, "nl">;
127 defm AsmJLE : CondExtendedMnemonic<12, "le">;
128 defm AsmJNH : CondExtendedMnemonic<13, "nh">;
129 defm AsmJNO : CondExtendedMnemonic<14, "no">;
131 // Define AsmParser mnemonics for each integer condition-code mask.
132 // This is like the list above, except that condition 3 is not possible
133 // and that the low bit of the mask is therefore always 0. This means
134 // that each condition has two names. Conditions "o" and "no" are not used.
136 // We don't make one of the two names an alias of the other because
137 // we need the custom parsing routines to select the correct register class.
138 multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
140 def CR : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
142 "crj"##name##"\t$R1, $R2, $RI4", []>;
143 def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
145 "cgrj"##name##"\t$R1, $R2, $RI4", []>;
146 def CI : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
148 "cij"##name##"\t$R1, $I2, $RI4", []>;
149 def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
151 "cgij"##name##"\t$R1, $I2, $RI4", []>;
154 multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
155 : IntCondExtendedMnemonicA<ccmask, name1> {
156 let isAsmParserOnly = 1 in
157 defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
159 defm AsmJH : IntCondExtendedMnemonic<2, "h", "nle">;
160 defm AsmJL : IntCondExtendedMnemonic<4, "l", "nhe">;
161 defm AsmJLH : IntCondExtendedMnemonic<6, "lh", "ne">;
162 defm AsmJE : IntCondExtendedMnemonic<8, "e", "nlh">;
163 defm AsmJHE : IntCondExtendedMnemonic<10, "he", "nl">;
164 defm AsmJLE : IntCondExtendedMnemonic<12, "le", "nh">;
166 //===----------------------------------------------------------------------===//
167 // Select instructions
168 //===----------------------------------------------------------------------===//
170 def Select32 : SelectWrapper<GR32>;
171 def Select64 : SelectWrapper<GR64>;
173 defm CondStore8_32 : CondStores<GR32, nonvolatile_truncstorei8,
174 nonvolatile_anyextloadi8, bdxaddr20only>;
175 defm CondStore16_32 : CondStores<GR32, nonvolatile_truncstorei16,
176 nonvolatile_anyextloadi16, bdxaddr20only>;
177 defm CondStore32_32 : CondStores<GR32, nonvolatile_store,
178 nonvolatile_load, bdxaddr20only>;
180 defm CondStore8 : CondStores<GR64, nonvolatile_truncstorei8,
181 nonvolatile_anyextloadi8, bdxaddr20only>;
182 defm CondStore16 : CondStores<GR64, nonvolatile_truncstorei16,
183 nonvolatile_anyextloadi16, bdxaddr20only>;
184 defm CondStore32 : CondStores<GR64, nonvolatile_truncstorei32,
185 nonvolatile_anyextloadi32, bdxaddr20only>;
186 defm CondStore64 : CondStores<GR64, nonvolatile_store,
187 nonvolatile_load, bdxaddr20only>;
189 //===----------------------------------------------------------------------===//
191 //===----------------------------------------------------------------------===//
193 // The definitions here are for the call-clobbered registers.
194 let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
195 F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D],
196 R1 = 14, isCodeGenOnly = 1 in {
197 def BRAS : InstRI<0xA75, (outs), (ins pcrel16call:$I2, variable_ops),
198 "bras\t%r14, $I2", []>;
199 def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$I2, variable_ops),
200 "brasl\t%r14, $I2", [(z_call pcrel32call:$I2)]>;
201 def BASR : InstRR<0x0D, (outs), (ins ADDR64:$R2, variable_ops),
202 "basr\t%r14, $R2", [(z_call ADDR64:$R2)]>;
205 // Define the general form of the call instructions for the asm parser.
206 // These instructions don't hard-code %r14 as the return address register.
207 def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2),
208 "bras\t$R1, $I2", []>;
209 def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2),
210 "brasl\t$R1, $I2", []>;
211 def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
212 "basr\t$R1, $R2", []>;
214 //===----------------------------------------------------------------------===//
216 //===----------------------------------------------------------------------===//
219 let neverHasSideEffects = 1 in {
220 def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>;
221 def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>;
225 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
226 // 16-bit sign-extended immediates.
227 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>;
228 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
230 // Other 16-bit immediates.
231 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
232 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
233 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
234 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
236 // 32-bit immediates.
237 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>;
238 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
239 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
243 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
244 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32>;
245 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;
247 def LG : UnaryRXY<"lg", 0xE304, load, GR64>;
248 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
250 // These instructions are split after register allocation, so we don't
251 // want a custom inserter.
252 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
253 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
254 [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
259 let SimpleBDXStore = 1 in {
260 let isCodeGenOnly = 1 in {
261 defm ST32 : StoreRXPair<"st", 0x50, 0xE350, store, GR32>;
262 def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
265 def STG : StoreRXY<"stg", 0xE324, store, GR64>;
266 def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
268 // These instructions are split after register allocation, so we don't
269 // want a custom inserter.
270 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
271 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
272 [(store GR128:$src, bdxaddr20only128:$dst)]>;
276 // 8-bit immediate stores to 8-bit fields.
277 defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
279 // 16-bit immediate stores to 16-, 32- or 64-bit fields.
280 def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
281 def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>;
282 def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>;
284 //===----------------------------------------------------------------------===//
286 //===----------------------------------------------------------------------===//
288 // 32-bit extensions from registers.
289 let neverHasSideEffects = 1 in {
290 def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>;
291 def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>;
294 // 64-bit extensions from registers.
295 let neverHasSideEffects = 1 in {
296 def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>;
297 def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>;
298 def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>;
301 // Match 32-to-64-bit sign extensions in which the source is already
302 // in a 64-bit register.
303 def : Pat<(sext_inreg GR64:$src, i32),
304 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
306 // 32-bit extensions from memory.
307 def LB : UnaryRXY<"lb", 0xE376, sextloadi8, GR32>;
308 defm LH : UnaryRXPair<"lh", 0x48, 0xE378, sextloadi16, GR32>;
309 def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_sextloadi16, GR32>;
311 // 64-bit extensions from memory.
312 def LGB : UnaryRXY<"lgb", 0xE377, sextloadi8, GR64>;
313 def LGH : UnaryRXY<"lgh", 0xE315, sextloadi16, GR64>;
314 def LGF : UnaryRXY<"lgf", 0xE314, sextloadi32, GR64>;
315 def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_sextloadi16, GR64>;
316 def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_sextloadi32, GR64>;
318 // If the sign of a load-extend operation doesn't matter, use the signed ones.
319 // There's not really much to choose between the sign and zero extensions,
320 // but LH is more compact than LLH for small offsets.
321 def : Pat<(i32 (extloadi8 bdxaddr20only:$src)), (LB bdxaddr20only:$src)>;
322 def : Pat<(i32 (extloadi16 bdxaddr12pair:$src)), (LH bdxaddr12pair:$src)>;
323 def : Pat<(i32 (extloadi16 bdxaddr20pair:$src)), (LHY bdxaddr20pair:$src)>;
325 def : Pat<(i64 (extloadi8 bdxaddr20only:$src)), (LGB bdxaddr20only:$src)>;
326 def : Pat<(i64 (extloadi16 bdxaddr20only:$src)), (LGH bdxaddr20only:$src)>;
327 def : Pat<(i64 (extloadi32 bdxaddr20only:$src)), (LGF bdxaddr20only:$src)>;
329 //===----------------------------------------------------------------------===//
331 //===----------------------------------------------------------------------===//
333 // 32-bit extensions from registers.
334 let neverHasSideEffects = 1 in {
335 def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>;
336 def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>;
339 // 64-bit extensions from registers.
340 let neverHasSideEffects = 1 in {
341 def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>;
342 def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>;
343 def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>;
346 // Match 32-to-64-bit zero extensions in which the source is already
347 // in a 64-bit register.
348 def : Pat<(and GR64:$src, 0xffffffff),
349 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
351 // 32-bit extensions from memory.
352 def LLC : UnaryRXY<"llc", 0xE394, zextloadi8, GR32>;
353 def LLH : UnaryRXY<"llh", 0xE395, zextloadi16, GR32>;
354 def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_zextloadi16, GR32>;
356 // 64-bit extensions from memory.
357 def LLGC : UnaryRXY<"llgc", 0xE390, zextloadi8, GR64>;
358 def LLGH : UnaryRXY<"llgh", 0xE391, zextloadi16, GR64>;
359 def LLGF : UnaryRXY<"llgf", 0xE316, zextloadi32, GR64>;
360 def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_zextloadi16, GR64>;
361 def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_zextloadi32, GR64>;
363 //===----------------------------------------------------------------------===//
365 //===----------------------------------------------------------------------===//
367 // Truncations of 64-bit registers to 32-bit registers.
368 def : Pat<(i32 (trunc GR64:$src)),
369 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
371 // Truncations of 32-bit registers to memory.
372 let isCodeGenOnly = 1 in {
373 defm STC32 : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32>;
374 defm STH32 : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32>;
375 def STHRL32 : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
378 // Truncations of 64-bit registers to memory.
379 defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR64>;
380 defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR64>;
381 def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR64>;
382 defm ST : StoreRXPair<"st", 0x50, 0xE350, truncstorei32, GR64>;
383 def STRL : StoreRILPC<"strl", 0xC4F, aligned_truncstorei32, GR64>;
385 //===----------------------------------------------------------------------===//
386 // Multi-register moves
387 //===----------------------------------------------------------------------===//
389 // Multi-register loads.
390 def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
392 // Multi-register stores.
393 def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
395 //===----------------------------------------------------------------------===//
397 //===----------------------------------------------------------------------===//
399 // Byte-swapping register moves.
400 let neverHasSideEffects = 1 in {
401 def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>;
402 def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>;
405 // Byte-swapping loads. Unlike normal loads, these instructions are
406 // allowed to access storage more than once.
407 def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap, nonvolatile_load>, GR32>;
408 def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64>;
410 // Likewise byte-swapping stores.
411 def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32>;
412 def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>, GR64>;
414 //===----------------------------------------------------------------------===//
415 // Load address instructions
416 //===----------------------------------------------------------------------===//
418 // Load BDX-style addresses.
419 let neverHasSideEffects = 1, Function = "la" in {
420 let PairType = "12" in
421 def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
423 [(set GR64:$R1, laaddr12pair:$XBD2)]>;
424 let PairType = "20" in
425 def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
427 [(set GR64:$R1, laaddr20pair:$XBD2)]>;
430 // Load a PC-relative address. There's no version of this instruction
431 // with a 16-bit offset, so there's no relaxation.
432 let neverHasSideEffects = 1 in {
433 def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
435 [(set GR64:$R1, pcrel32:$I2)]>;
438 //===----------------------------------------------------------------------===//
440 //===----------------------------------------------------------------------===//
443 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>;
444 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>;
445 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>;
447 defm : SXU<ineg, LCGFR>;
449 //===----------------------------------------------------------------------===//
451 //===----------------------------------------------------------------------===//
453 let isCodeGenOnly = 1 in
454 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, zextloadi8>;
455 defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, zextloadi8>;
457 defm : InsertMem<"inserti8", IC32, GR32, zextloadi8, bdxaddr12pair>;
458 defm : InsertMem<"inserti8", IC32Y, GR32, zextloadi8, bdxaddr20pair>;
460 defm : InsertMem<"inserti8", IC, GR64, zextloadi8, bdxaddr12pair>;
461 defm : InsertMem<"inserti8", ICY, GR64, zextloadi8, bdxaddr20pair>;
463 // Insertions of a 16-bit immediate, leaving other bits unaffected.
464 // We don't have or_as_insert equivalents of these operations because
465 // OI is available instead.
466 let isCodeGenOnly = 1 in {
467 def IILL32 : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
468 def IILH32 : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
470 def IILL : BinaryRI<"iill", 0xA53, insertll, GR64, imm64ll16>;
471 def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR64, imm64lh16>;
472 def IIHL : BinaryRI<"iihl", 0xA51, inserthl, GR64, imm64hl16>;
473 def IIHH : BinaryRI<"iihh", 0xA50, inserthh, GR64, imm64hh16>;
475 // ...likewise for 32-bit immediates. For GR32s this is a general
476 // full-width move. (We use IILF rather than something like LLILF
477 // for 32-bit moves because IILF leaves the upper 32 bits of the
479 let isCodeGenOnly = 1 in {
480 def IILF32 : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
482 def IILF : BinaryRIL<"iilf", 0xC09, insertlf, GR64, imm64lf32>;
483 def IIHF : BinaryRIL<"iihf", 0xC08, inserthf, GR64, imm64hf32>;
485 // An alternative model of inserthf, with the first operand being
486 // a zero-extended value.
487 def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
488 (IIHF (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit),
491 //===----------------------------------------------------------------------===//
493 //===----------------------------------------------------------------------===//
497 // Addition of a register.
498 let isCommutable = 1 in {
499 def AR : BinaryRR <"ar", 0x1A, add, GR32, GR32>;
500 def AGR : BinaryRRE<"agr", 0xB908, add, GR64, GR64>;
502 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>;
504 // Addition of signed 16-bit immediates.
505 def AHI : BinaryRI<"ahi", 0xA7A, add, GR32, imm32sx16>;
506 def AGHI : BinaryRI<"aghi", 0xA7B, add, GR64, imm64sx16>;
508 // Addition of signed 32-bit immediates.
509 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>;
510 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
512 // Addition of memory.
513 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, sextloadi16>;
514 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load>;
515 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, sextloadi32>;
516 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load>;
518 // Addition to memory.
519 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>;
520 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
522 defm : SXB<add, GR64, AGFR>;
524 // Addition producing a carry.
526 // Addition of a register.
527 let isCommutable = 1 in {
528 def ALR : BinaryRR <"alr", 0x1E, addc, GR32, GR32>;
529 def ALGR : BinaryRRE<"algr", 0xB90A, addc, GR64, GR64>;
531 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>;
533 // Addition of unsigned 32-bit immediates.
534 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>;
535 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
537 // Addition of memory.
538 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load>;
539 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, zextloadi32>;
540 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load>;
542 defm : ZXB<addc, GR64, ALGFR>;
544 // Addition producing and using a carry.
545 let Defs = [CC], Uses = [CC] in {
546 // Addition of a register.
547 def ALCR : BinaryRRE<"alcr", 0xB998, adde, GR32, GR32>;
548 def ALCGR : BinaryRRE<"alcgr", 0xB988, adde, GR64, GR64>;
550 // Addition of memory.
551 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load>;
552 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load>;
555 //===----------------------------------------------------------------------===//
557 //===----------------------------------------------------------------------===//
559 // Plain substraction. Although immediate forms exist, we use the
560 // add-immediate instruction instead.
562 // Subtraction of a register.
563 def SR : BinaryRR <"sr", 0x1B, sub, GR32, GR32>;
564 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>;
565 def SGR : BinaryRRE<"sgr", 0xB909, sub, GR64, GR64>;
567 // Subtraction of memory.
568 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, sextloadi16>;
569 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load>;
570 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, sextloadi32>;
571 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load>;
573 defm : SXB<sub, GR64, SGFR>;
575 // Subtraction producing a carry.
577 // Subtraction of a register.
578 def SLR : BinaryRR <"slr", 0x1F, subc, GR32, GR32>;
579 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>;
580 def SLGR : BinaryRRE<"slgr", 0xB90B, subc, GR64, GR64>;
582 // Subtraction of unsigned 32-bit immediates. These don't match
583 // subc because we prefer addc for constants.
584 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>;
585 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
587 // Subtraction of memory.
588 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load>;
589 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, zextloadi32>;
590 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load>;
592 defm : ZXB<subc, GR64, SLGFR>;
594 // Subtraction producing and using a carry.
595 let Defs = [CC], Uses = [CC] in {
596 // Subtraction of a register.
597 def SLBR : BinaryRRE<"slbr", 0xB999, sube, GR32, GR32>;
598 def SLGBR : BinaryRRE<"slbgr", 0xB989, sube, GR64, GR64>;
600 // Subtraction of memory.
601 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load>;
602 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load>;
605 //===----------------------------------------------------------------------===//
607 //===----------------------------------------------------------------------===//
610 // ANDs of a register.
611 let isCommutable = 1 in {
612 def NR : BinaryRR <"nr", 0x14, and, GR32, GR32>;
613 def NGR : BinaryRRE<"ngr", 0xB980, and, GR64, GR64>;
616 // ANDs of a 16-bit immediate, leaving other bits unaffected.
617 let isCodeGenOnly = 1 in {
618 def NILL32 : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
619 def NILH32 : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
621 def NILL : BinaryRI<"nill", 0xA57, and, GR64, imm64ll16c>;
622 def NILH : BinaryRI<"nilh", 0xA56, and, GR64, imm64lh16c>;
623 def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>;
624 def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>;
626 // ANDs of a 32-bit immediate, leaving other bits unaffected.
627 let isCodeGenOnly = 1 in
628 def NILF32 : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
629 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR64, imm64lf32c>;
630 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>;
633 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load>;
634 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load>;
637 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>;
639 defm : RMWIByte<and, bdaddr12pair, NI>;
640 defm : RMWIByte<and, bdaddr20pair, NIY>;
642 //===----------------------------------------------------------------------===//
644 //===----------------------------------------------------------------------===//
647 // ORs of a register.
648 let isCommutable = 1 in {
649 def OR : BinaryRR <"or", 0x16, or, GR32, GR32>;
650 def OGR : BinaryRRE<"ogr", 0xB981, or, GR64, GR64>;
653 // ORs of a 16-bit immediate, leaving other bits unaffected.
654 let isCodeGenOnly = 1 in {
655 def OILL32 : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
656 def OILH32 : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
658 def OILL : BinaryRI<"oill", 0xA5B, or, GR64, imm64ll16>;
659 def OILH : BinaryRI<"oilh", 0xA5A, or, GR64, imm64lh16>;
660 def OIHL : BinaryRI<"oihl", 0xA59, or, GR64, imm64hl16>;
661 def OIHH : BinaryRI<"oihh", 0xA58, or, GR64, imm64hh16>;
663 // ORs of a 32-bit immediate, leaving other bits unaffected.
664 let isCodeGenOnly = 1 in
665 def OILF32 : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
666 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR64, imm64lf32>;
667 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GR64, imm64hf32>;
670 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load>;
671 def OG : BinaryRXY<"og", 0xE381, or, GR64, load>;
674 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>;
676 defm : RMWIByte<or, bdaddr12pair, OI>;
677 defm : RMWIByte<or, bdaddr20pair, OIY>;
679 //===----------------------------------------------------------------------===//
681 //===----------------------------------------------------------------------===//
684 // XORs of a register.
685 let isCommutable = 1 in {
686 def XR : BinaryRR <"xr", 0x17, xor, GR32, GR32>;
687 def XGR : BinaryRRE<"xgr", 0xB982, xor, GR64, GR64>;
690 // XORs of a 32-bit immediate, leaving other bits unaffected.
691 let isCodeGenOnly = 1 in
692 def XILF32 : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
693 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR64, imm64lf32>;
694 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>;
697 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load>;
698 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load>;
701 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>;
703 defm : RMWIByte<xor, bdaddr12pair, XI>;
704 defm : RMWIByte<xor, bdaddr20pair, XIY>;
706 //===----------------------------------------------------------------------===//
708 //===----------------------------------------------------------------------===//
710 // Multiplication of a register.
711 let isCommutable = 1 in {
712 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>;
713 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>;
715 def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>;
716 defm : SXB<mul, GR64, MSGFR>;
718 // Multiplication of a signed 16-bit immediate.
719 def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>;
720 def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
722 // Multiplication of a signed 32-bit immediate.
723 def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>;
724 def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
726 // Multiplication of memory.
727 defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, sextloadi16>;
728 defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load>;
729 def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, sextloadi32>;
730 def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load>;
732 // Multiplication of a register, producing two results.
733 def MLGR : BinaryRRE<"mlgr", 0xB986, z_umul_lohi64, GR128, GR64>;
735 // Multiplication of memory, producing two results.
736 def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load>;
738 //===----------------------------------------------------------------------===//
739 // Division and remainder
740 //===----------------------------------------------------------------------===//
742 // Division and remainder, from registers.
743 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>;
744 def DSGR : BinaryRRE<"dsgr", 0xB90D, z_sdivrem64, GR128, GR64>;
745 def DLR : BinaryRRE<"dlr", 0xB997, z_udivrem32, GR128, GR32>;
746 def DLGR : BinaryRRE<"dlgr", 0xB987, z_udivrem64, GR128, GR64>;
747 defm : SXB<z_sdivrem64, GR128, DSGFR>;
749 // Division and remainder, from memory.
750 def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem64, GR128, sextloadi32>;
751 def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load>;
752 def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load>;
753 def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load>;
755 //===----------------------------------------------------------------------===//
757 //===----------------------------------------------------------------------===//
760 let neverHasSideEffects = 1 in {
761 def SLL : ShiftRS <"sll", 0x89, shl, GR32, shift12only>;
762 def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64, shift20only>;
765 // Logical shift right.
766 let neverHasSideEffects = 1 in {
767 def SRL : ShiftRS <"srl", 0x88, srl, GR32, shift12only>;
768 def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64, shift20only>;
771 // Arithmetic shift right.
773 def SRA : ShiftRS <"sra", 0x8A, sra, GR32, shift12only>;
774 def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64, shift20only>;
778 let neverHasSideEffects = 1 in {
779 def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32, shift20only>;
780 def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64, shift20only>;
783 // Rotate second operand left and inserted selected bits into first operand.
784 // These can act like 32-bit operands provided that the constant start and
785 // end bits (operands 2 and 3) are in the range [32, 64)
787 let isCodeGenOnly = 1 in
788 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
789 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
792 //===----------------------------------------------------------------------===//
794 //===----------------------------------------------------------------------===//
796 // Signed comparisons.
798 // Comparison with a register.
799 def CR : CompareRR <"cr", 0x19, z_cmp, GR32, GR32>;
800 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>;
801 def CGR : CompareRRE<"cgr", 0xB920, z_cmp, GR64, GR64>;
803 // Comparison with a signed 16-bit immediate.
804 def CHI : CompareRI<"chi", 0xA7E, z_cmp, GR32, imm32sx16>;
805 def CGHI : CompareRI<"cghi", 0xA7F, z_cmp, GR64, imm64sx16>;
807 // Comparison with a signed 32-bit immediate.
808 def CFI : CompareRIL<"cfi", 0xC2D, z_cmp, GR32, simm32>;
809 def CGFI : CompareRIL<"cgfi", 0xC2C, z_cmp, GR64, imm64sx32>;
811 // Comparison with memory.
812 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_cmp, GR32, sextloadi16>;
813 defm C : CompareRXPair<"c", 0x59, 0xE359, z_cmp, GR32, load>;
814 def CGH : CompareRXY<"cgh", 0xE334, z_cmp, GR64, sextloadi16>;
815 def CGF : CompareRXY<"cgf", 0xE330, z_cmp, GR64, sextloadi32>;
816 def CG : CompareRXY<"cg", 0xE320, z_cmp, GR64, load>;
817 def CHRL : CompareRILPC<"chrl", 0xC65, z_cmp, GR32, aligned_sextloadi16>;
818 def CRL : CompareRILPC<"crl", 0xC6D, z_cmp, GR32, aligned_load>;
819 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_cmp, GR64, aligned_sextloadi16>;
820 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_cmp, GR64, aligned_sextloadi32>;
821 def CGRL : CompareRILPC<"cgrl", 0xC68, z_cmp, GR64, aligned_load>;
823 // Comparison between memory and a signed 16-bit immediate.
824 def CHHSI : CompareSIL<"chhsi", 0xE554, z_cmp, sextloadi16, imm32sx16>;
825 def CHSI : CompareSIL<"chsi", 0xE55C, z_cmp, load, imm32sx16>;
826 def CGHSI : CompareSIL<"cghsi", 0xE558, z_cmp, load, imm64sx16>;
828 defm : SXB<z_cmp, GR64, CGFR>;
830 // Unsigned comparisons.
832 // Comparison with a register.
833 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>;
834 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>;
835 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>;
837 // Comparison with a signed 32-bit immediate.
838 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>;
839 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
841 // Comparison with memory.
842 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load>;
843 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, zextloadi32>;
844 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load>;
845 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32,
846 aligned_zextloadi16>;
847 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32,
849 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
850 aligned_zextloadi16>;
851 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
852 aligned_zextloadi32>;
853 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64,
856 // Comparison between memory and an unsigned 8-bit immediate.
857 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, zextloadi8, imm32zx8>;
859 // Comparison between memory and an unsigned 16-bit immediate.
860 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, zextloadi16, imm32zx16>;
861 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
862 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
864 defm : ZXB<z_ucmp, GR64, CLGFR>;
866 //===----------------------------------------------------------------------===//
868 //===----------------------------------------------------------------------===//
870 def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>;
871 def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>;
872 def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>;
874 def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
875 def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
876 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>;
877 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
878 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
879 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>;
880 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
881 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
883 def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
884 def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>;
885 def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>;
887 def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
888 def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
889 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>;
890 def ATOMIC_LOAD_NILL32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>;
891 def ATOMIC_LOAD_NILH32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>;
892 def ATOMIC_LOAD_NILF32 : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
893 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>;
894 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>;
895 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>;
896 def ATOMIC_LOAD_NIHL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>;
897 def ATOMIC_LOAD_NIHH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>;
898 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>;
899 def ATOMIC_LOAD_NIHF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>;
901 def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
902 def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
903 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>;
904 def ATOMIC_LOAD_OILL32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
905 def ATOMIC_LOAD_OILH32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
906 def ATOMIC_LOAD_OILF32 : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
907 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>;
908 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
909 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
910 def ATOMIC_LOAD_OIHL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
911 def ATOMIC_LOAD_OIHH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
912 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
913 def ATOMIC_LOAD_OIHF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
915 def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
916 def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
917 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>;
918 def ATOMIC_LOAD_XILF32 : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
919 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>;
920 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
921 def ATOMIC_LOAD_XIHF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
923 def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
924 def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
926 def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>;
927 def ATOMIC_LOAD_NILL32i : AtomicLoadBinaryImm32<atomic_load_nand_32,
929 def ATOMIC_LOAD_NILH32i : AtomicLoadBinaryImm32<atomic_load_nand_32,
931 def ATOMIC_LOAD_NILF32i : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
932 def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>;
933 def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm64<atomic_load_nand_64,
935 def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm64<atomic_load_nand_64,
937 def ATOMIC_LOAD_NIHLi : AtomicLoadBinaryImm64<atomic_load_nand_64,
939 def ATOMIC_LOAD_NIHHi : AtomicLoadBinaryImm64<atomic_load_nand_64,
941 def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm64<atomic_load_nand_64,
943 def ATOMIC_LOAD_NIHFi : AtomicLoadBinaryImm64<atomic_load_nand_64,
946 def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
947 def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>;
948 def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>;
950 def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
951 def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>;
952 def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>;
954 def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
955 def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
956 def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
958 def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
959 def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
960 def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
963 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
964 ADDR32:$bitshift, ADDR32:$negbitshift,
967 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
968 ADDR32:$bitshift, ADDR32:$negbitshift,
969 uimm32:$bitsize))]> {
973 let usesCustomInserter = 1;
977 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
978 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
981 //===----------------------------------------------------------------------===//
982 // Miscellaneous Instructions.
983 //===----------------------------------------------------------------------===//
985 // Read a 32-bit access register into a GR32. As with all GR32 operations,
986 // the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
987 // when a 64-bit address is stored in a pair of access registers.
988 def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
990 [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
992 // Find leftmost one, AKA count leading zeros. The instruction actually
993 // returns a pair of GR64s, the first giving the number of leading zeros
994 // and the second giving a copy of the source with the leftmost one bit
995 // cleared. We only use the first result here.
997 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>;
999 def : Pat<(ctlz GR64:$src),
1000 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_high)>;
1002 // Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
1003 def : Pat<(i64 (anyext GR32:$src)),
1004 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
1006 // There are no 32-bit equivalents of LLILL and LLILH, so use a full
1007 // 64-bit move followed by a subreg. This preserves the invariant that
1008 // all GR32 operations only modify the low 32 bits.
1009 def : Pat<(i32 imm32ll16:$src),
1010 (EXTRACT_SUBREG (LLILL (LL16 imm:$src)), subreg_32bit)>;
1011 def : Pat<(i32 imm32lh16:$src),
1012 (EXTRACT_SUBREG (LLILH (LH16 imm:$src)), subreg_32bit)>;
1014 // Extend GR32s and GR64s to GR128s.
1015 let usesCustomInserter = 1 in {
1016 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1017 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
1018 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1021 //===----------------------------------------------------------------------===//
1023 //===----------------------------------------------------------------------===//
1025 // Use AL* for GR64 additions of unsigned 32-bit values.
1026 defm : ZXB<add, GR64, ALGFR>;
1027 def : Pat<(add GR64:$src1, imm64zx32:$src2),
1028 (ALGFI GR64:$src1, imm64zx32:$src2)>;
1029 def : Pat<(add GR64:$src1, (zextloadi32 bdxaddr20only:$addr)),
1030 (ALGF GR64:$src1, bdxaddr20only:$addr)>;
1032 // Use SL* for GR64 subtractions of unsigned 32-bit values.
1033 defm : ZXB<sub, GR64, SLGFR>;
1034 def : Pat<(add GR64:$src1, imm64zx32n:$src2),
1035 (SLGFI GR64:$src1, imm64zx32n:$src2)>;
1036 def : Pat<(sub GR64:$src1, (zextloadi32 bdxaddr20only:$addr)),
1037 (SLGF GR64:$src1, bdxaddr20only:$addr)>;