lib/Target/SystemZ/SystemZInstrInfo.td

   1 //===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the SystemZ instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // SystemZ Instruction Predicate Definitions.
  16 def IsZ10 : Predicate<"Subtarget.isZ10()">;
  17
  18 include "SystemZInstrFormats.td"
  19
  20 //===----------------------------------------------------------------------===//
  21 // Type Constraints.
  22 //===----------------------------------------------------------------------===//
  23 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
  24 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
  25 class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>;
  26 class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
  27
  28 //===----------------------------------------------------------------------===//
  29 // Type Profiles.
  30 //===----------------------------------------------------------------------===//
  31 def SDT_SystemZCall         : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
  32 def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
  33 def SDT_SystemZCallSeqEnd   : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
  34 def SDT_CmpTest             : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
  35 def SDT_BrCond              : SDTypeProfile<0, 2,
  36                                            [SDTCisVT<0, OtherVT>,
  37                                             SDTCisI8<1>]>;
  38 def SDT_SelectCC            : SDTypeProfile<1, 3,
  39                                            [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  40                                             SDTCisI8<3>]>;
  41 def SDT_Address             : SDTypeProfile<1, 1,
  42                                             [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
  43
  44 //===----------------------------------------------------------------------===//
  45 // SystemZ Specific Node Definitions.
  46 //===----------------------------------------------------------------------===//
  47 def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
  48                      [SDNPHasChain, SDNPOptInFlag]>;
  49 def SystemZcall    : SDNode<"SystemZISD::CALL", SDT_SystemZCall,
  50                      [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
  51 def SystemZcallseq_start :
  52                  SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart,
  53                         [SDNPHasChain, SDNPOutFlag]>;
  54 def SystemZcallseq_end :
  55                  SDNode<"ISD::CALLSEQ_END",   SDT_SystemZCallSeqEnd,
  56                         [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
  57 def SystemZcmp     : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>;
  58 def SystemZucmp    : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>;
  59 def SystemZbrcond  : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
  60                             [SDNPHasChain, SDNPInFlag]>;
  61 def SystemZselect  : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>;
  62 def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
  63
  64
  65 include "SystemZOperands.td"
  66
  67 //===----------------------------------------------------------------------===//
  68 // Instruction list..
  69
  70 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
  71                               "#ADJCALLSTACKDOWN",
  72                               [(SystemZcallseq_start timm:$amt)]>;
  73 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
  74                               "#ADJCALLSTACKUP",
  75                               [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
  76
  77 let usesCustomDAGSchedInserter = 1 in {
  78   def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
  79                         "# Select32 PSEUDO",
  80                         [(set GR32:$dst,
  81                               (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>;
  82   def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
  83                         "# Select64 PSEUDO",
  84                         [(set GR64:$dst,
  85                               (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>;
  86 }
  87
  88
  89 //===----------------------------------------------------------------------===//
  90 //  Control Flow Instructions...
  91 //
  92
  93 // FIXME: Provide proper encoding!
  94 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
  95   def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
  96 }
  97
  98 let isBranch = 1, isTerminator = 1 in {
  99   let isBarrier = 1 in
 100     def JMP  : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
 101
 102   let isBarrier = 1, isIndirectBranch = 1 in {
 103     def JMPr   : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
 104     // FIXME: displacement here is 12 bits
 105     def JMPrri : Pseudo<(outs), (ins rriaddr:$dst), "b\t{$dst}", [(brind rriaddr:$dst)]>;
 106   }
 107
 108   let Uses = [PSW] in {
 109     def JE  : Pseudo<(outs), (ins brtarget:$dst),
 110                      "je\t$dst",
 111                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>;
 112     def JNE : Pseudo<(outs), (ins brtarget:$dst),
 113                      "jne\t$dst",
 114                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>;
 115     def JH  : Pseudo<(outs), (ins brtarget:$dst),
 116                      "jh\t$dst",
 117                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>;
 118     def JL  : Pseudo<(outs), (ins brtarget:$dst),
 119                      "jl\t$dst",
 120                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>;
 121     def JHE : Pseudo<(outs), (ins brtarget:$dst),
 122                      "jhe\t$dst",
 123                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>;
 124     def JLE : Pseudo<(outs), (ins brtarget:$dst),
 125                      "jle\t$dst",
 126                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>;
 127
 128   } // Uses = [PSW]
 129 } // isBranch = 1
 130
 131 //===----------------------------------------------------------------------===//
 132 //  Call Instructions...
 133 //
 134
 135 let isCall = 1 in
 136   // All calls clobber the non-callee saved registers (except R14 which we
 137   // handle separately). Uses for argument registers are added manually.
 138   let Defs = [R0D, R1D, R2D, R3D, R4D, R5D] in {
 139     def CALLi     : Pseudo<(outs), (ins i64imm:$dst, variable_ops),
 140                            "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
 141     def CALLr     : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
 142                            "brasl\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>;
 143   }
 144
 145 //===----------------------------------------------------------------------===//
 146 //  Miscellaneous Instructions.
 147 //
 148
 149 let isReMaterializable = 1 in
 150 // FIXME: Provide imm12 variant
 151 // FIXME: Address should be halfword aligned...
 152 def LA64r  : Pseudo<(outs GR64:$dst), (ins laaddr:$src),
 153                     "lay\t{$dst, $src}",
 154                     [(set GR64:$dst, laaddr:$src)]>;
 155 def LA64rm : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 156                     "larl\t{$dst, $src}",
 157                     [(set GR64:$dst,
 158                           (SystemZpcrelwrapper tglobaladdr:$src))]>;
 159
 160 let neverHasSideEffects = 1 in
 161 def NOP : Pseudo<(outs), (ins), "# no-op", []>;
 162
 163 //===----------------------------------------------------------------------===//
 164 // Move Instructions
 165
 166 // FIXME: Provide proper encoding!
 167 let neverHasSideEffects = 1 in {
 168 def MOV32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 169                      "lr\t{$dst, $src}",
 170                      []>;
 171 def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 172                      "lgr\t{$dst, $src}",
 173                      []>;
 174 def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
 175                      "# MOV128 PSEUDO!\n"
 176                      "\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 177                      "\tlgr\t${dst:subreg_even}, ${src:subreg_even}",
 178                      []>;
 179 def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
 180                      "# MOV64P PSEUDO!\n"
 181                      "\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 182                      "\tlr\t${dst:subreg_even}, ${src:subreg_even}",
 183                      []>;
 184 }
 185
 186 def MOVSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 187                          "lgfr\t{$dst, $src}",
 188                          [(set GR64:$dst, (sext GR32:$src))]>;
 189 def MOVZX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 190                          "llgfr\t{$dst, $src}",
 191                          [(set GR64:$dst, (zext GR32:$src))]>;
 192
 193 // FIXME: Provide proper encoding!
 194 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 195 def MOV32ri16 : Pseudo<(outs GR32:$dst), (ins s16imm:$src),
 196                        "lhi\t{$dst, $src}",
 197                        [(set GR32:$dst, immSExt16:$src)]>;
 198 def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins s16imm64:$src),
 199                        "lghi\t{$dst, $src}",
 200                        [(set GR64:$dst, immSExt16:$src)]>;
 201
 202 def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 203                          "llill\t{$dst, $src}",
 204                          [(set GR64:$dst, i64ll16:$src)]>;
 205 def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 206                          "llilh\t{$dst, $src}",
 207                          [(set GR64:$dst, i64lh16:$src)]>;
 208 def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 209                          "llihl\t{$dst, $src}",
 210                          [(set GR64:$dst, i64hl16:$src)]>;
 211 def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 212                          "llihh\t{$dst, $src}",
 213                          [(set GR64:$dst, i64hh16:$src)]>;
 214
 215 def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins s32imm64:$src),
 216                        "lgfi\t{$dst, $src}",
 217                        [(set GR64:$dst, immSExt32:$src)]>;
 218 def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 219                          "llilf\t{$dst, $src}",
 220                          [(set GR64:$dst, i64lo32:$src)]>;
 221 def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 222                          "llihf\t{$dst, $src}",
 223                          [(set GR64:$dst, i64hi32:$src)]>;
 224 }
 225
 226 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
 227 def MOV32rm : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 228                      "ly\t{$dst, $src}",
 229                      [(set GR32:$dst, (load rriaddr:$src))]>;
 230 def MOV64rm : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 231                      "lg\t{$dst, $src}",
 232                      [(set GR64:$dst, (load rriaddr:$src))]>;
 233
 234 }
 235
 236 def MOV32mr : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 237                      "sty\t{$src, $dst}",
 238                      [(store GR32:$src, rriaddr:$dst)]>;
 239 def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 240                      "stg\t{$src, $dst}",
 241                      [(store GR64:$src, rriaddr:$dst)]>;
 242
 243 // FIXME: displacements here are really 12 bit, not 20!
 244 def MOV8mi    : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src),
 245                        "mviy\t{$dst, $src}",
 246                        [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
 247
 248 def MOV16mi   : Pseudo<(outs), (ins riaddr:$dst, s16imm:$src),
 249                        "mvhhi\t{$dst, $src}",
 250                        [(truncstorei16 (i32 i32immSExt16:$src), riaddr:$dst)]>,
 251                        Requires<[IsZ10]>;
 252 def MOV32mi16 : Pseudo<(outs), (ins riaddr:$dst, s32imm:$src),
 253                        "mvhi\t{$dst, $src}",
 254                        [(store (i32 immSExt16:$src), riaddr:$dst)]>,
 255                        Requires<[IsZ10]>;
 256 def MOV64mi16 : Pseudo<(outs), (ins riaddr:$dst, s32imm64:$src),
 257                        "mvghi\t{$dst, $src}",
 258                        [(store (i64 immSExt16:$src), riaddr:$dst)]>,
 259                        Requires<[IsZ10]>;
 260
 261 // sexts
 262 def MOVSX32rr8  : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 263                          "lbr\t{$dst, $src}",
 264                          [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>;
 265 def MOVSX64rr8  : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 266                          "lgbr\t{$dst, $src}",
 267                          [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>;
 268 def MOVSX32rr16 : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 269                          "lhr\t{$dst, $src}",
 270                          [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>;
 271 def MOVSX64rr16 : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 272                          "lghr\t{$dst, $src}",
 273                          [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>;
 274
 275 // extloads
 276 def MOVSX32rm8  : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 277                          "lb\t{$dst, $src}",
 278                          [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
 279 def MOVSX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 280                          "lhy\t{$dst, $src}",
 281                          [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
 282 def MOVSX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 283                          "lgb\t{$dst, $src}",
 284                          [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
 285 def MOVSX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 286                          "lgh\t{$dst, $src}",
 287                          [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
 288 def MOVSX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 289                          "lgf\t{$dst, $src}",
 290                          [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
 291
 292 def MOVZX32rm8  : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 293                          "llc\t{$dst, $src}",
 294                          [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
 295 def MOVZX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 296                          "llh\t{$dst, $src}",
 297                          [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
 298 def MOVZX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 299                          "llgc\t{$dst, $src}",
 300                          [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
 301 def MOVZX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 302                          "llgh\t{$dst, $src}",
 303                          [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
 304 def MOVZX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 305                          "llgf\t{$dst, $src}",
 306                          [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
 307
 308 // truncstores
 309 // FIXME: Implement 12-bit displacement stuff someday
 310 def MOV32m8r  : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 311                        "stcy\t{$src, $dst}",
 312                        [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
 313
 314 def MOV32m16r : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 315                        "sthy\t{$src, $dst}",
 316                        [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
 317
 318 def MOV64m8r  : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 319                        "stcy\t{$src, $dst}",
 320                        [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
 321
 322 def MOV64m16r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 323                        "sthy\t{$src, $dst}",
 324                        [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
 325
 326 def MOV64m32r : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 327                        "sty\t{$src, $dst}",
 328                        [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
 329
 330 // multiple regs moves
 331 // FIXME: should we use multiple arg nodes?
 332 def MOV32mrm  : Pseudo<(outs), (ins riaddr:$dst, GR32:$from, GR32:$to),
 333                        "stmy\t{$from, $to, $dst}",
 334                        []>;
 335 def MOV64mrm  : Pseudo<(outs), (ins riaddr:$dst, GR64:$from, GR64:$to),
 336                        "stmg\t{$from, $to, $dst}",
 337                        []>;
 338 def MOV32rmm  : Pseudo<(outs GR32:$from, GR32:$to), (ins riaddr:$dst),
 339                        "lmy\t{$from, $to, $dst}",
 340                        []>;
 341 def MOV64rmm  : Pseudo<(outs GR64:$from, GR64:$to), (ins riaddr:$dst),
 342                        "lmg\t{$from, $to, $dst}",
 343                        []>;
 344
 345
 346 //===----------------------------------------------------------------------===//
 347 // Arithmetic Instructions
 348
 349 let Defs = [PSW] in {
 350 def NEG32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 351                      "lcr\t{$dst, $src}",
 352                      [(set GR32:$dst, (ineg GR32:$src)),
 353                       (implicit PSW)]>;
 354 def NEG64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 355                      "lcgr\t{$dst, $src}",
 356                      [(set GR64:$dst, (ineg GR64:$src)),
 357                       (implicit PSW)]>;
 358 def NEG64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 359                        "lcgfr\t{$dst, $src}",
 360                        [(set GR64:$dst, (ineg (sext GR32:$src))),
 361                         (implicit PSW)]>;
 362 }
 363
 364 let isTwoAddress = 1 in {
 365
 366 let Defs = [PSW] in {
 367
 368 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
 369 // FIXME: Provide proper encoding!
 370 def ADD32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 371                      "ar\t{$dst, $src2}",
 372                      [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 373                       (implicit PSW)]>;
 374 def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 375                      "agr\t{$dst, $src2}",
 376                      [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
 377                       (implicit PSW)]>;
 378 }
 379
 380 // FIXME: Provide proper encoding!
 381 def ADD32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 382                        "ahi\t{$dst, $src2}",
 383                        [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
 384                         (implicit PSW)]>;
 385 def ADD32ri   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 386                        "afi\t{$dst, $src2}",
 387                        [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
 388                         (implicit PSW)]>;
 389 def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 390                        "aghi\t{$dst, $src2}",
 391                        [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
 392                         (implicit PSW)]>;
 393 def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 394                        "agfi\t{$dst, $src2}",
 395                        [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
 396                         (implicit PSW)]>;
 397
 398 let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
 399 // FIXME: Provide proper encoding!
 400 def AND32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 401                      "nr\t{$dst, $src2}",
 402                      [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
 403 def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 404                      "ngr\t{$dst, $src2}",
 405                      [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
 406 }
 407
 408 // FIXME: Provide proper encoding!
 409 // FIXME: Compute masked bits properly!
 410 def AND32rill16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 411                          "nill\t{$dst, $src2}",
 412                         [(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>;
 413 def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 414                          "nill\t{$dst, $src2}",
 415                          [(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>;
 416
 417 def AND32rilh16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 418                          "nilh\t{$dst, $src2}",
 419                          [(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>;
 420 def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 421                          "nilh\t{$dst, $src2}",
 422                          [(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>;
 423
 424 def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 425                          "nihl\t{$dst, $src2}",
 426                          [(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>;
 427 def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 428                          "nihh\t{$dst, $src2}",
 429                          [(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>;
 430
 431 def AND32ri     : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 432                          "nilf\t{$dst, $src2}",
 433                          [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
 434 def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 435                          "nilf\t{$dst, $src2}",
 436                          [(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>;
 437 def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 438                          "nihf\t{$dst, $src2}",
 439                          [(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>;
 440
 441 let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
 442 // FIXME: Provide proper encoding!
 443 def OR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 444                     "or\t{$dst, $src2}",
 445                     [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
 446 def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 447                     "ogr\t{$dst, $src2}",
 448                     [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
 449 }
 450
 451 def OR32ri16  : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 452                       "oill\t{$dst, $src2}",
 453                       [(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>;
 454 def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 455                       "oilh\t{$dst, $src2}",
 456                       [(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>;
 457 def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 458                     "oilf\t{$dst, $src2}",
 459                     [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
 460
 461 def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 462                         "oill\t{$dst, $src2}",
 463                         [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
 464 def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 465                         "oilh\t{$dst, $src2}",
 466                         [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
 467 def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 468                         "oihl\t{$dst, $src2}",
 469                         [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
 470 def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 471                         "oihh\t{$dst, $src2}",
 472                         [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
 473
 474 def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 475                         "oilf\t{$dst, $src2}",
 476                         [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
 477 def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 478                         "oihf\t{$dst, $src2}",
 479                         [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
 480
 481 // FIXME: Provide proper encoding!
 482 def SUB32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 483                      "sr\t{$dst, $src2}",
 484                      [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
 485 def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 486                      "sgr\t{$dst, $src2}",
 487                      [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
 488
 489
 490 let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
 491 // FIXME: Provide proper encoding!
 492 def XOR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 493                      "xr\t{$dst, $src2}",
 494                      [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
 495 def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 496                      "xgr\t{$dst, $src2}",
 497                      [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
 498 }
 499
 500 def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 501                      "xilf\t{$dst, $src2}",
 502                      [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
 503
 504 } // Defs = [PSW]
 505
 506 let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
 507 def MUL32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 508                      "msr\t{$dst, $src2}",
 509                      [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
 510 def MUL64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 511                      "msgr\t{$dst, $src2}",
 512                      [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
 513
 514 def MUL64rrP   : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 515                         "mr\t{$dst, $src2}",
 516                         []>;
 517 def UMUL64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 518                          "mlr\t{$dst, $src2}",
 519                          []>;
 520 def UMUL128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 521                         "mlgr\t{$dst, $src2}",
 522                         []>;
 523 }
 524
 525
 526 def MUL32ri16   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 527                          "mhi\t{$dst, $src2}",
 528                          [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
 529 def MUL64ri16   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 530                          "mghi\t{$dst, $src2}",
 531                          [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
 532
 533 def MUL32ri     : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 534                          "msfi\t{$dst, $src2}",
 535                          [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>,
 536                          Requires<[IsZ10]>;
 537 def MUL64ri32   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 538                          "msgfi\t{$dst, $src2}",
 539                          [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
 540                          Requires<[IsZ10]>;
 541
 542 def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 543                      "msy\t{$dst, $src2}",
 544                      [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
 545 def MUL64rm : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 546                      "msg\t{$dst, $src2}",
 547                      [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
 548
 549 def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
 550                          "msgfr\t{$dst, $src2}",
 551                          [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
 552
 553 def SDIVREM64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 554                            "dr\t{$dst, $src2}",
 555                            []>;
 556
 557 def SDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 558                            "dsgr\t{$dst, $src2}",
 559                            []>;
 560
 561 def UDIVREM64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 562                            "dlr\t{$dst, $src2}",
 563                            []>;
 564
 565 def UDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 566                            "dlgr\t{$dst, $src2}",
 567                            []>;
 568
 569 } // isTwoAddress = 1
 570
 571 //===----------------------------------------------------------------------===//
 572 // Shifts
 573
 574 let isTwoAddress = 1 in
 575 def SRL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 576                       "srl\t{$src, $amt}",
 577                       [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
 578 def SRL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 579                       "srlg\t{$dst, $src, $amt}",
 580                       [(set GR64:$dst, (srl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 581 def SRLA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 582                       "srlg\t{$dst, $src, $amt}",
 583                       [(set GR64:$dst, (srl GR64:$src, (i32 imm:$amt)))]>;
 584
 585 let isTwoAddress = 1 in
 586 def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 587                       "sll\t{$src, $amt}",
 588                       [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
 589 def SHL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 590                       "sllg\t{$dst, $src, $amt}",
 591                       [(set GR64:$dst, (shl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 592 def SHL64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 593                       "sllg\t{$dst, $src, $amt}",
 594                       [(set GR64:$dst, (shl GR64:$src, (i32 imm:$amt)))]>;
 595
 596 let Defs = [PSW] in {
 597 let isTwoAddress = 1 in
 598 def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 599                       "sra\t{$src, $amt}",
 600                       [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
 601                        (implicit PSW)]>;
 602 def SRA64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 603                       "srag\t{$dst, $src, $amt}",
 604                       [(set GR64:$dst, (sra GR64:$src, (i32 (trunc riaddr:$amt)))),
 605                        (implicit PSW)]>;
 606 def SRA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 607                       "srag\t{$dst, $src, $amt}",
 608                       [(set GR64:$dst, (sra GR64:$src, (i32 imm:$amt))),
 609                        (implicit PSW)]>;
 610 } // Defs = [PSW]
 611
 612 let isTwoAddress = 1 in
 613 def ROTL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 614                        "rll\t{$src, $amt}",
 615                        [(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>;
 616 def ROTL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 617                        "rllg\t{$dst, $src, $amt}",
 618                        [(set GR64:$dst, (rotl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 619 def ROTL64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 620                        "rllg\t{$dst, $src, $amt}",
 621                        [(set GR64:$dst, (rotl GR64:$src, (i32 imm:$amt)))]>;
 622
 623 //===----------------------------------------------------------------------===//
 624 // Test instructions (like AND but do not produce any result
 625
 626 // Integer comparisons
 627 let Defs = [PSW] in {
 628 def CMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 629                      "cr\t$src1, $src2",
 630                      [(SystemZcmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 631 def CMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 632                      "cgr\t$src1, $src2",
 633                      [(SystemZcmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 634
 635 def CMP32ri   : Pseudo<(outs), (ins GR32:$src1, s32imm:$src2),
 636                        "cfi\t$src1, $src2",
 637                        [(SystemZcmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 638 def CMP64ri32 : Pseudo<(outs), (ins GR64:$src1, s32imm64:$src2),
 639                        "cgfi\t$src1, $src2",
 640                        [(SystemZcmp GR64:$src1, i64immSExt32:$src2),
 641                         (implicit PSW)]>;
 642
 643 def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 644                      "cy\t$src1, $src2",
 645                      [(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
 646                       (implicit PSW)]>;
 647 def CMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 648                      "cg\t$src1, $src2",
 649                      [(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
 650                       (implicit PSW)]>;
 651
 652 def UCMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 653                       "clr\t$src1, $src2",
 654                       [(SystemZucmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 655 def UCMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 656                       "clgr\t$src1, $src2",
 657                       [(SystemZucmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 658
 659 def UCMP32ri   : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2),
 660                         "clfi\t$src1, $src2",
 661                         [(SystemZucmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 662 def UCMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2),
 663                         "clgfi\t$src1, $src2",
 664                         [(SystemZucmp GR64:$src1, i64immZExt32:$src2),
 665                          (implicit PSW)]>;
 666
 667 def UCMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 668                       "cly\t$src1, $src2",
 669                       [(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
 670                        (implicit PSW)]>;
 671 def UCMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 672                       "clg\t$src1, $src2",
 673                       [(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
 674                        (implicit PSW)]>;
 675
 676 def CMPSX64rr32  : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 677                           "cgfr\t$src1, $src2",
 678                           [(SystemZucmp GR64:$src1, (sext GR32:$src2)),
 679                            (implicit PSW)]>;
 680 def UCMPZX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 681                           "clgfr\t$src1, $src2",
 682                           [(SystemZucmp GR64:$src1, (zext GR32:$src2)),
 683                            (implicit PSW)]>;
 684
 685 def CMPSX64rm32   : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 686                            "cgf\t$src1, $src2",
 687                            [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
 688                             (implicit PSW)]>;
 689 def UCMPZX64rm32  : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 690                            "clgf\t$src1, $src2",
 691                            [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
 692                             (implicit PSW)]>;
 693
 694 // FIXME: Add other crazy ucmp forms
 695
 696 } // Defs = [PSW]
 697
 698 //===----------------------------------------------------------------------===//
 699 // Non-Instruction Patterns.
 700 //===----------------------------------------------------------------------===//
 701
 702 // anyext
 703 def : Pat<(i64 (anyext GR32:$src)),
 704           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
 705
 706 //===----------------------------------------------------------------------===//
 707 // Peepholes.
 708 //===----------------------------------------------------------------------===//
 709
 710 // FIXME: use add/sub tricks with 32678/-32768
 711
 712 // Arbitrary immediate support.  Implement in terms of LLIHF/OILF.
 713 def : Pat<(i64 imm:$imm),
 714           (OR64rilo32 (MOV64rihi32 (HI32 imm:$imm)), (LO32 imm:$imm))>;
 715
 716 // trunc patterns
 717 def : Pat<(i32 (trunc GR64:$src)),
 718           (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
 719
 720 // sext_inreg patterns
 721 def : Pat<(sext_inreg GR64:$src, i32),
 722           (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
 723
 724 // extload patterns
 725 def : Pat<(extloadi32i8  rriaddr:$src), (MOVZX32rm8  rriaddr:$src)>;
 726 def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>;
 727 def : Pat<(extloadi64i8  rriaddr:$src), (MOVZX64rm8  rriaddr:$src)>;
 728 def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
 729 def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
 730
 731 // calls
 732 def : Pat<(SystemZcall (i64 tglobaladdr:$dst)),
 733           (CALLi tglobaladdr:$dst)>;
 734 def : Pat<(SystemZcall (i64 texternalsym:$dst)),
 735           (CALLi texternalsym:$dst)>;
 736
 737 // muls
 738 def : Pat<(mulhs GR32:$src1, GR32:$src2),
 739           (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 740                                                    GR32:$src1, subreg_odd),
 741                                     GR32:$src2),
 742                           subreg_even)>;
 743
 744 def : Pat<(mulhu GR32:$src1, GR32:$src2),
 745           (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 746                                                     GR32:$src1, subreg_odd),
 747                                      GR32:$src2),
 748                           subreg_even)>;
 749 def : Pat<(mulhu GR64:$src1, GR64:$src2),
 750           (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 751                                                      GR64:$src1, subreg_odd),
 752                                       GR64:$src2),
 753                           subreg_even)>;
 754
 755 // divs
 756 // FIXME: Add memory versions
 757 def : Pat<(sdiv GR32:$src1, GR32:$src2),
 758           (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 759                                                        GR32:$src1, subreg_odd),
 760                                          GR32:$src2),
 761                           subreg_odd)>;
 762 def : Pat<(sdiv GR64:$src1, GR64:$src2),
 763           (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 764                                                         GR64:$src1, subreg_odd),
 765                                          GR64:$src2),
 766                           subreg_odd)>;
 767 def : Pat<(udiv GR32:$src1, GR32:$src2),
 768           (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 769                                                        GR32:$src1, subreg_odd),
 770                                          GR32:$src2),
 771                           subreg_odd)>;
 772 def : Pat<(udiv GR64:$src1, GR64:$src2),
 773           (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 774                                                         GR64:$src1, subreg_odd),
 775                                          GR64:$src2),
 776                           subreg_odd)>;
 777
 778 // rems
 779 // FIXME: Add memory versions
 780 def : Pat<(srem GR32:$src1, GR32:$src2),
 781           (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 782                                                        GR32:$src1, subreg_odd),
 783                                          GR32:$src2),
 784                           subreg_even)>;
 785 def : Pat<(srem GR64:$src1, GR64:$src2),
 786           (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 787                                                         GR64:$src1, subreg_odd),
 788                                          GR64:$src2),
 789                           subreg_even)>;
 790 def : Pat<(urem GR32:$src1, GR32:$src2),
 791           (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 792                                                        GR32:$src1, subreg_odd),
 793                                          GR32:$src2),
 794                           subreg_even)>;
 795 def : Pat<(urem GR64:$src1, GR64:$src2),
 796           (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 797                                                         GR64:$src1, subreg_odd),
 798                                          GR64:$src2),
 799                           subreg_even)>;
 800
 801 def : Pat<(i32 imm:$src),
 802           (EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;