lib/Target/SystemZ/SystemZInstrInfo.td

   1 //===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the SystemZ instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // SystemZ Instruction Predicate Definitions.
  16 def IsZ10 : Predicate<"Subtarget.isZ10()">;
  17
  18 include "SystemZInstrFormats.td"
  19
  20 //===----------------------------------------------------------------------===//
  21 // Type Constraints.
  22 //===----------------------------------------------------------------------===//
  23 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
  24 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
  25 class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>;
  26 class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
  27
  28 //===----------------------------------------------------------------------===//
  29 // Type Profiles.
  30 //===----------------------------------------------------------------------===//
  31 def SDT_SystemZCall         : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
  32 def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
  33 def SDT_SystemZCallSeqEnd   : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
  34 def SDT_CmpTest             : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
  35 def SDT_BrCond              : SDTypeProfile<0, 2,
  36                                            [SDTCisVT<0, OtherVT>,
  37                                             SDTCisI8<1>]>;
  38 def SDT_SelectCC            : SDTypeProfile<1, 3,
  39                                            [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  40                                             SDTCisI8<3>]>;
  41 def SDT_Address             : SDTypeProfile<1, 1,
  42                                             [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
  43
  44 //===----------------------------------------------------------------------===//
  45 // SystemZ Specific Node Definitions.
  46 //===----------------------------------------------------------------------===//
  47 def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
  48                      [SDNPHasChain, SDNPOptInFlag]>;
  49 def SystemZcall    : SDNode<"SystemZISD::CALL", SDT_SystemZCall,
  50                      [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
  51 def SystemZcallseq_start :
  52                  SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart,
  53                         [SDNPHasChain, SDNPOutFlag]>;
  54 def SystemZcallseq_end :
  55                  SDNode<"ISD::CALLSEQ_END",   SDT_SystemZCallSeqEnd,
  56                         [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
  57 def SystemZcmp     : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>;
  58 def SystemZucmp    : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>;
  59 def SystemZbrcond  : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
  60                             [SDNPHasChain, SDNPInFlag]>;
  61 def SystemZselect  : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>;
  62 def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
  63
  64
  65 include "SystemZOperands.td"
  66
  67 //===----------------------------------------------------------------------===//
  68 // Instruction list..
  69
  70 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
  71                               "#ADJCALLSTACKDOWN",
  72                               [(SystemZcallseq_start timm:$amt)]>;
  73 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
  74                               "#ADJCALLSTACKUP",
  75                               [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
  76
  77 let usesCustomDAGSchedInserter = 1 in {
  78   def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
  79                         "# Select32 PSEUDO",
  80                         [(set GR32:$dst,
  81                               (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>;
  82   def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
  83                         "# Select64 PSEUDO",
  84                         [(set GR64:$dst,
  85                               (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>;
  86 }
  87
  88
  89 //===----------------------------------------------------------------------===//
  90 //  Control Flow Instructions...
  91 //
  92
  93 // FIXME: Provide proper encoding!
  94 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
  95   def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
  96 }
  97
  98 let isBranch = 1, isTerminator = 1 in {
  99   let isBarrier = 1 in {
 100     def JMP  : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
 101
 102     let isIndirectBranch = 1 in
 103       def JMPr   : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
 104   }
 105
 106   let Uses = [PSW] in {
 107     def JE  : Pseudo<(outs), (ins brtarget:$dst),
 108                      "je\t$dst",
 109                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>;
 110     def JNE : Pseudo<(outs), (ins brtarget:$dst),
 111                      "jne\t$dst",
 112                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>;
 113     def JH  : Pseudo<(outs), (ins brtarget:$dst),
 114                      "jh\t$dst",
 115                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>;
 116     def JL  : Pseudo<(outs), (ins brtarget:$dst),
 117                      "jl\t$dst",
 118                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>;
 119     def JHE : Pseudo<(outs), (ins brtarget:$dst),
 120                      "jhe\t$dst",
 121                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>;
 122     def JLE : Pseudo<(outs), (ins brtarget:$dst),
 123                      "jle\t$dst",
 124                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>;
 125
 126   } // Uses = [PSW]
 127 } // isBranch = 1
 128
 129 //===----------------------------------------------------------------------===//
 130 //  Call Instructions...
 131 //
 132
 133 let isCall = 1 in
 134   // All calls clobber the non-callee saved registers. Uses for argument
 135   // registers are added manually.
 136   let Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D] in {
 137     def CALLi     : Pseudo<(outs), (ins i64imm:$dst, variable_ops),
 138                            "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
 139     def CALLr     : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
 140                            "basr\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>;
 141   }
 142
 143 //===----------------------------------------------------------------------===//
 144 //  Miscellaneous Instructions.
 145 //
 146
 147 let isReMaterializable = 1 in
 148 // FIXME: Provide imm12 variant
 149 // FIXME: Address should be halfword aligned...
 150 def LA64r  : Pseudo<(outs GR64:$dst), (ins laaddr:$src),
 151                     "lay\t{$dst, $src}",
 152                     [(set GR64:$dst, laaddr:$src)]>;
 153 def LA64rm : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 154                     "larl\t{$dst, $src}",
 155                     [(set GR64:$dst,
 156                           (SystemZpcrelwrapper tglobaladdr:$src))]>;
 157
 158 let neverHasSideEffects = 1 in
 159 def NOP : Pseudo<(outs), (ins), "# no-op", []>;
 160
 161 //===----------------------------------------------------------------------===//
 162 // Move Instructions
 163
 164 // FIXME: Provide proper encoding!
 165 let neverHasSideEffects = 1 in {
 166 def MOV32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 167                      "lr\t{$dst, $src}",
 168                      []>;
 169 def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 170                      "lgr\t{$dst, $src}",
 171                      []>;
 172 def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
 173                      "# MOV128 PSEUDO!\n"
 174                      "\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 175                      "\tlgr\t${dst:subreg_even}, ${src:subreg_even}",
 176                      []>;
 177 def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
 178                      "# MOV64P PSEUDO!\n"
 179                      "\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 180                      "\tlr\t${dst:subreg_even}, ${src:subreg_even}",
 181                      []>;
 182 }
 183
 184 def MOVSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 185                          "lgfr\t{$dst, $src}",
 186                          [(set GR64:$dst, (sext GR32:$src))]>;
 187 def MOVZX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 188                          "llgfr\t{$dst, $src}",
 189                          [(set GR64:$dst, (zext GR32:$src))]>;
 190
 191 // FIXME: Provide proper encoding!
 192 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 193 def MOV32ri16 : Pseudo<(outs GR32:$dst), (ins s16imm:$src),
 194                        "lhi\t{$dst, $src}",
 195                        [(set GR32:$dst, immSExt16:$src)]>;
 196 def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins s16imm64:$src),
 197                        "lghi\t{$dst, $src}",
 198                        [(set GR64:$dst, immSExt16:$src)]>;
 199
 200 def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 201                          "llill\t{$dst, $src}",
 202                          [(set GR64:$dst, i64ll16:$src)]>;
 203 def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 204                          "llilh\t{$dst, $src}",
 205                          [(set GR64:$dst, i64lh16:$src)]>;
 206 def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 207                          "llihl\t{$dst, $src}",
 208                          [(set GR64:$dst, i64hl16:$src)]>;
 209 def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 210                          "llihh\t{$dst, $src}",
 211                          [(set GR64:$dst, i64hh16:$src)]>;
 212
 213 def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins s32imm64:$src),
 214                        "lgfi\t{$dst, $src}",
 215                        [(set GR64:$dst, immSExt32:$src)]>;
 216 def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 217                          "llilf\t{$dst, $src}",
 218                          [(set GR64:$dst, i64lo32:$src)]>;
 219 def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 220                          "llihf\t{$dst, $src}",
 221                          [(set GR64:$dst, i64hi32:$src)]>;
 222 }
 223
 224 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
 225 def MOV32rm  : Pseudo<(outs GR32:$dst), (ins rriaddr12:$src),
 226                       "l\t{$dst, $src}",
 227                       [(set GR32:$dst, (load rriaddr12:$src))]>;
 228 def MOV32rmy : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 229                       "ly\t{$dst, $src}",
 230                       [(set GR32:$dst, (load rriaddr:$src))]>;
 231 def MOV64rm  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 232                       "lg\t{$dst, $src}",
 233                       [(set GR64:$dst, (load rriaddr:$src))]>;
 234
 235 }
 236
 237 def MOV32mr  : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src),
 238                       "st\t{$src, $dst}",
 239                       [(store GR32:$src, rriaddr12:$dst)]>;
 240 def MOV32mry : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 241                       "sty\t{$src, $dst}",
 242                       [(store GR32:$src, rriaddr:$dst)]>;
 243 def MOV64mr  : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 244                       "stg\t{$src, $dst}",
 245                       [(store GR64:$src, rriaddr:$dst)]>;
 246
 247 def MOV8mi    : Pseudo<(outs), (ins riaddr12:$dst, i32i8imm:$src),
 248                        "mvi\t{$dst, $src}",
 249                        [(truncstorei8 (i32 i32immSExt8:$src), riaddr12:$dst)]>;
 250 def MOV8miy   : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src),
 251                        "mviy\t{$dst, $src}",
 252                        [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
 253
 254 def MOV16mi   : Pseudo<(outs), (ins riaddr12:$dst, s16imm:$src),
 255                        "mvhhi\t{$dst, $src}",
 256                        [(truncstorei16 (i32 i32immSExt16:$src), riaddr12:$dst)]>,
 257                        Requires<[IsZ10]>;
 258 def MOV32mi16 : Pseudo<(outs), (ins riaddr12:$dst, s32imm:$src),
 259                        "mvhi\t{$dst, $src}",
 260                        [(store (i32 immSExt16:$src), riaddr12:$dst)]>,
 261                        Requires<[IsZ10]>;
 262 def MOV64mi16 : Pseudo<(outs), (ins riaddr12:$dst, s32imm64:$src),
 263                        "mvghi\t{$dst, $src}",
 264                        [(store (i64 immSExt16:$src), riaddr12:$dst)]>,
 265                        Requires<[IsZ10]>;
 266
 267 // sexts
 268 def MOVSX32rr8  : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 269                          "lbr\t{$dst, $src}",
 270                          [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>;
 271 def MOVSX64rr8  : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 272                          "lgbr\t{$dst, $src}",
 273                          [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>;
 274 def MOVSX32rr16 : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 275                          "lhr\t{$dst, $src}",
 276                          [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>;
 277 def MOVSX64rr16 : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 278                          "lghr\t{$dst, $src}",
 279                          [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>;
 280
 281 // extloads
 282 def MOVSX32rm8   : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 283                           "lb\t{$dst, $src}",
 284                           [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
 285 def MOVSX32rm16  : Pseudo<(outs GR32:$dst), (ins rriaddr12:$src),
 286                           "lh\t{$dst, $src}",
 287                           [(set GR32:$dst, (sextloadi32i16 rriaddr12:$src))]>;
 288 def MOVSX32rm16y : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 289                          "lhy\t{$dst, $src}",
 290                          [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
 291 def MOVSX64rm8   : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 292                           "lgb\t{$dst, $src}",
 293                           [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
 294 def MOVSX64rm16  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 295                           "lgh\t{$dst, $src}",
 296                           [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
 297 def MOVSX64rm32  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 298                           "lgf\t{$dst, $src}",
 299                           [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
 300
 301 def MOVZX32rm8  : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 302                          "llc\t{$dst, $src}",
 303                          [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
 304 def MOVZX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 305                          "llh\t{$dst, $src}",
 306                          [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
 307 def MOVZX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 308                          "llgc\t{$dst, $src}",
 309                          [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
 310 def MOVZX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 311                          "llgh\t{$dst, $src}",
 312                          [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
 313 def MOVZX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 314                          "llgf\t{$dst, $src}",
 315                          [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
 316
 317 // truncstores
 318 def MOV32m8r   : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src),
 319                         "stc\t{$src, $dst}",
 320                         [(truncstorei8 GR32:$src, rriaddr12:$dst)]>;
 321
 322 def MOV32m8ry  : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 323                         "stcy\t{$src, $dst}",
 324                         [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
 325
 326 def MOV32m16r  : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src),
 327                         "sth\t{$src, $dst}",
 328                         [(truncstorei16 GR32:$src, rriaddr12:$dst)]>;
 329
 330 def MOV32m16ry : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 331                         "sthy\t{$src, $dst}",
 332                         [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
 333
 334 def MOV64m8r   : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src),
 335                         "stc\t{$src, $dst}",
 336                         [(truncstorei8 GR64:$src, rriaddr12:$dst)]>;
 337
 338 def MOV64m8ry  : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 339                         "stcy\t{$src, $dst}",
 340                         [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
 341
 342 def MOV64m16r  : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src),
 343                         "sth\t{$src, $dst}",
 344                         [(truncstorei16 GR64:$src, rriaddr12:$dst)]>;
 345
 346 def MOV64m16ry : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 347                         "sthy\t{$src, $dst}",
 348                         [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
 349
 350 def MOV64m32r  : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src),
 351                         "st\t{$src, $dst}",
 352                         [(truncstorei32 GR64:$src, rriaddr12:$dst)]>;
 353
 354 def MOV64m32ry : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 355                         "sty\t{$src, $dst}",
 356                         [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
 357
 358 // multiple regs moves
 359 // FIXME: should we use multiple arg nodes?
 360 def MOV32mrm  : Pseudo<(outs), (ins riaddr:$dst, GR32:$from, GR32:$to),
 361                        "stmy\t{$from, $to, $dst}",
 362                        []>;
 363 def MOV64mrm  : Pseudo<(outs), (ins riaddr:$dst, GR64:$from, GR64:$to),
 364                        "stmg\t{$from, $to, $dst}",
 365                        []>;
 366 def MOV32rmm  : Pseudo<(outs GR32:$from, GR32:$to), (ins riaddr:$dst),
 367                        "lmy\t{$from, $to, $dst}",
 368                        []>;
 369 def MOV64rmm  : Pseudo<(outs GR64:$from, GR64:$to), (ins riaddr:$dst),
 370                        "lmg\t{$from, $to, $dst}",
 371                        []>;
 372
 373
 374 //===----------------------------------------------------------------------===//
 375 // Arithmetic Instructions
 376
 377 let Defs = [PSW] in {
 378 def NEG32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 379                      "lcr\t{$dst, $src}",
 380                      [(set GR32:$dst, (ineg GR32:$src)),
 381                       (implicit PSW)]>;
 382 def NEG64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 383                      "lcgr\t{$dst, $src}",
 384                      [(set GR64:$dst, (ineg GR64:$src)),
 385                       (implicit PSW)]>;
 386 def NEG64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 387                        "lcgfr\t{$dst, $src}",
 388                        [(set GR64:$dst, (ineg (sext GR32:$src))),
 389                         (implicit PSW)]>;
 390 }
 391
 392 let isTwoAddress = 1 in {
 393
 394 let Defs = [PSW] in {
 395
 396 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
 397 // FIXME: Provide proper encoding!
 398 def ADD32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 399                      "ar\t{$dst, $src2}",
 400                      [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 401                       (implicit PSW)]>;
 402 def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 403                      "agr\t{$dst, $src2}",
 404                      [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
 405                       (implicit PSW)]>;
 406 }
 407
 408 // FIXME: Provide proper encoding!
 409 def ADD32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 410                        "ahi\t{$dst, $src2}",
 411                        [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
 412                         (implicit PSW)]>;
 413 def ADD32ri   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 414                        "afi\t{$dst, $src2}",
 415                        [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
 416                         (implicit PSW)]>;
 417 def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 418                        "aghi\t{$dst, $src2}",
 419                        [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
 420                         (implicit PSW)]>;
 421 def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 422                        "agfi\t{$dst, $src2}",
 423                        [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
 424                         (implicit PSW)]>;
 425
 426 let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
 427 // FIXME: Provide proper encoding!
 428 def AND32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 429                      "nr\t{$dst, $src2}",
 430                      [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
 431 def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 432                      "ngr\t{$dst, $src2}",
 433                      [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
 434 }
 435
 436 // FIXME: Provide proper encoding!
 437 // FIXME: Compute masked bits properly!
 438 def AND32rill16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 439                          "nill\t{$dst, $src2}",
 440                         [(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>;
 441 def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 442                          "nill\t{$dst, $src2}",
 443                          [(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>;
 444
 445 def AND32rilh16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 446                          "nilh\t{$dst, $src2}",
 447                          [(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>;
 448 def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 449                          "nilh\t{$dst, $src2}",
 450                          [(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>;
 451
 452 def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 453                          "nihl\t{$dst, $src2}",
 454                          [(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>;
 455 def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 456                          "nihh\t{$dst, $src2}",
 457                          [(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>;
 458
 459 def AND32ri     : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 460                          "nilf\t{$dst, $src2}",
 461                          [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
 462 def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 463                          "nilf\t{$dst, $src2}",
 464                          [(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>;
 465 def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 466                          "nihf\t{$dst, $src2}",
 467                          [(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>;
 468
 469 let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
 470 // FIXME: Provide proper encoding!
 471 def OR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 472                     "or\t{$dst, $src2}",
 473                     [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
 474 def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 475                     "ogr\t{$dst, $src2}",
 476                     [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
 477 }
 478
 479 def OR32ri16  : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 480                       "oill\t{$dst, $src2}",
 481                       [(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>;
 482 def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 483                       "oilh\t{$dst, $src2}",
 484                       [(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>;
 485 def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 486                     "oilf\t{$dst, $src2}",
 487                     [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
 488
 489 def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 490                         "oill\t{$dst, $src2}",
 491                         [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
 492 def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 493                         "oilh\t{$dst, $src2}",
 494                         [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
 495 def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 496                         "oihl\t{$dst, $src2}",
 497                         [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
 498 def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 499                         "oihh\t{$dst, $src2}",
 500                         [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
 501
 502 def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 503                         "oilf\t{$dst, $src2}",
 504                         [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
 505 def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 506                         "oihf\t{$dst, $src2}",
 507                         [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
 508
 509 // FIXME: Provide proper encoding!
 510 def SUB32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 511                      "sr\t{$dst, $src2}",
 512                      [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
 513 def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 514                      "sgr\t{$dst, $src2}",
 515                      [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
 516
 517
 518 let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
 519 // FIXME: Provide proper encoding!
 520 def XOR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 521                      "xr\t{$dst, $src2}",
 522                      [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
 523 def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 524                      "xgr\t{$dst, $src2}",
 525                      [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
 526 }
 527
 528 def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 529                      "xilf\t{$dst, $src2}",
 530                      [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
 531
 532 } // Defs = [PSW]
 533
 534 let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
 535 def MUL32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 536                      "msr\t{$dst, $src2}",
 537                      [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
 538 def MUL64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 539                      "msgr\t{$dst, $src2}",
 540                      [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
 541 }
 542
 543 def MUL64rrP   : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 544                         "mr\t{$dst, $src2}",
 545                         []>;
 546 def UMUL64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 547                          "mlr\t{$dst, $src2}",
 548                          []>;
 549 def UMUL128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 550                         "mlgr\t{$dst, $src2}",
 551                         []>;
 552
 553 def MUL32ri16   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 554                          "mhi\t{$dst, $src2}",
 555                          [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
 556 def MUL64ri16   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 557                          "mghi\t{$dst, $src2}",
 558                          [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
 559
 560 def MUL32ri     : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 561                          "msfi\t{$dst, $src2}",
 562                          [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>,
 563                          Requires<[IsZ10]>;
 564 def MUL64ri32   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 565                          "msgfi\t{$dst, $src2}",
 566                          [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
 567                          Requires<[IsZ10]>;
 568
 569 def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
 570                      "ms\t{$dst, $src2}",
 571                      [(set GR32:$dst, (mul GR32:$src1, (load rriaddr12:$src2)))]>;
 572 def MUL32rmy : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 573                       "msy\t{$dst, $src2}",
 574                       [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
 575 def MUL64rm  : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 576                       "msg\t{$dst, $src2}",
 577                       [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
 578
 579 def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
 580                          "msgfr\t{$dst, $src2}",
 581                          [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
 582
 583 def SDIVREM64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 584                            "dr\t{$dst, $src2}",
 585                            []>;
 586
 587 def SDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 588                            "dsgr\t{$dst, $src2}",
 589                            []>;
 590
 591 def UDIVREM64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 592                            "dlr\t{$dst, $src2}",
 593                            []>;
 594
 595 def UDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 596                            "dlgr\t{$dst, $src2}",
 597                            []>;
 598
 599 } // isTwoAddress = 1
 600
 601 //===----------------------------------------------------------------------===//
 602 // Shifts
 603
 604 let isTwoAddress = 1 in
 605 def SRL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 606                       "srl\t{$src, $amt}",
 607                       [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
 608 def SRL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 609                       "srlg\t{$dst, $src, $amt}",
 610                       [(set GR64:$dst, (srl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 611 def SRLA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 612                       "srlg\t{$dst, $src, $amt}",
 613                       [(set GR64:$dst, (srl GR64:$src, (i32 imm:$amt)))]>;
 614
 615 let isTwoAddress = 1 in
 616 def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 617                       "sll\t{$src, $amt}",
 618                       [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
 619 def SHL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 620                       "sllg\t{$dst, $src, $amt}",
 621                       [(set GR64:$dst, (shl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 622 def SHL64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 623                       "sllg\t{$dst, $src, $amt}",
 624                       [(set GR64:$dst, (shl GR64:$src, (i32 imm:$amt)))]>;
 625
 626 let Defs = [PSW] in {
 627 let isTwoAddress = 1 in
 628 def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 629                       "sra\t{$src, $amt}",
 630                       [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
 631                        (implicit PSW)]>;
 632 def SRA64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 633                       "srag\t{$dst, $src, $amt}",
 634                       [(set GR64:$dst, (sra GR64:$src, (i32 (trunc riaddr:$amt)))),
 635                        (implicit PSW)]>;
 636 def SRA64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 637                       "srag\t{$dst, $src, $amt}",
 638                       [(set GR64:$dst, (sra GR64:$src, (i32 imm:$amt))),
 639                        (implicit PSW)]>;
 640 } // Defs = [PSW]
 641
 642 def ROTL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 643                        "rll\t{$dst, $src, $amt}",
 644                        [(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>;
 645 def ROTL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 646                        "rllg\t{$dst, $src, $amt}",
 647                        [(set GR64:$dst, (rotl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
 648 def ROTL64ri  : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
 649                        "rllg\t{$dst, $src, $amt}",
 650                        [(set GR64:$dst, (rotl GR64:$src, (i32 imm:$amt)))]>;
 651
 652 //===----------------------------------------------------------------------===//
 653 // Test instructions (like AND but do not produce any result)
 654
 655 // Integer comparisons
 656 let Defs = [PSW] in {
 657 def CMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 658                      "cr\t$src1, $src2",
 659                      [(SystemZcmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 660 def CMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 661                      "cgr\t$src1, $src2",
 662                      [(SystemZcmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 663
 664 def CMP32ri   : Pseudo<(outs), (ins GR32:$src1, s32imm:$src2),
 665                        "cfi\t$src1, $src2",
 666                        [(SystemZcmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 667 def CMP64ri32 : Pseudo<(outs), (ins GR64:$src1, s32imm64:$src2),
 668                        "cgfi\t$src1, $src2",
 669                        [(SystemZcmp GR64:$src1, i64immSExt32:$src2),
 670                         (implicit PSW)]>;
 671
 672 def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr12:$src2),
 673                      "c\t$src1, $src2",
 674                      [(SystemZcmp GR32:$src1, (load rriaddr12:$src2)),
 675                       (implicit PSW)]>;
 676 def CMP32rmy : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 677                       "cy\t$src1, $src2",
 678                       [(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
 679                        (implicit PSW)]>;
 680 def CMP64rm  : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 681                       "cg\t$src1, $src2",
 682                       [(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
 683                        (implicit PSW)]>;
 684
 685 def UCMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 686                       "clr\t$src1, $src2",
 687                       [(SystemZucmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 688 def UCMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 689                       "clgr\t$src1, $src2",
 690                       [(SystemZucmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 691
 692 def UCMP32ri   : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2),
 693                         "clfi\t$src1, $src2",
 694                         [(SystemZucmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 695 def UCMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2),
 696                         "clgfi\t$src1, $src2",
 697                         [(SystemZucmp GR64:$src1, i64immZExt32:$src2),
 698                          (implicit PSW)]>;
 699
 700 def UCMP32rm  : Pseudo<(outs), (ins GR32:$src1, rriaddr12:$src2),
 701                        "cl\t$src1, $src2",
 702                        [(SystemZucmp GR32:$src1, (load rriaddr12:$src2)),
 703                         (implicit PSW)]>;
 704 def UCMP32rmy : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 705                        "cly\t$src1, $src2",
 706                        [(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
 707                         (implicit PSW)]>;
 708 def UCMP64rm  : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 709                        "clg\t$src1, $src2",
 710                        [(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
 711                         (implicit PSW)]>;
 712
 713 def CMPSX64rr32  : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 714                           "cgfr\t$src1, $src2",
 715                           [(SystemZucmp GR64:$src1, (sext GR32:$src2)),
 716                            (implicit PSW)]>;
 717 def UCMPZX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 718                           "clgfr\t$src1, $src2",
 719                           [(SystemZucmp GR64:$src1, (zext GR32:$src2)),
 720                            (implicit PSW)]>;
 721
 722 def CMPSX64rm32   : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 723                            "cgf\t$src1, $src2",
 724                            [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
 725                             (implicit PSW)]>;
 726 def UCMPZX64rm32  : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 727                            "clgf\t$src1, $src2",
 728                            [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
 729                             (implicit PSW)]>;
 730
 731 // FIXME: Add other crazy ucmp forms
 732
 733 } // Defs = [PSW]
 734
 735 //===----------------------------------------------------------------------===//
 736 // Non-Instruction Patterns.
 737 //===----------------------------------------------------------------------===//
 738
 739 // JumpTable
 740 def : Pat<(SystemZpcrelwrapper tjumptable:$src), (LA64rm tjumptable:$src)>;
 741
 742 // anyext
 743 def : Pat<(i64 (anyext GR32:$src)),
 744           (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
 745
 746 // calls
 747 def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), (CALLi tglobaladdr:$dst)>;
 748 def : Pat<(SystemZcall (i64 texternalsym:$dst)), (CALLi texternalsym:$dst)>;
 749
 750 //===----------------------------------------------------------------------===//
 751 // Peepholes.
 752 //===----------------------------------------------------------------------===//
 753
 754 // FIXME: use add/sub tricks with 32678/-32768
 755
 756 // Arbitrary immediate support.  Implement in terms of LLIHF/OILF.
 757 def : Pat<(i64 imm:$imm),
 758           (OR64rilo32 (MOV64rihi32 (HI32 imm:$imm)), (LO32 imm:$imm))>;
 759
 760 // trunc patterns
 761 def : Pat<(i32 (trunc GR64:$src)),
 762           (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
 763
 764 // sext_inreg patterns
 765 def : Pat<(sext_inreg GR64:$src, i32),
 766           (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
 767
 768 // extload patterns
 769 def : Pat<(extloadi32i8  rriaddr:$src), (MOVZX32rm8  rriaddr:$src)>;
 770 def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>;
 771 def : Pat<(extloadi64i8  rriaddr:$src), (MOVZX64rm8  rriaddr:$src)>;
 772 def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
 773 def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
 774
 775 // muls
 776 def : Pat<(mulhs GR32:$src1, GR32:$src2),
 777           (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 778                                                    GR32:$src1, subreg_odd),
 779                                     GR32:$src2),
 780                           subreg_even)>;
 781
 782 def : Pat<(mulhu GR32:$src1, GR32:$src2),
 783           (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 784                                                     GR32:$src1, subreg_odd),
 785                                      GR32:$src2),
 786                           subreg_even)>;
 787 def : Pat<(mulhu GR64:$src1, GR64:$src2),
 788           (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 789                                                      GR64:$src1, subreg_odd),
 790                                       GR64:$src2),
 791                           subreg_even)>;
 792
 793 // divs
 794 // FIXME: Add memory versions
 795 def : Pat<(sdiv GR32:$src1, GR32:$src2),
 796           (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 797                                                        GR32:$src1, subreg_odd),
 798                                          GR32:$src2),
 799                           subreg_odd)>;
 800 def : Pat<(sdiv GR64:$src1, GR64:$src2),
 801           (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 802                                                         GR64:$src1, subreg_odd),
 803                                          GR64:$src2),
 804                           subreg_odd)>;
 805 def : Pat<(udiv GR32:$src1, GR32:$src2),
 806           (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 807                                                        GR32:$src1, subreg_odd),
 808                                          GR32:$src2),
 809                           subreg_odd)>;
 810 def : Pat<(udiv GR64:$src1, GR64:$src2),
 811           (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 812                                                         GR64:$src1, subreg_odd),
 813                                          GR64:$src2),
 814                           subreg_odd)>;
 815
 816 // rems
 817 // FIXME: Add memory versions
 818 def : Pat<(srem GR32:$src1, GR32:$src2),
 819           (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 820                                                        GR32:$src1, subreg_odd),
 821                                          GR32:$src2),
 822                           subreg_even)>;
 823 def : Pat<(srem GR64:$src1, GR64:$src2),
 824           (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 825                                                         GR64:$src1, subreg_odd),
 826                                          GR64:$src2),
 827                           subreg_even)>;
 828 def : Pat<(urem GR32:$src1, GR32:$src2),
 829           (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 830                                                        GR32:$src1, subreg_odd),
 831                                          GR32:$src2),
 832                           subreg_even)>;
 833 def : Pat<(urem GR64:$src1, GR64:$src2),
 834           (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 835                                                         GR64:$src1, subreg_odd),
 836                                          GR64:$src2),
 837                           subreg_even)>;
 838
 839 def : Pat<(i32 imm:$src),
 840           (EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;