1 //===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15 [(callseq_start timm:$amt)]>;
16 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17 [(callseq_end timm:$amt1, timm:$amt2)]>;
19 let neverHasSideEffects = 1 in {
20 // Takes as input the value of the stack pointer after a dynamic allocation
21 // has been made. Sets the output to the address of the dynamically-
22 // allocated area itself, skipping the outgoing arguments.
24 // This expands to an LA or LAY instruction. We restrict the offset
25 // to the range of LA and keep the LAY range in reserve for when
26 // the size of the outgoing arguments is added.
27 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28 [(set GR64:$dst, dynalloc12only:$src)]>;
31 //===----------------------------------------------------------------------===//
32 // Control flow instructions
33 //===----------------------------------------------------------------------===//
35 // A return instruction. R1 is the condition-code mask (all 1s)
36 // and R2 is the target address, which is always stored in %r14.
37 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1,
38 R1 = 15, R2 = 14, isCodeGenOnly = 1 in {
39 def RET : InstRR<0x07, (outs), (ins), "br\t%r14", [(z_retflag)]>;
42 // Unconditional branches. R1 is the condition-code mask (all 1s).
43 let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
44 let isIndirectBranch = 1 in
45 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
46 "br\t$R2", [(brind ADDR64:$R2)]>;
48 // An assembler extended mnemonic for BRC. Use a separate instruction for
49 // the asm parser, so that we don't relax Js to external symbols into JGs.
50 let isCodeGenOnly = 1 in
51 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2", []>;
52 def AsmJ : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2", []>;
54 // An assembler extended mnemonic for BRCL. (The extension is "G"
55 // rather than "L" because "JL" is "Jump if Less".)
56 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
57 "jg\t$I2", [(br bb:$I2)]>;
60 // Conditional branches. It's easier for LLVM to handle these branches
61 // in their raw BRC/BRCL form, with the 4-bit condition-code mask being
62 // the first operand. It seems friendlier to use mnemonic forms like
63 // JE and JLH when writing out the assembly though.
64 multiclass CondBranches<Operand imm, string short, string long> {
65 let isBranch = 1, isTerminator = 1, Uses = [PSW] in {
66 def "" : InstRI<0xA74, (outs), (ins imm:$R1, brtarget16:$I2), short, []>;
67 def L : InstRIL<0xC04, (outs), (ins imm:$R1, brtarget32:$I2), long, []>;
70 let isCodeGenOnly = 1 in
71 defm BRC : CondBranches<cond4, "j$R1\t$I2", "jg$R1\t$I2">;
72 defm AsmBRC : CondBranches<uimm8zx4, "brc\t$R1, $I2", "brcl\t$R1, $I2">;
74 def : Pat<(z_br_ccmask cond4:$cond, bb:$dst), (BRCL cond4:$cond, bb:$dst)>;
76 // Define AsmParser mnemonics for each condition code.
77 multiclass CondExtendedMnemonic<bits<4> Cond, string name> {
79 def "" : InstRI<0xA74, (outs), (ins brtarget16:$I2),
80 "j"##name##"\t$I2", []>;
81 def L : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
82 "jg"##name##"\t$I2", []>;
85 defm AsmJO : CondExtendedMnemonic<1, "o">;
86 defm AsmJH : CondExtendedMnemonic<2, "h">;
87 defm AsmJNLE : CondExtendedMnemonic<3, "nle">;
88 defm AsmJL : CondExtendedMnemonic<4, "l">;
89 defm AsmJNHE : CondExtendedMnemonic<5, "nhe">;
90 defm AsmJLH : CondExtendedMnemonic<6, "lh">;
91 defm AsmJNE : CondExtendedMnemonic<7, "ne">;
92 defm AsmJE : CondExtendedMnemonic<8, "e">;
93 defm AsmJNLH : CondExtendedMnemonic<9, "nlh">;
94 defm AsmJHE : CondExtendedMnemonic<10, "he">;
95 defm AsmJNL : CondExtendedMnemonic<11, "nl">;
96 defm AsmJLE : CondExtendedMnemonic<12, "le">;
97 defm AsmJNH : CondExtendedMnemonic<13, "nh">;
98 defm AsmJNO : CondExtendedMnemonic<14, "no">;
100 def Select32 : SelectWrapper<GR32>;
101 def Select64 : SelectWrapper<GR64>;
103 //===----------------------------------------------------------------------===//
105 //===----------------------------------------------------------------------===//
107 // The definitions here are for the call-clobbered registers.
108 let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
109 F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D],
110 R1 = 14, isCodeGenOnly = 1 in {
111 def BRAS : InstRI<0xA75, (outs), (ins pcrel16call:$I2, variable_ops),
112 "bras\t%r14, $I2", []>;
113 def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$I2, variable_ops),
114 "brasl\t%r14, $I2", [(z_call pcrel32call:$I2)]>;
115 def BASR : InstRR<0x0D, (outs), (ins ADDR64:$R2, variable_ops),
116 "basr\t%r14, $R2", [(z_call ADDR64:$R2)]>;
119 // Define the general form of the call instructions for the asm parser.
120 // These instructions don't hard-code %r14 as the return address register.
121 def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2),
122 "bras\t$R1, $I2", []>;
123 def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2),
124 "brasl\t$R1, $I2", []>;
125 def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
126 "basr\t$R1, $R2", []>;
128 //===----------------------------------------------------------------------===//
130 //===----------------------------------------------------------------------===//
133 let neverHasSideEffects = 1 in {
134 def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>;
135 def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>;
139 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
140 // 16-bit sign-extended immediates.
141 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>;
142 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
144 // Other 16-bit immediates.
145 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
146 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
147 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
148 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
150 // 32-bit immediates.
151 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>;
152 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
153 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
157 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
158 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32>;
159 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;
161 def LG : UnaryRXY<"lg", 0xE304, load, GR64>;
162 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
164 // These instructions are split after register allocation, so we don't
165 // want a custom inserter.
166 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
167 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
168 [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
173 let SimpleBDXStore = 1 in {
174 let isCodeGenOnly = 1 in {
175 defm ST32 : StoreRXPair<"st", 0x50, 0xE350, store, GR32>;
176 def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
179 def STG : StoreRXY<"stg", 0xE324, store, GR64>;
180 def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
182 // These instructions are split after register allocation, so we don't
183 // want a custom inserter.
184 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
185 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
186 [(store GR128:$src, bdxaddr20only128:$dst)]>;
190 // 8-bit immediate stores to 8-bit fields.
191 defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
193 // 16-bit immediate stores to 16-, 32- or 64-bit fields.
194 def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
195 def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>;
196 def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>;
198 //===----------------------------------------------------------------------===//
200 //===----------------------------------------------------------------------===//
202 // 32-bit extensions from registers.
203 let neverHasSideEffects = 1 in {
204 def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>;
205 def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>;
208 // 64-bit extensions from registers.
209 let neverHasSideEffects = 1 in {
210 def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>;
211 def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>;
212 def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>;
215 // Match 32-to-64-bit sign extensions in which the source is already
216 // in a 64-bit register.
217 def : Pat<(sext_inreg GR64:$src, i32),
218 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
220 // 32-bit extensions from memory.
221 def LB : UnaryRXY<"lb", 0xE376, sextloadi8, GR32>;
222 defm LH : UnaryRXPair<"lh", 0x48, 0xE378, sextloadi16, GR32>;
223 def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_sextloadi16, GR32>;
225 // 64-bit extensions from memory.
226 def LGB : UnaryRXY<"lgb", 0xE377, sextloadi8, GR64>;
227 def LGH : UnaryRXY<"lgh", 0xE315, sextloadi16, GR64>;
228 def LGF : UnaryRXY<"lgf", 0xE314, sextloadi32, GR64>;
229 def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_sextloadi16, GR64>;
230 def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_sextloadi32, GR64>;
232 // If the sign of a load-extend operation doesn't matter, use the signed ones.
233 // There's not really much to choose between the sign and zero extensions,
234 // but LH is more compact than LLH for small offsets.
235 def : Pat<(i32 (extloadi8 bdxaddr20only:$src)), (LB bdxaddr20only:$src)>;
236 def : Pat<(i32 (extloadi16 bdxaddr12pair:$src)), (LH bdxaddr12pair:$src)>;
237 def : Pat<(i32 (extloadi16 bdxaddr20pair:$src)), (LHY bdxaddr20pair:$src)>;
239 def : Pat<(i64 (extloadi8 bdxaddr20only:$src)), (LGB bdxaddr20only:$src)>;
240 def : Pat<(i64 (extloadi16 bdxaddr20only:$src)), (LGH bdxaddr20only:$src)>;
241 def : Pat<(i64 (extloadi32 bdxaddr20only:$src)), (LGF bdxaddr20only:$src)>;
243 //===----------------------------------------------------------------------===//
245 //===----------------------------------------------------------------------===//
247 // 32-bit extensions from registers.
248 let neverHasSideEffects = 1 in {
249 def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>;
250 def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>;
253 // 64-bit extensions from registers.
254 let neverHasSideEffects = 1 in {
255 def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>;
256 def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>;
257 def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>;
260 // Match 32-to-64-bit zero extensions in which the source is already
261 // in a 64-bit register.
262 def : Pat<(and GR64:$src, 0xffffffff),
263 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
265 // 32-bit extensions from memory.
266 def LLC : UnaryRXY<"llc", 0xE394, zextloadi8, GR32>;
267 def LLH : UnaryRXY<"llh", 0xE395, zextloadi16, GR32>;
268 def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_zextloadi16, GR32>;
270 // 64-bit extensions from memory.
271 def LLGC : UnaryRXY<"llgc", 0xE390, zextloadi8, GR64>;
272 def LLGH : UnaryRXY<"llgh", 0xE391, zextloadi16, GR64>;
273 def LLGF : UnaryRXY<"llgf", 0xE316, zextloadi32, GR64>;
274 def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_zextloadi16, GR64>;
275 def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_zextloadi32, GR64>;
277 //===----------------------------------------------------------------------===//
279 //===----------------------------------------------------------------------===//
281 // Truncations of 64-bit registers to 32-bit registers.
282 def : Pat<(i32 (trunc GR64:$src)),
283 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
285 // Truncations of 32-bit registers to memory.
286 let isCodeGenOnly = 1 in {
287 defm STC32 : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32>;
288 defm STH32 : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32>;
289 def STHRL32 : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
292 // Truncations of 64-bit registers to memory.
293 defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR64>;
294 defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR64>;
295 def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR64>;
296 defm ST : StoreRXPair<"st", 0x50, 0xE350, truncstorei32, GR64>;
297 def STRL : StoreRILPC<"strl", 0xC4F, aligned_truncstorei32, GR64>;
299 //===----------------------------------------------------------------------===//
300 // Multi-register moves
301 //===----------------------------------------------------------------------===//
303 // Multi-register loads.
304 def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
306 // Multi-register stores.
307 def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
309 //===----------------------------------------------------------------------===//
311 //===----------------------------------------------------------------------===//
313 // Byte-swapping register moves.
314 let neverHasSideEffects = 1 in {
315 def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>;
316 def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>;
319 // Byte-swapping loads.
320 def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap>, GR32>;
321 def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap>, GR64>;
323 // Byte-swapping stores.
324 def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap>, GR32>;
325 def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap>, GR64>;
327 //===----------------------------------------------------------------------===//
328 // Load address instructions
329 //===----------------------------------------------------------------------===//
331 // Load BDX-style addresses.
332 let neverHasSideEffects = 1, Function = "la" in {
333 let PairType = "12" in
334 def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
336 [(set GR64:$R1, laaddr12pair:$XBD2)]>;
337 let PairType = "20" in
338 def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
340 [(set GR64:$R1, laaddr20pair:$XBD2)]>;
343 // Load a PC-relative address. There's no version of this instruction
344 // with a 16-bit offset, so there's no relaxation.
345 let neverHasSideEffects = 1 in {
346 def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
348 [(set GR64:$R1, pcrel32:$I2)]>;
351 //===----------------------------------------------------------------------===//
353 //===----------------------------------------------------------------------===//
355 let Defs = [PSW] in {
356 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>;
357 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>;
358 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>;
360 defm : SXU<ineg, LCGFR>;
362 //===----------------------------------------------------------------------===//
364 //===----------------------------------------------------------------------===//
366 let isCodeGenOnly = 1 in
367 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, zextloadi8>;
368 defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, zextloadi8>;
370 defm : InsertMem<"inserti8", IC32, GR32, zextloadi8, bdxaddr12pair>;
371 defm : InsertMem<"inserti8", IC32Y, GR32, zextloadi8, bdxaddr20pair>;
373 defm : InsertMem<"inserti8", IC, GR64, zextloadi8, bdxaddr12pair>;
374 defm : InsertMem<"inserti8", ICY, GR64, zextloadi8, bdxaddr20pair>;
376 // Insertions of a 16-bit immediate, leaving other bits unaffected.
377 // We don't have or_as_insert equivalents of these operations because
378 // OI is available instead.
379 let isCodeGenOnly = 1 in {
380 def IILL32 : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
381 def IILH32 : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
383 def IILL : BinaryRI<"iill", 0xA53, insertll, GR64, imm64ll16>;
384 def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR64, imm64lh16>;
385 def IIHL : BinaryRI<"iihl", 0xA51, inserthl, GR64, imm64hl16>;
386 def IIHH : BinaryRI<"iihh", 0xA50, inserthh, GR64, imm64hh16>;
388 // ...likewise for 32-bit immediates. For GR32s this is a general
389 // full-width move. (We use IILF rather than something like LLILF
390 // for 32-bit moves because IILF leaves the upper 32 bits of the
392 let isCodeGenOnly = 1 in {
393 def IILF32 : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
395 def IILF : BinaryRIL<"iilf", 0xC09, insertlf, GR64, imm64lf32>;
396 def IIHF : BinaryRIL<"iihf", 0xC08, inserthf, GR64, imm64hf32>;
398 // An alternative model of inserthf, with the first operand being
399 // a zero-extended value.
400 def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
401 (IIHF (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit),
404 //===----------------------------------------------------------------------===//
406 //===----------------------------------------------------------------------===//
409 let Defs = [PSW] in {
410 // Addition of a register.
411 let isCommutable = 1 in {
412 def AR : BinaryRR <"ar", 0x1A, add, GR32, GR32>;
413 def AGR : BinaryRRE<"agr", 0xB908, add, GR64, GR64>;
415 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>;
417 // Addition of signed 16-bit immediates.
418 def AHI : BinaryRI<"ahi", 0xA7A, add, GR32, imm32sx16>;
419 def AGHI : BinaryRI<"aghi", 0xA7B, add, GR64, imm64sx16>;
421 // Addition of signed 32-bit immediates.
422 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>;
423 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
425 // Addition of memory.
426 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, sextloadi16>;
427 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load>;
428 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, sextloadi32>;
429 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load>;
431 // Addition to memory.
432 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>;
433 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
435 defm : SXB<add, GR64, AGFR>;
437 // Addition producing a carry.
438 let Defs = [PSW] in {
439 // Addition of a register.
440 let isCommutable = 1 in {
441 def ALR : BinaryRR <"alr", 0x1E, addc, GR32, GR32>;
442 def ALGR : BinaryRRE<"algr", 0xB90A, addc, GR64, GR64>;
444 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>;
446 // Addition of unsigned 32-bit immediates.
447 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>;
448 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
450 // Addition of memory.
451 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load>;
452 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, zextloadi32>;
453 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load>;
455 defm : ZXB<addc, GR64, ALGFR>;
457 // Addition producing and using a carry.
458 let Defs = [PSW], Uses = [PSW] in {
459 // Addition of a register.
460 def ALCR : BinaryRRE<"alcr", 0xB998, adde, GR32, GR32>;
461 def ALCGR : BinaryRRE<"alcgr", 0xB988, adde, GR64, GR64>;
463 // Addition of memory.
464 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load>;
465 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load>;
468 //===----------------------------------------------------------------------===//
470 //===----------------------------------------------------------------------===//
472 // Plain substraction. Although immediate forms exist, we use the
473 // add-immediate instruction instead.
474 let Defs = [PSW] in {
475 // Subtraction of a register.
476 def SR : BinaryRR <"sr", 0x1B, sub, GR32, GR32>;
477 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>;
478 def SGR : BinaryRRE<"sgr", 0xB909, sub, GR64, GR64>;
480 // Subtraction of memory.
481 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, sextloadi16>;
482 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load>;
483 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, sextloadi32>;
484 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load>;
486 defm : SXB<sub, GR64, SGFR>;
488 // Subtraction producing a carry.
489 let Defs = [PSW] in {
490 // Subtraction of a register.
491 def SLR : BinaryRR <"slr", 0x1F, subc, GR32, GR32>;
492 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>;
493 def SLGR : BinaryRRE<"slgr", 0xB90B, subc, GR64, GR64>;
495 // Subtraction of unsigned 32-bit immediates. These don't match
496 // subc because we prefer addc for constants.
497 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>;
498 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
500 // Subtraction of memory.
501 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load>;
502 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, zextloadi32>;
503 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load>;
505 defm : ZXB<subc, GR64, SLGFR>;
507 // Subtraction producing and using a carry.
508 let Defs = [PSW], Uses = [PSW] in {
509 // Subtraction of a register.
510 def SLBR : BinaryRRE<"slbr", 0xB999, sube, GR32, GR32>;
511 def SLGBR : BinaryRRE<"slbgr", 0xB989, sube, GR64, GR64>;
513 // Subtraction of memory.
514 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load>;
515 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load>;
518 //===----------------------------------------------------------------------===//
520 //===----------------------------------------------------------------------===//
522 let Defs = [PSW] in {
523 // ANDs of a register.
524 let isCommutable = 1 in {
525 def NR : BinaryRR <"nr", 0x14, and, GR32, GR32>;
526 def NGR : BinaryRRE<"ngr", 0xB980, and, GR64, GR64>;
529 // ANDs of a 16-bit immediate, leaving other bits unaffected.
530 let isCodeGenOnly = 1 in {
531 def NILL32 : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
532 def NILH32 : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
534 def NILL : BinaryRI<"nill", 0xA57, and, GR64, imm64ll16c>;
535 def NILH : BinaryRI<"nilh", 0xA56, and, GR64, imm64lh16c>;
536 def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>;
537 def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>;
539 // ANDs of a 32-bit immediate, leaving other bits unaffected.
540 let isCodeGenOnly = 1 in
541 def NILF32 : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
542 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR64, imm64lf32c>;
543 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>;
546 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load>;
547 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load>;
550 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>;
552 defm : RMWIByte<and, bdaddr12pair, NI>;
553 defm : RMWIByte<and, bdaddr20pair, NIY>;
555 //===----------------------------------------------------------------------===//
557 //===----------------------------------------------------------------------===//
559 let Defs = [PSW] in {
560 // ORs of a register.
561 let isCommutable = 1 in {
562 def OR : BinaryRR <"or", 0x16, or, GR32, GR32>;
563 def OGR : BinaryRRE<"ogr", 0xB981, or, GR64, GR64>;
566 // ORs of a 16-bit immediate, leaving other bits unaffected.
567 let isCodeGenOnly = 1 in {
568 def OILL32 : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
569 def OILH32 : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
571 def OILL : BinaryRI<"oill", 0xA5B, or, GR64, imm64ll16>;
572 def OILH : BinaryRI<"oilh", 0xA5A, or, GR64, imm64lh16>;
573 def OIHL : BinaryRI<"oihl", 0xA59, or, GR64, imm64hl16>;
574 def OIHH : BinaryRI<"oihh", 0xA58, or, GR64, imm64hh16>;
576 // ORs of a 32-bit immediate, leaving other bits unaffected.
577 let isCodeGenOnly = 1 in
578 def OILF32 : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
579 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR64, imm64lf32>;
580 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GR64, imm64hf32>;
583 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load>;
584 def OG : BinaryRXY<"og", 0xE381, or, GR64, load>;
587 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>;
589 defm : RMWIByte<or, bdaddr12pair, OI>;
590 defm : RMWIByte<or, bdaddr20pair, OIY>;
592 //===----------------------------------------------------------------------===//
594 //===----------------------------------------------------------------------===//
596 let Defs = [PSW] in {
597 // XORs of a register.
598 let isCommutable = 1 in {
599 def XR : BinaryRR <"xr", 0x17, xor, GR32, GR32>;
600 def XGR : BinaryRRE<"xgr", 0xB982, xor, GR64, GR64>;
603 // XORs of a 32-bit immediate, leaving other bits unaffected.
604 let isCodeGenOnly = 1 in
605 def XILF32 : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
606 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR64, imm64lf32>;
607 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>;
610 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load>;
611 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load>;
614 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>;
616 defm : RMWIByte<xor, bdaddr12pair, XI>;
617 defm : RMWIByte<xor, bdaddr20pair, XIY>;
619 //===----------------------------------------------------------------------===//
621 //===----------------------------------------------------------------------===//
623 // Multiplication of a register.
624 let isCommutable = 1 in {
625 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>;
626 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>;
628 def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>;
629 defm : SXB<mul, GR64, MSGFR>;
631 // Multiplication of a signed 16-bit immediate.
632 def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>;
633 def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
635 // Multiplication of a signed 32-bit immediate.
636 def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>;
637 def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
639 // Multiplication of memory.
640 defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, sextloadi16>;
641 defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load>;
642 def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, sextloadi32>;
643 def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load>;
645 // Multiplication of a register, producing two results.
646 def MLGR : BinaryRRE<"mlgr", 0xB986, z_umul_lohi64, GR128, GR64>;
648 // Multiplication of memory, producing two results.
649 def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load>;
651 //===----------------------------------------------------------------------===//
652 // Division and remainder
653 //===----------------------------------------------------------------------===//
655 // Division and remainder, from registers.
656 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>;
657 def DSGR : BinaryRRE<"dsgr", 0xB90D, z_sdivrem64, GR128, GR64>;
658 def DLR : BinaryRRE<"dlr", 0xB997, z_udivrem32, GR128, GR32>;
659 def DLGR : BinaryRRE<"dlgr", 0xB987, z_udivrem64, GR128, GR64>;
660 defm : SXB<z_sdivrem64, GR128, DSGFR>;
662 // Division and remainder, from memory.
663 def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem64, GR128, sextloadi32>;
664 def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load>;
665 def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load>;
666 def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load>;
668 //===----------------------------------------------------------------------===//
670 //===----------------------------------------------------------------------===//
673 let neverHasSideEffects = 1 in {
674 def SLL : ShiftRS <"sll", 0x89, shl, GR32, shift12only>;
675 def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64, shift20only>;
678 // Logical shift right.
679 let neverHasSideEffects = 1 in {
680 def SRL : ShiftRS <"srl", 0x88, srl, GR32, shift12only>;
681 def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64, shift20only>;
684 // Arithmetic shift right.
685 let Defs = [PSW] in {
686 def SRA : ShiftRS <"sra", 0x8A, sra, GR32, shift12only>;
687 def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64, shift20only>;
691 let neverHasSideEffects = 1 in {
692 def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32, shift20only>;
693 def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64, shift20only>;
696 // Rotate second operand left and inserted selected bits into first operand.
697 // These can act like 32-bit operands provided that the constant start and
698 // end bits (operands 2 and 3) are in the range [32, 64)
699 let Defs = [PSW] in {
700 let isCodeGenOnly = 1 in
701 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
702 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
705 //===----------------------------------------------------------------------===//
707 //===----------------------------------------------------------------------===//
709 // Signed comparisons.
710 let Defs = [PSW] in {
711 // Comparison with a register.
712 def CR : CompareRR <"cr", 0x19, z_cmp, GR32, GR32>;
713 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>;
714 def CGR : CompareRRE<"cgr", 0xB920, z_cmp, GR64, GR64>;
716 // Comparison with a signed 16-bit immediate.
717 def CHI : CompareRI<"chi", 0xA7E, z_cmp, GR32, imm32sx16>;
718 def CGHI : CompareRI<"cghi", 0xA7F, z_cmp, GR64, imm64sx16>;
720 // Comparison with a signed 32-bit immediate.
721 def CFI : CompareRIL<"cfi", 0xC2D, z_cmp, GR32, simm32>;
722 def CGFI : CompareRIL<"cgfi", 0xC2C, z_cmp, GR64, imm64sx32>;
724 // Comparison with memory.
725 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_cmp, GR32, sextloadi16>;
726 defm C : CompareRXPair<"c", 0x59, 0xE359, z_cmp, GR32, load>;
727 def CGH : CompareRXY<"cgh", 0xE334, z_cmp, GR64, sextloadi16>;
728 def CGF : CompareRXY<"cgf", 0xE330, z_cmp, GR64, sextloadi32>;
729 def CG : CompareRXY<"cg", 0xE320, z_cmp, GR64, load>;
730 def CHRL : CompareRILPC<"chrl", 0xC65, z_cmp, GR32, aligned_sextloadi16>;
731 def CRL : CompareRILPC<"crl", 0xC6D, z_cmp, GR32, aligned_load>;
732 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_cmp, GR64, aligned_sextloadi16>;
733 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_cmp, GR64, aligned_sextloadi32>;
734 def CGRL : CompareRILPC<"cgrl", 0xC68, z_cmp, GR64, aligned_load>;
736 // Comparison between memory and a signed 16-bit immediate.
737 def CHHSI : CompareSIL<"chhsi", 0xE554, z_cmp, sextloadi16, imm32sx16>;
738 def CHSI : CompareSIL<"chsi", 0xE55C, z_cmp, load, imm32sx16>;
739 def CGHSI : CompareSIL<"cghsi", 0xE558, z_cmp, load, imm64sx16>;
741 defm : SXB<z_cmp, GR64, CGFR>;
743 // Unsigned comparisons.
744 let Defs = [PSW] in {
745 // Comparison with a register.
746 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>;
747 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>;
748 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>;
750 // Comparison with a signed 32-bit immediate.
751 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>;
752 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
754 // Comparison with memory.
755 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load>;
756 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, zextloadi32>;
757 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load>;
758 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32,
759 aligned_zextloadi16>;
760 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32,
762 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
763 aligned_zextloadi16>;
764 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
765 aligned_zextloadi32>;
766 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64,
769 // Comparison between memory and an unsigned 8-bit immediate.
770 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, zextloadi8, imm32zx8>;
772 // Comparison between memory and an unsigned 16-bit immediate.
773 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, zextloadi16, imm32zx16>;
774 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
775 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
777 defm : ZXB<z_ucmp, GR64, CLGFR>;
779 //===----------------------------------------------------------------------===//
781 //===----------------------------------------------------------------------===//
783 def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>;
784 def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>;
785 def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>;
787 def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
788 def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
789 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>;
790 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
791 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
792 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>;
793 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
794 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
796 def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
797 def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>;
798 def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>;
800 def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
801 def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
802 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>;
803 def ATOMIC_LOAD_NILL32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>;
804 def ATOMIC_LOAD_NILH32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>;
805 def ATOMIC_LOAD_NILF32 : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
806 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>;
807 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>;
808 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>;
809 def ATOMIC_LOAD_NIHL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>;
810 def ATOMIC_LOAD_NIHH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>;
811 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>;
812 def ATOMIC_LOAD_NIHF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>;
814 def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
815 def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
816 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>;
817 def ATOMIC_LOAD_OILL32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
818 def ATOMIC_LOAD_OILH32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
819 def ATOMIC_LOAD_OILF32 : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
820 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>;
821 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
822 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
823 def ATOMIC_LOAD_OIHL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
824 def ATOMIC_LOAD_OIHH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
825 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
826 def ATOMIC_LOAD_OIHF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
828 def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
829 def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
830 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>;
831 def ATOMIC_LOAD_XILF32 : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
832 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>;
833 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
834 def ATOMIC_LOAD_XIHF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
836 def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
837 def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
839 def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>;
840 def ATOMIC_LOAD_NILL32i : AtomicLoadBinaryImm32<atomic_load_nand_32,
842 def ATOMIC_LOAD_NILH32i : AtomicLoadBinaryImm32<atomic_load_nand_32,
844 def ATOMIC_LOAD_NILF32i : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
845 def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>;
846 def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm64<atomic_load_nand_64,
848 def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm64<atomic_load_nand_64,
850 def ATOMIC_LOAD_NIHLi : AtomicLoadBinaryImm64<atomic_load_nand_64,
852 def ATOMIC_LOAD_NIHHi : AtomicLoadBinaryImm64<atomic_load_nand_64,
854 def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm64<atomic_load_nand_64,
856 def ATOMIC_LOAD_NIHFi : AtomicLoadBinaryImm64<atomic_load_nand_64,
859 def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
860 def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>;
861 def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>;
863 def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
864 def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>;
865 def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>;
867 def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
868 def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
869 def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
871 def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
872 def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
873 def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
876 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
877 ADDR32:$bitshift, ADDR32:$negbitshift,
880 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
881 ADDR32:$bitshift, ADDR32:$negbitshift,
882 uimm32:$bitsize))]> {
886 let usesCustomInserter = 1;
889 let Defs = [PSW] in {
890 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
891 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
894 //===----------------------------------------------------------------------===//
895 // Miscellaneous Instructions.
896 //===----------------------------------------------------------------------===//
898 // Read a 32-bit access register into a GR32. As with all GR32 operations,
899 // the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
900 // when a 64-bit address is stored in a pair of access registers.
901 def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
903 [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
905 // Find leftmost one, AKA count leading zeros. The instruction actually
906 // returns a pair of GR64s, the first giving the number of leading zeros
907 // and the second giving a copy of the source with the leftmost one bit
908 // cleared. We only use the first result here.
909 let Defs = [PSW] in {
910 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>;
912 def : Pat<(ctlz GR64:$src),
913 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_high)>;
915 // Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
916 def : Pat<(i64 (anyext GR32:$src)),
917 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
919 // There are no 32-bit equivalents of LLILL and LLILH, so use a full
920 // 64-bit move followed by a subreg. This preserves the invariant that
921 // all GR32 operations only modify the low 32 bits.
922 def : Pat<(i32 imm32ll16:$src),
923 (EXTRACT_SUBREG (LLILL (LL16 imm:$src)), subreg_32bit)>;
924 def : Pat<(i32 imm32lh16:$src),
925 (EXTRACT_SUBREG (LLILH (LH16 imm:$src)), subreg_32bit)>;
927 // Extend GR32s and GR64s to GR128s.
928 let usesCustomInserter = 1 in {
929 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
930 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
931 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
934 //===----------------------------------------------------------------------===//
936 //===----------------------------------------------------------------------===//
938 // Use AL* for GR64 additions of unsigned 32-bit values.
939 defm : ZXB<add, GR64, ALGFR>;
940 def : Pat<(add GR64:$src1, imm64zx32:$src2),
941 (ALGFI GR64:$src1, imm64zx32:$src2)>;
942 def : Pat<(add GR64:$src1, (zextloadi32 bdxaddr20only:$addr)),
943 (ALGF GR64:$src1, bdxaddr20only:$addr)>;
945 // Use SL* for GR64 subtractions of unsigned 32-bit values.
946 defm : ZXB<sub, GR64, SLGFR>;
947 def : Pat<(add GR64:$src1, imm64zx32n:$src2),
948 (SLGFI GR64:$src1, imm64zx32n:$src2)>;
949 def : Pat<(sub GR64:$src1, (zextloadi32 bdxaddr20only:$addr)),
950 (SLGF GR64:$src1, bdxaddr20only:$addr)>;