1 //===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15 [(callseq_start timm:$amt)]>;
16 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17 [(callseq_end timm:$amt1, timm:$amt2)]>;
19 let neverHasSideEffects = 1 in {
20 // Takes as input the value of the stack pointer after a dynamic allocation
21 // has been made. Sets the output to the address of the dynamically-
22 // allocated area itself, skipping the outgoing arguments.
24 // This expands to an LA or LAY instruction. We restrict the offset
25 // to the range of LA and keep the LAY range in reserve for when
26 // the size of the outgoing arguments is added.
27 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28 [(set GR64:$dst, dynalloc12only:$src)]>;
31 //===----------------------------------------------------------------------===//
32 // Control flow instructions
33 //===----------------------------------------------------------------------===//
35 // A return instruction. R1 is the condition-code mask (all 1s)
36 // and R2 is the target address, which is always stored in %r14.
37 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1,
38 R1 = 15, R2 = 14, isCodeGenOnly = 1 in {
39 def RET : InstRR<0x07, (outs), (ins), "br\t%r14", [(z_retflag)]>;
42 // Unconditional branches. R1 is the condition-code mask (all 1s).
43 let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
44 let isIndirectBranch = 1 in
45 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
46 "br\t$R2", [(brind ADDR64:$R2)]>;
48 // An assembler extended mnemonic for BRC.
49 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
52 // An assembler extended mnemonic for BRCL. (The extension is "G"
53 // rather than "L" because "JL" is "Jump if Less".)
54 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
57 // Conditional branches. It's easier for LLVM to handle these branches
58 // in their raw BRC/BRCL form, with the 4-bit condition-code mask being
59 // the first operand. It seems friendlier to use mnemonic forms like
60 // JE and JLH when writing out the assembly though.
61 multiclass CondBranches<Operand ccmask, string short, string long> {
62 let isBranch = 1, isTerminator = 1, Uses = [CC] in {
63 def "" : InstRI<0xA74, (outs), (ins ccmask:$R1, brtarget16:$I2), short, []>;
64 def L : InstRIL<0xC04, (outs), (ins ccmask:$R1, brtarget32:$I2), long, []>;
67 let isCodeGenOnly = 1 in
68 defm BRC : CondBranches<cond4, "j$R1\t$I2", "jg$R1\t$I2">;
69 defm AsmBRC : CondBranches<uimm8zx4, "brc\t$R1, $I2", "brcl\t$R1, $I2">;
71 def : Pat<(z_br_ccmask cond4:$cond, bb:$dst), (BRC cond4:$cond, bb:$dst)>;
73 // Fused compare-and-branch instructions. As for normal branches,
74 // we handle these instructions internally in their raw CRJ-like form,
75 // but use assembly macros like CRJE when writing them out.
77 // These instructions do not use or clobber the condition codes.
78 // We nevertheless pretend that they clobber CC, so that we can lower
79 // them to separate comparisons and BRCLs if the branch ends up being
81 multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
82 let isBranch = 1, isTerminator = 1, Defs = [CC] in {
83 def RJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
85 "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
86 def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
88 "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
89 def IJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
91 "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
92 def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
94 "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
97 let isCodeGenOnly = 1 in
98 defm C : CompareBranches<cond4, "$M3", "">;
99 defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">;
101 // Define AsmParser mnemonics for each general condition-code mask
102 // (integer or floating-point)
103 multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
105 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2),
106 "j"##name##"\t$I2", []>;
107 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
108 "jg"##name##"\t$I2", []>;
110 def LOCR : FixedCondUnaryRRF<"locr"##name, 0xB9F2, GR32, GR32, ccmask>;
111 def LOCGR : FixedCondUnaryRRF<"locgr"##name, 0xB9E2, GR64, GR64, ccmask>;
112 def LOC : FixedCondUnaryRSY<"loc"##name, 0xEBF2, GR32, ccmask, 4>;
113 def LOCG : FixedCondUnaryRSY<"locg"##name, 0xEBE2, GR64, ccmask, 8>;
114 def STOC : FixedCondStoreRSY<"stoc"##name, 0xEBF3, GR32, ccmask, 4>;
115 def STOCG : FixedCondStoreRSY<"stocg"##name, 0xEBE3, GR64, ccmask, 8>;
117 defm AsmO : CondExtendedMnemonic<1, "o">;
118 defm AsmH : CondExtendedMnemonic<2, "h">;
119 defm AsmNLE : CondExtendedMnemonic<3, "nle">;
120 defm AsmL : CondExtendedMnemonic<4, "l">;
121 defm AsmNHE : CondExtendedMnemonic<5, "nhe">;
122 defm AsmLH : CondExtendedMnemonic<6, "lh">;
123 defm AsmNE : CondExtendedMnemonic<7, "ne">;
124 defm AsmE : CondExtendedMnemonic<8, "e">;
125 defm AsmNLH : CondExtendedMnemonic<9, "nlh">;
126 defm AsmHE : CondExtendedMnemonic<10, "he">;
127 defm AsmNL : CondExtendedMnemonic<11, "nl">;
128 defm AsmLE : CondExtendedMnemonic<12, "le">;
129 defm AsmNH : CondExtendedMnemonic<13, "nh">;
130 defm AsmNO : CondExtendedMnemonic<14, "no">;
132 // Define AsmParser mnemonics for each integer condition-code mask.
133 // This is like the list above, except that condition 3 is not possible
134 // and that the low bit of the mask is therefore always 0. This means
135 // that each condition has two names. Conditions "o" and "no" are not used.
137 // We don't make one of the two names an alias of the other because
138 // we need the custom parsing routines to select the correct register class.
139 multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
141 def CR : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
143 "crj"##name##"\t$R1, $R2, $RI4", []>;
144 def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
146 "cgrj"##name##"\t$R1, $R2, $RI4", []>;
147 def CI : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
149 "cij"##name##"\t$R1, $I2, $RI4", []>;
150 def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
152 "cgij"##name##"\t$R1, $I2, $RI4", []>;
155 multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
156 : IntCondExtendedMnemonicA<ccmask, name1> {
157 let isAsmParserOnly = 1 in
158 defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
160 defm AsmJH : IntCondExtendedMnemonic<2, "h", "nle">;
161 defm AsmJL : IntCondExtendedMnemonic<4, "l", "nhe">;
162 defm AsmJLH : IntCondExtendedMnemonic<6, "lh", "ne">;
163 defm AsmJE : IntCondExtendedMnemonic<8, "e", "nlh">;
164 defm AsmJHE : IntCondExtendedMnemonic<10, "he", "nl">;
165 defm AsmJLE : IntCondExtendedMnemonic<12, "le", "nh">;
167 //===----------------------------------------------------------------------===//
168 // Select instructions
169 //===----------------------------------------------------------------------===//
171 def Select32 : SelectWrapper<GR32>;
172 def Select64 : SelectWrapper<GR64>;
174 defm CondStore8_32 : CondStores<GR32, nonvolatile_truncstorei8,
175 nonvolatile_anyextloadi8, bdxaddr20only>;
176 defm CondStore16_32 : CondStores<GR32, nonvolatile_truncstorei16,
177 nonvolatile_anyextloadi16, bdxaddr20only>;
178 defm CondStore32_32 : CondStores<GR32, nonvolatile_store,
179 nonvolatile_load, bdxaddr20only>;
181 defm CondStore8 : CondStores<GR64, nonvolatile_truncstorei8,
182 nonvolatile_anyextloadi8, bdxaddr20only>;
183 defm CondStore16 : CondStores<GR64, nonvolatile_truncstorei16,
184 nonvolatile_anyextloadi16, bdxaddr20only>;
185 defm CondStore32 : CondStores<GR64, nonvolatile_truncstorei32,
186 nonvolatile_anyextloadi32, bdxaddr20only>;
187 defm CondStore64 : CondStores<GR64, nonvolatile_store,
188 nonvolatile_load, bdxaddr20only>;
190 //===----------------------------------------------------------------------===//
192 //===----------------------------------------------------------------------===//
194 // The definitions here are for the call-clobbered registers.
195 let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
196 F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D],
197 R1 = 14, isCodeGenOnly = 1 in {
198 def BRAS : InstRI<0xA75, (outs), (ins pcrel16call:$I2, variable_ops),
199 "bras\t%r14, $I2", []>;
200 def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$I2, variable_ops),
201 "brasl\t%r14, $I2", [(z_call pcrel32call:$I2)]>;
202 def BASR : InstRR<0x0D, (outs), (ins ADDR64:$R2, variable_ops),
203 "basr\t%r14, $R2", [(z_call ADDR64:$R2)]>;
206 // Define the general form of the call instructions for the asm parser.
207 // These instructions don't hard-code %r14 as the return address register.
208 def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2),
209 "bras\t$R1, $I2", []>;
210 def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2),
211 "brasl\t$R1, $I2", []>;
212 def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
213 "basr\t$R1, $R2", []>;
215 //===----------------------------------------------------------------------===//
217 //===----------------------------------------------------------------------===//
220 let neverHasSideEffects = 1 in {
221 def LR : UnaryRR <"l", 0x18, null_frag, GR32, GR32>;
222 def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
225 // Move on condition.
226 let isCodeGenOnly = 1, Uses = [CC] in {
227 def LOCR : CondUnaryRRF<"loc", 0xB9F2, GR32, GR32>;
228 def LOCGR : CondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
231 def AsmLOCR : AsmCondUnaryRRF<"loc", 0xB9F2, GR32, GR32>;
232 def AsmLOCGR : AsmCondUnaryRRF<"locg", 0xB9E2, GR64, GR64>;
236 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
237 isReMaterializable = 1 in {
238 // 16-bit sign-extended immediates.
239 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>;
240 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
242 // Other 16-bit immediates.
243 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
244 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
245 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
246 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
248 // 32-bit immediates.
249 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>;
250 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
251 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
255 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
256 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
257 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
259 // These instructions are split after register allocation, so we don't
260 // want a custom inserter.
261 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
262 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
263 [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
266 let canFoldAsLoad = 1 in {
267 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;
268 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
271 // Load on condition.
272 let isCodeGenOnly = 1, Uses = [CC] in {
273 def LOC : CondUnaryRSY<"loc", 0xEBF2, GR32, 4>;
274 def LOCG : CondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
277 def AsmLOC : AsmCondUnaryRSY<"loc", 0xEBF2, GR32, 4>;
278 def AsmLOCG : AsmCondUnaryRSY<"locg", 0xEBE2, GR64, 8>;
280 defm : CondLoad<LOC, GR32, nonvolatile_load>;
281 defm : CondLoad<LOCG, GR64, nonvolatile_load>;
284 let SimpleBDXStore = 1 in {
285 let isCodeGenOnly = 1 in
286 defm ST32 : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
287 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
289 // These instructions are split after register allocation, so we don't
290 // want a custom inserter.
291 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
292 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
293 [(store GR128:$src, bdxaddr20only128:$dst)]>;
296 let isCodeGenOnly = 1 in
297 def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
298 def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
300 // Store on condition.
301 let isCodeGenOnly = 1, Uses = [CC] in {
302 def STOC32 : CondStoreRSY<"stoc", 0xEBF3, GR32, 4>;
303 def STOC : CondStoreRSY<"stoc", 0xEBF3, GR64, 4>;
304 def STOCG : CondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
307 def AsmSTOC : AsmCondStoreRSY<"stoc", 0xEBF3, GR32, 4>;
308 def AsmSTOCG : AsmCondStoreRSY<"stocg", 0xEBE3, GR64, 8>;
311 // 8-bit immediate stores to 8-bit fields.
312 defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
314 // 16-bit immediate stores to 16-, 32- or 64-bit fields.
315 def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
316 def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>;
317 def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>;
319 // Memory-to-memory moves.
320 let mayLoad = 1, mayStore = 1 in
321 def MVC : InstSS<0xD2, (outs), (ins bdladdr12onlylen8:$BDL1,
323 "mvc\t$BDL1, $BD2", []>;
325 let mayLoad = 1, mayStore = 1, usesCustomInserter = 1 in
326 def MVCWrapper : Pseudo<(outs), (ins bdaddr12only:$dest, bdaddr12only:$src,
328 [(z_mvc bdaddr12only:$dest, bdaddr12only:$src,
329 imm32len8:$length)]>;
331 defm LoadStore8_32 : MVCLoadStore<anyextloadi8, truncstorei8, i32,
333 defm LoadStore16_32 : MVCLoadStore<anyextloadi16, truncstorei16, i32,
335 defm LoadStore32_32 : MVCLoadStore<load, store, i32, MVCWrapper, 4>;
337 defm LoadStore8 : MVCLoadStore<anyextloadi8, truncstorei8, i64,
339 defm LoadStore16 : MVCLoadStore<anyextloadi16, truncstorei16, i64,
341 defm LoadStore32 : MVCLoadStore<anyextloadi32, truncstorei32, i64,
343 defm LoadStore64 : MVCLoadStore<load, store, i64, MVCWrapper, 8>;
345 //===----------------------------------------------------------------------===//
347 //===----------------------------------------------------------------------===//
349 // 32-bit extensions from registers.
350 let neverHasSideEffects = 1 in {
351 def LBR : UnaryRRE<"lb", 0xB926, sext8, GR32, GR32>;
352 def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
355 // 64-bit extensions from registers.
356 let neverHasSideEffects = 1 in {
357 def LGBR : UnaryRRE<"lgb", 0xB906, sext8, GR64, GR64>;
358 def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
359 def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
362 // Match 32-to-64-bit sign extensions in which the source is already
363 // in a 64-bit register.
364 def : Pat<(sext_inreg GR64:$src, i32),
365 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
367 // 32-bit extensions from memory.
368 def LB : UnaryRXY<"lb", 0xE376, sextloadi8, GR32, 1>;
369 defm LH : UnaryRXPair<"lh", 0x48, 0xE378, sextloadi16, GR32, 2>;
370 def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_sextloadi16, GR32>;
372 // 64-bit extensions from memory.
373 def LGB : UnaryRXY<"lgb", 0xE377, sextloadi8, GR64, 1>;
374 def LGH : UnaryRXY<"lgh", 0xE315, sextloadi16, GR64, 2>;
375 def LGF : UnaryRXY<"lgf", 0xE314, sextloadi32, GR64, 4>;
376 def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_sextloadi16, GR64>;
377 def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_sextloadi32, GR64>;
379 // If the sign of a load-extend operation doesn't matter, use the signed ones.
380 // There's not really much to choose between the sign and zero extensions,
381 // but LH is more compact than LLH for small offsets.
382 def : Pat<(i32 (extloadi8 bdxaddr20only:$src)), (LB bdxaddr20only:$src)>;
383 def : Pat<(i32 (extloadi16 bdxaddr12pair:$src)), (LH bdxaddr12pair:$src)>;
384 def : Pat<(i32 (extloadi16 bdxaddr20pair:$src)), (LHY bdxaddr20pair:$src)>;
386 def : Pat<(i64 (extloadi8 bdxaddr20only:$src)), (LGB bdxaddr20only:$src)>;
387 def : Pat<(i64 (extloadi16 bdxaddr20only:$src)), (LGH bdxaddr20only:$src)>;
388 def : Pat<(i64 (extloadi32 bdxaddr20only:$src)), (LGF bdxaddr20only:$src)>;
390 // We want PC-relative addresses to be tried ahead of BD and BDX addresses.
391 // However, BDXs have two extra operands and are therefore 6 units more
393 let AddedComplexity = 7 in {
394 def : Pat<(i32 (extloadi16 pcrel32:$src)), (LHRL pcrel32:$src)>;
395 def : Pat<(i64 (extloadi16 pcrel32:$src)), (LGHRL pcrel32:$src)>;
398 //===----------------------------------------------------------------------===//
400 //===----------------------------------------------------------------------===//
402 // 32-bit extensions from registers.
403 let neverHasSideEffects = 1 in {
404 def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>;
405 def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
408 // 64-bit extensions from registers.
409 let neverHasSideEffects = 1 in {
410 def LLGCR : UnaryRRE<"llgc", 0xB984, zext8, GR64, GR64>;
411 def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
412 def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
415 // Match 32-to-64-bit zero extensions in which the source is already
416 // in a 64-bit register.
417 def : Pat<(and GR64:$src, 0xffffffff),
418 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
420 // 32-bit extensions from memory.
421 def LLC : UnaryRXY<"llc", 0xE394, zextloadi8, GR32, 1>;
422 def LLH : UnaryRXY<"llh", 0xE395, zextloadi16, GR32, 2>;
423 def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_zextloadi16, GR32>;
425 // 64-bit extensions from memory.
426 def LLGC : UnaryRXY<"llgc", 0xE390, zextloadi8, GR64, 1>;
427 def LLGH : UnaryRXY<"llgh", 0xE391, zextloadi16, GR64, 2>;
428 def LLGF : UnaryRXY<"llgf", 0xE316, zextloadi32, GR64, 4>;
429 def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_zextloadi16, GR64>;
430 def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_zextloadi32, GR64>;
432 //===----------------------------------------------------------------------===//
434 //===----------------------------------------------------------------------===//
436 // Truncations of 64-bit registers to 32-bit registers.
437 def : Pat<(i32 (trunc GR64:$src)),
438 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
440 // Truncations of 32-bit registers to memory.
441 let isCodeGenOnly = 1 in {
442 defm STC32 : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
443 defm STH32 : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
444 def STHRL32 : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
447 // Truncations of 64-bit registers to memory.
448 defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR64, 1>;
449 defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR64, 2>;
450 def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR64>;
451 defm ST : StoreRXPair<"st", 0x50, 0xE350, truncstorei32, GR64, 4>;
452 def STRL : StoreRILPC<"strl", 0xC4F, aligned_truncstorei32, GR64>;
454 //===----------------------------------------------------------------------===//
455 // Multi-register moves
456 //===----------------------------------------------------------------------===//
458 // Multi-register loads.
459 def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
461 // Multi-register stores.
462 def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
464 //===----------------------------------------------------------------------===//
466 //===----------------------------------------------------------------------===//
468 // Byte-swapping register moves.
469 let neverHasSideEffects = 1 in {
470 def LRVR : UnaryRRE<"lrv", 0xB91F, bswap, GR32, GR32>;
471 def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
474 // Byte-swapping loads. Unlike normal loads, these instructions are
475 // allowed to access storage more than once.
476 def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>;
477 def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>;
479 // Likewise byte-swapping stores.
480 def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>;
481 def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>,
484 //===----------------------------------------------------------------------===//
485 // Load address instructions
486 //===----------------------------------------------------------------------===//
488 // Load BDX-style addresses.
489 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
491 let DispSize = "12" in
492 def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
494 [(set GR64:$R1, laaddr12pair:$XBD2)]>;
495 let DispSize = "20" in
496 def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
498 [(set GR64:$R1, laaddr20pair:$XBD2)]>;
501 // Load a PC-relative address. There's no version of this instruction
502 // with a 16-bit offset, so there's no relaxation.
503 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
504 isReMaterializable = 1 in {
505 def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
507 [(set GR64:$R1, pcrel32:$I2)]>;
510 //===----------------------------------------------------------------------===//
512 //===----------------------------------------------------------------------===//
515 def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>;
516 def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
517 def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>;
519 defm : SXU<ineg, LCGFR>;
521 //===----------------------------------------------------------------------===//
523 //===----------------------------------------------------------------------===//
525 let isCodeGenOnly = 1 in
526 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, zextloadi8, 1>;
527 defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, zextloadi8, 1>;
529 defm : InsertMem<"inserti8", IC32, GR32, zextloadi8, bdxaddr12pair>;
530 defm : InsertMem<"inserti8", IC32Y, GR32, zextloadi8, bdxaddr20pair>;
532 defm : InsertMem<"inserti8", IC, GR64, zextloadi8, bdxaddr12pair>;
533 defm : InsertMem<"inserti8", ICY, GR64, zextloadi8, bdxaddr20pair>;
535 // Insertions of a 16-bit immediate, leaving other bits unaffected.
536 // We don't have or_as_insert equivalents of these operations because
537 // OI is available instead.
538 let isCodeGenOnly = 1 in {
539 def IILL32 : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
540 def IILH32 : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
542 def IILL : BinaryRI<"iill", 0xA53, insertll, GR64, imm64ll16>;
543 def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR64, imm64lh16>;
544 def IIHL : BinaryRI<"iihl", 0xA51, inserthl, GR64, imm64hl16>;
545 def IIHH : BinaryRI<"iihh", 0xA50, inserthh, GR64, imm64hh16>;
547 // ...likewise for 32-bit immediates. For GR32s this is a general
548 // full-width move. (We use IILF rather than something like LLILF
549 // for 32-bit moves because IILF leaves the upper 32 bits of the
551 let isCodeGenOnly = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
552 isReMaterializable = 1 in {
553 def IILF32 : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
555 def IILF : BinaryRIL<"iilf", 0xC09, insertlf, GR64, imm64lf32>;
556 def IIHF : BinaryRIL<"iihf", 0xC08, inserthf, GR64, imm64hf32>;
558 // An alternative model of inserthf, with the first operand being
559 // a zero-extended value.
560 def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
561 (IIHF (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit),
564 //===----------------------------------------------------------------------===//
566 //===----------------------------------------------------------------------===//
570 // Addition of a register.
571 let isCommutable = 1 in {
572 defm AR : BinaryRRAndK<"a", 0x1A, 0xB9F8, add, GR32, GR32>;
573 defm AGR : BinaryRREAndK<"ag", 0xB908, 0xB9E8, add, GR64, GR64>;
575 def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
577 // Addition of signed 16-bit immediates.
578 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, add, GR32, imm32sx16>;
579 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, add, GR64, imm64sx16>;
581 // Addition of signed 32-bit immediates.
582 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>;
583 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
585 // Addition of memory.
586 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, sextloadi16, 2>;
587 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>;
588 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, sextloadi32, 4>;
589 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>;
591 // Addition to memory.
592 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>;
593 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
595 defm : SXB<add, GR64, AGFR>;
597 // Addition producing a carry.
599 // Addition of a register.
600 let isCommutable = 1 in {
601 defm ALR : BinaryRRAndK<"al", 0x1E, 0xB9FA, addc, GR32, GR32>;
602 defm ALGR : BinaryRREAndK<"alg", 0xB90A, 0xB9EA, addc, GR64, GR64>;
604 def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
606 // Addition of signed 16-bit immediates.
607 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, addc, GR32, imm32sx16>,
608 Requires<[FeatureDistinctOps]>;
609 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, addc, GR64, imm64sx16>,
610 Requires<[FeatureDistinctOps]>;
612 // Addition of unsigned 32-bit immediates.
613 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>;
614 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
616 // Addition of memory.
617 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>;
618 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, zextloadi32, 4>;
619 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>;
621 defm : ZXB<addc, GR64, ALGFR>;
623 // Addition producing and using a carry.
624 let Defs = [CC], Uses = [CC] in {
625 // Addition of a register.
626 def ALCR : BinaryRRE<"alc", 0xB998, adde, GR32, GR32>;
627 def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>;
629 // Addition of memory.
630 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>;
631 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>;
634 //===----------------------------------------------------------------------===//
636 //===----------------------------------------------------------------------===//
638 // Plain substraction. Although immediate forms exist, we use the
639 // add-immediate instruction instead.
641 // Subtraction of a register.
642 defm SR : BinaryRRAndK<"s", 0x1B, 0xB9F9, sub, GR32, GR32>;
643 def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
644 defm SGR : BinaryRREAndK<"sg", 0xB909, 0xB9E9, sub, GR64, GR64>;
646 // Subtraction of memory.
647 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, sextloadi16, 2>;
648 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>;
649 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, sextloadi32, 4>;
650 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>;
652 defm : SXB<sub, GR64, SGFR>;
654 // Subtraction producing a carry.
656 // Subtraction of a register.
657 defm SLR : BinaryRRAndK<"sl", 0x1F, 0xB9FB, subc, GR32, GR32>;
658 def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
659 defm SLGR : BinaryRREAndK<"slg", 0xB90B, 0xB9EB, subc, GR64, GR64>;
661 // Subtraction of unsigned 32-bit immediates. These don't match
662 // subc because we prefer addc for constants.
663 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>;
664 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
666 // Subtraction of memory.
667 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
668 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, zextloadi32, 4>;
669 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>;
671 defm : ZXB<subc, GR64, SLGFR>;
673 // Subtraction producing and using a carry.
674 let Defs = [CC], Uses = [CC] in {
675 // Subtraction of a register.
676 def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>;
677 def SLGBR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
679 // Subtraction of memory.
680 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>;
681 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
684 //===----------------------------------------------------------------------===//
686 //===----------------------------------------------------------------------===//
689 // ANDs of a register.
690 let isCommutable = 1 in {
691 defm NR : BinaryRRAndK<"n", 0x14, 0xB9F4, and, GR32, GR32>;
692 defm NGR : BinaryRREAndK<"ng", 0xB980, 0xB9E4, and, GR64, GR64>;
695 // ANDs of a 16-bit immediate, leaving other bits unaffected.
696 let isCodeGenOnly = 1 in {
697 def NILL32 : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
698 def NILH32 : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
700 def NILL : BinaryRI<"nill", 0xA57, and, GR64, imm64ll16c>;
701 def NILH : BinaryRI<"nilh", 0xA56, and, GR64, imm64lh16c>;
702 def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>;
703 def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>;
705 // ANDs of a 32-bit immediate, leaving other bits unaffected.
706 let isCodeGenOnly = 1 in
707 def NILF32 : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
708 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR64, imm64lf32c>;
709 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>;
712 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>;
713 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>;
716 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>;
718 defm : RMWIByte<and, bdaddr12pair, NI>;
719 defm : RMWIByte<and, bdaddr20pair, NIY>;
721 //===----------------------------------------------------------------------===//
723 //===----------------------------------------------------------------------===//
726 // ORs of a register.
727 let isCommutable = 1 in {
728 defm OR : BinaryRRAndK<"o", 0x16, 0xB9F6, or, GR32, GR32>;
729 defm OGR : BinaryRREAndK<"og", 0xB981, 0xB9E6, or, GR64, GR64>;
732 // ORs of a 16-bit immediate, leaving other bits unaffected.
733 let isCodeGenOnly = 1 in {
734 def OILL32 : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
735 def OILH32 : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
737 def OILL : BinaryRI<"oill", 0xA5B, or, GR64, imm64ll16>;
738 def OILH : BinaryRI<"oilh", 0xA5A, or, GR64, imm64lh16>;
739 def OIHL : BinaryRI<"oihl", 0xA59, or, GR64, imm64hl16>;
740 def OIHH : BinaryRI<"oihh", 0xA58, or, GR64, imm64hh16>;
742 // ORs of a 32-bit immediate, leaving other bits unaffected.
743 let isCodeGenOnly = 1 in
744 def OILF32 : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
745 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR64, imm64lf32>;
746 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GR64, imm64hf32>;
749 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>;
750 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>;
753 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>;
755 defm : RMWIByte<or, bdaddr12pair, OI>;
756 defm : RMWIByte<or, bdaddr20pair, OIY>;
758 //===----------------------------------------------------------------------===//
760 //===----------------------------------------------------------------------===//
763 // XORs of a register.
764 let isCommutable = 1 in {
765 defm XR : BinaryRRAndK<"x", 0x17, 0xB9F7, xor, GR32, GR32>;
766 defm XGR : BinaryRREAndK<"xg", 0xB982, 0xB9E7, xor, GR64, GR64>;
769 // XORs of a 32-bit immediate, leaving other bits unaffected.
770 let isCodeGenOnly = 1 in
771 def XILF32 : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
772 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR64, imm64lf32>;
773 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>;
776 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>;
777 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>;
780 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>;
782 defm : RMWIByte<xor, bdaddr12pair, XI>;
783 defm : RMWIByte<xor, bdaddr20pair, XIY>;
785 //===----------------------------------------------------------------------===//
787 //===----------------------------------------------------------------------===//
789 // Multiplication of a register.
790 let isCommutable = 1 in {
791 def MSR : BinaryRRE<"ms", 0xB252, mul, GR32, GR32>;
792 def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>;
794 def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>;
795 defm : SXB<mul, GR64, MSGFR>;
797 // Multiplication of a signed 16-bit immediate.
798 def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>;
799 def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
801 // Multiplication of a signed 32-bit immediate.
802 def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>;
803 def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
805 // Multiplication of memory.
806 defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, sextloadi16, 2>;
807 defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
808 def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, sextloadi32, 4>;
809 def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>;
811 // Multiplication of a register, producing two results.
812 def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>;
814 // Multiplication of memory, producing two results.
815 def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
817 //===----------------------------------------------------------------------===//
818 // Division and remainder
819 //===----------------------------------------------------------------------===//
821 // Division and remainder, from registers.
822 def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>;
823 def DSGR : BinaryRRE<"dsg", 0xB90D, z_sdivrem64, GR128, GR64>;
824 def DLR : BinaryRRE<"dl", 0xB997, z_udivrem32, GR128, GR32>;
825 def DLGR : BinaryRRE<"dlg", 0xB987, z_udivrem64, GR128, GR64>;
827 // Division and remainder, from memory.
828 def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
829 def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load, 8>;
830 def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load, 4>;
831 def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>;
833 //===----------------------------------------------------------------------===//
835 //===----------------------------------------------------------------------===//
838 let neverHasSideEffects = 1 in {
839 defm SLL : ShiftRSAndK<"sll", 0x89, 0xEBDF, shl, GR32>;
840 def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64>;
843 // Logical shift right.
844 let neverHasSideEffects = 1 in {
845 defm SRL : ShiftRSAndK<"srl", 0x88, 0xEBDE, srl, GR32>;
846 def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64>;
849 // Arithmetic shift right.
851 defm SRA : ShiftRSAndK<"sra", 0x8A, 0xEBDC, sra, GR32>;
852 def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64>;
856 let neverHasSideEffects = 1 in {
857 def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32>;
858 def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64>;
861 // Rotate second operand left and inserted selected bits into first operand.
862 // These can act like 32-bit operands provided that the constant start and
863 // end bits (operands 2 and 3) are in the range [32, 64)
865 let isCodeGenOnly = 1 in
866 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
867 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
870 // Forms of RISBG that only affect one word of the destination register.
871 // They do not set CC.
872 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GR64, GR64>,
873 Requires<[FeatureHighWord]>;
874 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR64, GR64>,
875 Requires<[FeatureHighWord]>;
877 // Rotate second operand left and perform a logical operation with selected
878 // bits of the first operand.
880 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>;
881 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>;
882 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>;
885 //===----------------------------------------------------------------------===//
887 //===----------------------------------------------------------------------===//
889 // Signed comparisons.
891 // Comparison with a register.
892 def CR : CompareRR <"c", 0x19, z_cmp, GR32, GR32>;
893 def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>;
894 def CGR : CompareRRE<"cg", 0xB920, z_cmp, GR64, GR64>;
896 // Comparison with a signed 16-bit immediate.
897 def CHI : CompareRI<"chi", 0xA7E, z_cmp, GR32, imm32sx16>;
898 def CGHI : CompareRI<"cghi", 0xA7F, z_cmp, GR64, imm64sx16>;
900 // Comparison with a signed 32-bit immediate.
901 def CFI : CompareRIL<"cfi", 0xC2D, z_cmp, GR32, simm32>;
902 def CGFI : CompareRIL<"cgfi", 0xC2C, z_cmp, GR64, imm64sx32>;
904 // Comparison with memory.
905 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_cmp, GR32, sextloadi16, 2>;
906 defm C : CompareRXPair<"c", 0x59, 0xE359, z_cmp, GR32, load, 4>;
907 def CGH : CompareRXY<"cgh", 0xE334, z_cmp, GR64, sextloadi16, 2>;
908 def CGF : CompareRXY<"cgf", 0xE330, z_cmp, GR64, sextloadi32, 4>;
909 def CG : CompareRXY<"cg", 0xE320, z_cmp, GR64, load, 8>;
910 def CHRL : CompareRILPC<"chrl", 0xC65, z_cmp, GR32, aligned_sextloadi16>;
911 def CRL : CompareRILPC<"crl", 0xC6D, z_cmp, GR32, aligned_load>;
912 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_cmp, GR64, aligned_sextloadi16>;
913 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_cmp, GR64, aligned_sextloadi32>;
914 def CGRL : CompareRILPC<"cgrl", 0xC68, z_cmp, GR64, aligned_load>;
916 // Comparison between memory and a signed 16-bit immediate.
917 def CHHSI : CompareSIL<"chhsi", 0xE554, z_cmp, sextloadi16, imm32sx16>;
918 def CHSI : CompareSIL<"chsi", 0xE55C, z_cmp, load, imm32sx16>;
919 def CGHSI : CompareSIL<"cghsi", 0xE558, z_cmp, load, imm64sx16>;
921 defm : SXB<z_cmp, GR64, CGFR>;
923 // Unsigned comparisons.
925 // Comparison with a register.
926 def CLR : CompareRR <"cl", 0x15, z_ucmp, GR32, GR32>;
927 def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>;
928 def CLGR : CompareRRE<"clg", 0xB921, z_ucmp, GR64, GR64>;
930 // Comparison with a signed 32-bit immediate.
931 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>;
932 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
934 // Comparison with memory.
935 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>;
936 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, zextloadi32, 4>;
937 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>;
938 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32,
939 aligned_zextloadi16>;
940 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32,
942 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
943 aligned_zextloadi16>;
944 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
945 aligned_zextloadi32>;
946 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64,
949 // Comparison between memory and an unsigned 8-bit immediate.
950 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, zextloadi8, imm32zx8>;
952 // Comparison between memory and an unsigned 16-bit immediate.
953 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, zextloadi16, imm32zx16>;
954 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
955 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
957 defm : ZXB<z_ucmp, GR64, CLGFR>;
959 //===----------------------------------------------------------------------===//
961 //===----------------------------------------------------------------------===//
963 def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>;
964 def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>;
965 def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>;
967 def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
968 def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
969 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>;
970 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
971 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
972 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>;
973 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
974 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
976 def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
977 def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>;
978 def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>;
980 def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
981 def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
982 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>;
983 def ATOMIC_LOAD_NILL32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>;
984 def ATOMIC_LOAD_NILH32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>;
985 def ATOMIC_LOAD_NILF32 : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
986 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>;
987 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>;
988 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>;
989 def ATOMIC_LOAD_NIHL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>;
990 def ATOMIC_LOAD_NIHH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>;
991 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>;
992 def ATOMIC_LOAD_NIHF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>;
994 def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
995 def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
996 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>;
997 def ATOMIC_LOAD_OILL32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
998 def ATOMIC_LOAD_OILH32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
999 def ATOMIC_LOAD_OILF32 : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
1000 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>;
1001 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
1002 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
1003 def ATOMIC_LOAD_OIHL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
1004 def ATOMIC_LOAD_OIHH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
1005 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
1006 def ATOMIC_LOAD_OIHF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
1008 def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
1009 def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
1010 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>;
1011 def ATOMIC_LOAD_XILF32 : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
1012 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>;
1013 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
1014 def ATOMIC_LOAD_XIHF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
1016 def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
1017 def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
1019 def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>;
1020 def ATOMIC_LOAD_NILL32i : AtomicLoadBinaryImm32<atomic_load_nand_32,
1022 def ATOMIC_LOAD_NILH32i : AtomicLoadBinaryImm32<atomic_load_nand_32,
1024 def ATOMIC_LOAD_NILF32i : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
1025 def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>;
1026 def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm64<atomic_load_nand_64,
1028 def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm64<atomic_load_nand_64,
1030 def ATOMIC_LOAD_NIHLi : AtomicLoadBinaryImm64<atomic_load_nand_64,
1032 def ATOMIC_LOAD_NIHHi : AtomicLoadBinaryImm64<atomic_load_nand_64,
1034 def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm64<atomic_load_nand_64,
1036 def ATOMIC_LOAD_NIHFi : AtomicLoadBinaryImm64<atomic_load_nand_64,
1039 def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
1040 def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>;
1041 def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>;
1043 def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
1044 def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>;
1045 def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>;
1047 def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
1048 def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
1049 def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
1051 def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
1052 def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
1053 def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
1055 def ATOMIC_CMP_SWAPW
1056 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1057 ADDR32:$bitshift, ADDR32:$negbitshift,
1060 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
1061 ADDR32:$bitshift, ADDR32:$negbitshift,
1062 uimm32:$bitsize))]> {
1066 let usesCustomInserter = 1;
1069 let Defs = [CC] in {
1070 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
1071 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
1074 //===----------------------------------------------------------------------===//
1075 // Miscellaneous Instructions.
1076 //===----------------------------------------------------------------------===//
1078 // Read a 32-bit access register into a GR32. As with all GR32 operations,
1079 // the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
1080 // when a 64-bit address is stored in a pair of access registers.
1081 def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
1083 [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
1085 // Find leftmost one, AKA count leading zeros. The instruction actually
1086 // returns a pair of GR64s, the first giving the number of leading zeros
1087 // and the second giving a copy of the source with the leftmost one bit
1088 // cleared. We only use the first result here.
1089 let Defs = [CC] in {
1090 def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>;
1092 def : Pat<(ctlz GR64:$src),
1093 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_high)>;
1095 // Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
1096 def : Pat<(i64 (anyext GR32:$src)),
1097 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
1099 // There are no 32-bit equivalents of LLILL and LLILH, so use a full
1100 // 64-bit move followed by a subreg. This preserves the invariant that
1101 // all GR32 operations only modify the low 32 bits.
1102 def : Pat<(i32 imm32ll16:$src),
1103 (EXTRACT_SUBREG (LLILL (LL16 imm:$src)), subreg_32bit)>;
1104 def : Pat<(i32 imm32lh16:$src),
1105 (EXTRACT_SUBREG (LLILH (LH16 imm:$src)), subreg_32bit)>;
1107 // Extend GR32s and GR64s to GR128s.
1108 let usesCustomInserter = 1 in {
1109 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1110 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
1111 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1114 //===----------------------------------------------------------------------===//
1116 //===----------------------------------------------------------------------===//
1118 // Use AL* for GR64 additions of unsigned 32-bit values.
1119 defm : ZXB<add, GR64, ALGFR>;
1120 def : Pat<(add GR64:$src1, imm64zx32:$src2),
1121 (ALGFI GR64:$src1, imm64zx32:$src2)>;
1122 def : Pat<(add GR64:$src1, (zextloadi32 bdxaddr20only:$addr)),
1123 (ALGF GR64:$src1, bdxaddr20only:$addr)>;
1125 // Use SL* for GR64 subtractions of unsigned 32-bit values.
1126 defm : ZXB<sub, GR64, SLGFR>;
1127 def : Pat<(add GR64:$src1, imm64zx32n:$src2),
1128 (SLGFI GR64:$src1, imm64zx32n:$src2)>;
1129 def : Pat<(sub GR64:$src1, (zextloadi32 bdxaddr20only:$addr)),
1130 (SLGF GR64:$src1, bdxaddr20only:$addr)>;
1132 // Optimize sign-extended 1/0 selects to -1/0 selects. This is important
1133 // for vector legalization.
1134 def : Pat<(sra (shl (i32 (z_select_ccmask 1, 0, imm:$cc)), (i32 31)), (i32 31)),
1135 (Select32 (LHI -1), (LHI 0), imm:$cc)>;
1136 def : Pat<(sra (shl (i64 (anyext (i32 (z_select_ccmask 1, 0, imm:$cc)))),
1139 (Select64 (LGHI -1), (LGHI 0), imm:$cc)>;