1 //==- SystemZInstrVector.td - SystemZ Vector instructions ------*- tblgen-*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 let Predicates = [FeatureVector] in {
16 def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>;
17 def VLR32 : UnaryAliasVRR<null_frag, v32eb, v32eb>;
18 def VLR64 : UnaryAliasVRR<null_frag, v64db, v64db>;
20 // Load GR from VR element.
21 def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>;
22 def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>;
23 def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>;
24 def VLGVG : BinaryVRSc<"vlgvg", 0xE721, z_vector_extract, v128g, 3>;
26 // Load VR element from GR.
27 def VLVGB : TernaryVRSb<"vlvgb", 0xE722, z_vector_insert,
28 v128b, v128b, GR32, 0>;
29 def VLVGH : TernaryVRSb<"vlvgh", 0xE722, z_vector_insert,
30 v128h, v128h, GR32, 1>;
31 def VLVGF : TernaryVRSb<"vlvgf", 0xE722, z_vector_insert,
32 v128f, v128f, GR32, 2>;
33 def VLVGG : TernaryVRSb<"vlvgg", 0xE722, z_vector_insert,
34 v128g, v128g, GR64, 3>;
36 // Load VR from GRs disjoint.
37 def VLVGP : BinaryVRRf<"vlvgp", 0xE762, z_join_dwords, v128g>;
38 def VLVGP32 : BinaryAliasVRRf<GR32>;
41 // Extractions always assign to the full GR64, even if the element would
42 // fit in the lower 32 bits. Sub-i64 extracts therefore need to take a
43 // subreg of the result.
44 class VectorExtractSubreg<ValueType type, Instruction insn>
45 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)),
46 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>;
48 def : VectorExtractSubreg<v16i8, VLGVB>;
49 def : VectorExtractSubreg<v8i16, VLGVH>;
50 def : VectorExtractSubreg<v4i32, VLGVF>;
52 //===----------------------------------------------------------------------===//
53 // Immediate instructions
54 //===----------------------------------------------------------------------===//
56 let Predicates = [FeatureVector] in {
57 // Generate byte mask.
58 def VZERO : InherentVRIa<"vzero", 0xE744, 0>;
59 def VONE : InherentVRIa<"vone", 0xE744, 0xffff>;
60 def VGBM : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16>;
63 def VGMB : BinaryVRIb<"vgmb", 0xE746, z_rotate_mask, v128b, 0>;
64 def VGMH : BinaryVRIb<"vgmh", 0xE746, z_rotate_mask, v128h, 1>;
65 def VGMF : BinaryVRIb<"vgmf", 0xE746, z_rotate_mask, v128f, 2>;
66 def VGMG : BinaryVRIb<"vgmg", 0xE746, z_rotate_mask, v128g, 3>;
68 // Load element immediate.
70 // We want these instructions to be used ahead of VLVG* where possible.
71 // However, VLVG* takes a variable BD-format index whereas VLEI takes
72 // a plain immediate index. This means that VLVG* has an extra "base"
73 // register operand and is 3 units more complex. Bumping the complexity
74 // of the VLEI* instructions by 4 means that they are strictly better
75 // than VLVG* in cases where both forms match.
76 let AddedComplexity = 4 in {
77 def VLEIB : TernaryVRIa<"vleib", 0xE740, z_vector_insert,
78 v128b, v128b, imm32sx16trunc, imm32zx4>;
79 def VLEIH : TernaryVRIa<"vleih", 0xE741, z_vector_insert,
80 v128h, v128h, imm32sx16trunc, imm32zx3>;
81 def VLEIF : TernaryVRIa<"vleif", 0xE743, z_vector_insert,
82 v128f, v128f, imm32sx16, imm32zx2>;
83 def VLEIG : TernaryVRIa<"vleig", 0xE742, z_vector_insert,
84 v128g, v128g, imm64sx16, imm32zx1>;
87 // Replicate immediate.
88 def VREPIB : UnaryVRIa<"vrepib", 0xE745, z_replicate, v128b, imm32sx16, 0>;
89 def VREPIH : UnaryVRIa<"vrepih", 0xE745, z_replicate, v128h, imm32sx16, 1>;
90 def VREPIF : UnaryVRIa<"vrepif", 0xE745, z_replicate, v128f, imm32sx16, 2>;
91 def VREPIG : UnaryVRIa<"vrepig", 0xE745, z_replicate, v128g, imm32sx16, 3>;
94 //===----------------------------------------------------------------------===//
96 //===----------------------------------------------------------------------===//
98 let Predicates = [FeatureVector] in {
100 def VL : UnaryVRX<"vl", 0xE706, null_frag, v128any, 16>;
102 // Load to block boundary. The number of loaded bytes is only known
104 def VLBB : BinaryVRX<"vlbb", 0xE707, null_frag, v128any, 0>;
106 // Load count to block boundary.
108 def LCBB : InstRXE<0xE727, (outs GR32:$R1),
109 (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
110 "lcbb\t$R1, $XBD2, $M3", []>;
112 // Load with length. The number of loaded bytes is only known at run time.
113 def VLL : BinaryVRSb<"vll", 0xE737, null_frag, 0>;
116 def VLM : LoadMultipleVRSa<"vlm", 0xE736>;
118 // Load and replicate
119 def VLREPB : UnaryVRX<"vlrepb", 0xE705, z_replicate_loadi8, v128b, 1, 0>;
120 def VLREPH : UnaryVRX<"vlreph", 0xE705, z_replicate_loadi16, v128h, 2, 1>;
121 def VLREPF : UnaryVRX<"vlrepf", 0xE705, z_replicate_loadi32, v128f, 4, 2>;
122 def VLREPG : UnaryVRX<"vlrepg", 0xE705, z_replicate_loadi64, v128g, 8, 3>;
123 def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)),
124 (VLREPF bdxaddr12only:$addr)>;
125 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)),
126 (VLREPG bdxaddr12only:$addr)>;
128 // Use VLREP to load subvectors. These patterns use "12pair" because
129 // LEY and LDY offer full 20-bit displacement fields. It's often better
130 // to use those instructions rather than force a 20-bit displacement
131 // into a GPR temporary.
132 def VL32 : UnaryAliasVRX<load, v32eb, bdxaddr12pair>;
133 def VL64 : UnaryAliasVRX<load, v64db, bdxaddr12pair>;
135 // Load logical element and zero.
136 def VLLEZB : UnaryVRX<"vllezb", 0xE704, z_vllezi8, v128b, 1, 0>;
137 def VLLEZH : UnaryVRX<"vllezh", 0xE704, z_vllezi16, v128h, 2, 1>;
138 def VLLEZF : UnaryVRX<"vllezf", 0xE704, z_vllezi32, v128f, 4, 2>;
139 def VLLEZG : UnaryVRX<"vllezg", 0xE704, z_vllezi64, v128g, 8, 3>;
140 def : Pat<(v4f32 (z_vllezf32 bdxaddr12only:$addr)),
141 (VLLEZF bdxaddr12only:$addr)>;
142 def : Pat<(v2f64 (z_vllezf64 bdxaddr12only:$addr)),
143 (VLLEZG bdxaddr12only:$addr)>;
146 def VLEB : TernaryVRX<"vleb", 0xE700, z_vlei8, v128b, v128b, 1, imm32zx4>;
147 def VLEH : TernaryVRX<"vleh", 0xE701, z_vlei16, v128h, v128h, 2, imm32zx3>;
148 def VLEF : TernaryVRX<"vlef", 0xE703, z_vlei32, v128f, v128f, 4, imm32zx2>;
149 def VLEG : TernaryVRX<"vleg", 0xE702, z_vlei64, v128g, v128g, 8, imm32zx1>;
150 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index),
151 (VLEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>;
152 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index),
153 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;
156 def VGEF : TernaryVRV<"vgef", 0xE713, 4, imm32zx2>;
157 def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>;
160 // Use replicating loads if we're inserting a single element into an
161 // undefined vector. This avoids a false dependency on the previous
162 // register contents.
163 multiclass ReplicatePeephole<Instruction vlrep, ValueType vectype,
164 SDPatternOperator load, ValueType scalartype> {
165 def : Pat<(vectype (z_vector_insert
166 (undef), (scalartype (load bdxaddr12only:$addr)), 0)),
167 (vlrep bdxaddr12only:$addr)>;
168 def : Pat<(vectype (scalar_to_vector
169 (scalartype (load bdxaddr12only:$addr)))),
170 (vlrep bdxaddr12only:$addr)>;
172 defm : ReplicatePeephole<VLREPB, v16i8, anyextloadi8, i32>;
173 defm : ReplicatePeephole<VLREPH, v8i16, anyextloadi16, i32>;
174 defm : ReplicatePeephole<VLREPF, v4i32, load, i32>;
175 defm : ReplicatePeephole<VLREPG, v2i64, load, i64>;
176 defm : ReplicatePeephole<VLREPF, v4f32, load, f32>;
177 defm : ReplicatePeephole<VLREPG, v2f64, load, f64>;
179 //===----------------------------------------------------------------------===//
181 //===----------------------------------------------------------------------===//
183 let Predicates = [FeatureVector] in {
185 def VST : StoreVRX<"vst", 0xE70E, null_frag, v128any, 16>;
187 // Store with length. The number of stored bytes is only known at run time.
188 def VSTL : StoreLengthVRSb<"vstl", 0xE73F, null_frag, 0>;
191 def VSTM : StoreMultipleVRSa<"vstm", 0xE73E>;
194 def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, z_vstei8, v128b, 1, imm32zx4>;
195 def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, z_vstei16, v128h, 2, imm32zx3>;
196 def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, z_vstei32, v128f, 4, imm32zx2>;
197 def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, z_vstei64, v128g, 8, imm32zx1>;
198 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr,
200 (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>;
201 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr,
203 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;
205 // Use VSTE to store subvectors. These patterns use "12pair" because
206 // STEY and STDY offer full 20-bit displacement fields. It's often better
207 // to use those instructions rather than force a 20-bit displacement
208 // into a GPR temporary.
209 def VST32 : StoreAliasVRX<store, v32eb, bdxaddr12pair>;
210 def VST64 : StoreAliasVRX<store, v64db, bdxaddr12pair>;
213 def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>;
214 def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>;
217 //===----------------------------------------------------------------------===//
218 // Selects and permutes
219 //===----------------------------------------------------------------------===//
221 let Predicates = [FeatureVector] in {
223 def VMRHB : BinaryVRRc<"vmrhb", 0xE761, z_merge_high, v128b, v128b, 0>;
224 def VMRHH : BinaryVRRc<"vmrhh", 0xE761, z_merge_high, v128h, v128h, 1>;
225 def VMRHF : BinaryVRRc<"vmrhf", 0xE761, z_merge_high, v128f, v128f, 2>;
226 def VMRHG : BinaryVRRc<"vmrhg", 0xE761, z_merge_high, v128g, v128g, 3>;
227 def : BinaryRRWithType<VMRHF, VR128, z_merge_high, v4f32>;
228 def : BinaryRRWithType<VMRHG, VR128, z_merge_high, v2f64>;
231 def VMRLB : BinaryVRRc<"vmrlb", 0xE760, z_merge_low, v128b, v128b, 0>;
232 def VMRLH : BinaryVRRc<"vmrlh", 0xE760, z_merge_low, v128h, v128h, 1>;
233 def VMRLF : BinaryVRRc<"vmrlf", 0xE760, z_merge_low, v128f, v128f, 2>;
234 def VMRLG : BinaryVRRc<"vmrlg", 0xE760, z_merge_low, v128g, v128g, 3>;
235 def : BinaryRRWithType<VMRLF, VR128, z_merge_low, v4f32>;
236 def : BinaryRRWithType<VMRLG, VR128, z_merge_low, v2f64>;
239 def VPERM : TernaryVRRe<"vperm", 0xE78C, z_permute, v128b, v128b>;
241 // Permute doubleword immediate.
242 def VPDI : TernaryVRRc<"vpdi", 0xE784, z_permute_dwords, v128g, v128g>;
245 def VREPB : BinaryVRIc<"vrepb", 0xE74D, z_splat, v128b, v128b, 0>;
246 def VREPH : BinaryVRIc<"vreph", 0xE74D, z_splat, v128h, v128h, 1>;
247 def VREPF : BinaryVRIc<"vrepf", 0xE74D, z_splat, v128f, v128f, 2>;
248 def VREPG : BinaryVRIc<"vrepg", 0xE74D, z_splat, v128g, v128g, 3>;
249 def : Pat<(v4f32 (z_splat VR128:$vec, imm32zx16:$index)),
250 (VREPF VR128:$vec, imm32zx16:$index)>;
251 def : Pat<(v2f64 (z_splat VR128:$vec, imm32zx16:$index)),
252 (VREPG VR128:$vec, imm32zx16:$index)>;
255 def VSEL : TernaryVRRe<"vsel", 0xE78D, null_frag, v128any, v128any>;
258 //===----------------------------------------------------------------------===//
259 // Widening and narrowing
260 //===----------------------------------------------------------------------===//
262 let Predicates = [FeatureVector] in {
264 def VPKH : BinaryVRRc<"vpkh", 0xE794, z_pack, v128b, v128h, 1>;
265 def VPKF : BinaryVRRc<"vpkf", 0xE794, z_pack, v128h, v128f, 2>;
266 def VPKG : BinaryVRRc<"vpkg", 0xE794, z_pack, v128f, v128g, 3>;
269 defm VPKSH : BinaryVRRbSPair<"vpksh", 0xE797, null_frag, null_frag,
271 defm VPKSF : BinaryVRRbSPair<"vpksf", 0xE797, null_frag, null_frag,
273 defm VPKSG : BinaryVRRbSPair<"vpksg", 0xE797, null_frag, null_frag,
276 // Pack saturate logical.
277 defm VPKLSH : BinaryVRRbSPair<"vpklsh", 0xE795, null_frag, null_frag,
279 defm VPKLSF : BinaryVRRbSPair<"vpklsf", 0xE795, null_frag, null_frag,
281 defm VPKLSG : BinaryVRRbSPair<"vpklsg", 0xE795, null_frag, null_frag,
284 // Sign-extend to doubleword.
285 def VSEGB : UnaryVRRa<"vsegb", 0xE75F, z_vsei8, v128g, v128g, 0>;
286 def VSEGH : UnaryVRRa<"vsegh", 0xE75F, z_vsei16, v128g, v128g, 1>;
287 def VSEGF : UnaryVRRa<"vsegf", 0xE75F, z_vsei32, v128g, v128g, 2>;
288 def : Pat<(z_vsei8_by_parts (v16i8 VR128:$src)), (VSEGB VR128:$src)>;
289 def : Pat<(z_vsei16_by_parts (v8i16 VR128:$src)), (VSEGH VR128:$src)>;
290 def : Pat<(z_vsei32_by_parts (v4i32 VR128:$src)), (VSEGF VR128:$src)>;
293 def VUPHB : UnaryVRRa<"vuphb", 0xE7D7, null_frag, v128h, v128b, 0>;
294 def VUPHH : UnaryVRRa<"vuphh", 0xE7D7, null_frag, v128f, v128h, 1>;
295 def VUPHF : UnaryVRRa<"vuphf", 0xE7D7, null_frag, v128g, v128f, 2>;
297 // Unpack logical high.
298 def VUPLHB : UnaryVRRa<"vuplhb", 0xE7D5, null_frag, v128h, v128b, 0>;
299 def VUPLHH : UnaryVRRa<"vuplhh", 0xE7D5, null_frag, v128f, v128h, 1>;
300 def VUPLHF : UnaryVRRa<"vuplhf", 0xE7D5, null_frag, v128g, v128f, 2>;
303 def VUPLB : UnaryVRRa<"vuplb", 0xE7D6, null_frag, v128h, v128b, 0>;
304 def VUPLHW : UnaryVRRa<"vuplhw", 0xE7D6, null_frag, v128f, v128h, 1>;
305 def VUPLF : UnaryVRRa<"vuplf", 0xE7D6, null_frag, v128g, v128f, 2>;
307 // Unpack logical low.
308 def VUPLLB : UnaryVRRa<"vupllb", 0xE7D4, null_frag, v128h, v128b, 0>;
309 def VUPLLH : UnaryVRRa<"vupllh", 0xE7D4, null_frag, v128f, v128h, 1>;
310 def VUPLLF : UnaryVRRa<"vupllf", 0xE7D4, null_frag, v128g, v128f, 2>;
313 //===----------------------------------------------------------------------===//
314 // Instantiating generic operations for specific types.
315 //===----------------------------------------------------------------------===//
317 multiclass GenericVectorOps<ValueType type, ValueType inttype> {
318 let Predicates = [FeatureVector] in {
319 def : Pat<(type (load bdxaddr12only:$addr)),
320 (VL bdxaddr12only:$addr)>;
321 def : Pat<(store (type VR128:$src), bdxaddr12only:$addr),
322 (VST VR128:$src, bdxaddr12only:$addr)>;
323 def : Pat<(type (vselect (inttype VR128:$x), VR128:$y, VR128:$z)),
324 (VSEL VR128:$y, VR128:$z, VR128:$x)>;
325 def : Pat<(type (vselect (inttype (z_vnot VR128:$x)), VR128:$y, VR128:$z)),
326 (VSEL VR128:$z, VR128:$y, VR128:$x)>;
330 defm : GenericVectorOps<v16i8, v16i8>;
331 defm : GenericVectorOps<v8i16, v8i16>;
332 defm : GenericVectorOps<v4i32, v4i32>;
333 defm : GenericVectorOps<v2i64, v2i64>;
334 defm : GenericVectorOps<v4f32, v4i32>;
335 defm : GenericVectorOps<v2f64, v2i64>;
337 //===----------------------------------------------------------------------===//
338 // Integer arithmetic
339 //===----------------------------------------------------------------------===//
341 let Predicates = [FeatureVector] in {
343 def VAB : BinaryVRRc<"vab", 0xE7F3, add, v128b, v128b, 0>;
344 def VAH : BinaryVRRc<"vah", 0xE7F3, add, v128h, v128h, 1>;
345 def VAF : BinaryVRRc<"vaf", 0xE7F3, add, v128f, v128f, 2>;
346 def VAG : BinaryVRRc<"vag", 0xE7F3, add, v128g, v128g, 3>;
347 def VAQ : BinaryVRRc<"vaq", 0xE7F3, null_frag, v128q, v128q, 4>;
349 // Add compute carry.
350 def VACCB : BinaryVRRc<"vaccb", 0xE7F1, null_frag, v128b, v128b, 0>;
351 def VACCH : BinaryVRRc<"vacch", 0xE7F1, null_frag, v128h, v128h, 1>;
352 def VACCF : BinaryVRRc<"vaccf", 0xE7F1, null_frag, v128f, v128f, 2>;
353 def VACCG : BinaryVRRc<"vaccg", 0xE7F1, null_frag, v128g, v128g, 3>;
354 def VACCQ : BinaryVRRc<"vaccq", 0xE7F1, null_frag, v128q, v128q, 4>;
357 def VACQ : TernaryVRRd<"vacq", 0xE7BB, null_frag, v128q, v128q, 4>;
359 // Add with carry compute carry.
360 def VACCCQ : TernaryVRRd<"vacccq", 0xE7B9, null_frag, v128q, v128q, 4>;
363 def VN : BinaryVRRc<"vn", 0xE768, null_frag, v128any, v128any>;
365 // And with complement.
366 def VNC : BinaryVRRc<"vnc", 0xE769, null_frag, v128any, v128any>;
369 def VAVGB : BinaryVRRc<"vavgb", 0xE7F2, null_frag, v128b, v128b, 0>;
370 def VAVGH : BinaryVRRc<"vavgh", 0xE7F2, null_frag, v128h, v128h, 1>;
371 def VAVGF : BinaryVRRc<"vavgf", 0xE7F2, null_frag, v128f, v128f, 2>;
372 def VAVGG : BinaryVRRc<"vavgg", 0xE7F2, null_frag, v128g, v128g, 3>;
375 def VAVGLB : BinaryVRRc<"vavglb", 0xE7F0, null_frag, v128b, v128b, 0>;
376 def VAVGLH : BinaryVRRc<"vavglh", 0xE7F0, null_frag, v128h, v128h, 1>;
377 def VAVGLF : BinaryVRRc<"vavglf", 0xE7F0, null_frag, v128f, v128f, 2>;
378 def VAVGLG : BinaryVRRc<"vavglg", 0xE7F0, null_frag, v128g, v128g, 3>;
381 def VCKSM : BinaryVRRc<"vcksm", 0xE766, null_frag, v128any, v128any>;
383 // Count leading zeros.
384 def VCLZB : UnaryVRRa<"vclzb", 0xE753, ctlz, v128b, v128b, 0>;
385 def VCLZH : UnaryVRRa<"vclzh", 0xE753, ctlz, v128h, v128h, 1>;
386 def VCLZF : UnaryVRRa<"vclzf", 0xE753, ctlz, v128f, v128f, 2>;
387 def VCLZG : UnaryVRRa<"vclzg", 0xE753, ctlz, v128g, v128g, 3>;
389 // Count trailing zeros.
390 def VCTZB : UnaryVRRa<"vctzb", 0xE752, cttz, v128b, v128b, 0>;
391 def VCTZH : UnaryVRRa<"vctzh", 0xE752, cttz, v128h, v128h, 1>;
392 def VCTZF : UnaryVRRa<"vctzf", 0xE752, cttz, v128f, v128f, 2>;
393 def VCTZG : UnaryVRRa<"vctzg", 0xE752, cttz, v128g, v128g, 3>;
396 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>;
398 // Galois field multiply sum.
399 def VGFMB : BinaryVRRc<"vgfmb", 0xE7B4, null_frag, v128b, v128b, 0>;
400 def VGFMH : BinaryVRRc<"vgfmh", 0xE7B4, null_frag, v128h, v128h, 1>;
401 def VGFMF : BinaryVRRc<"vgfmf", 0xE7B4, null_frag, v128f, v128f, 2>;
402 def VGFMG : BinaryVRRc<"vgfmg", 0xE7B4, null_frag, v128g, v128g, 3>;
404 // Galois field multiply sum and accumulate.
405 def VGFMAB : TernaryVRRd<"vgfmab", 0xE7BC, null_frag, v128b, v128b, 0>;
406 def VGFMAH : TernaryVRRd<"vgfmah", 0xE7BC, null_frag, v128h, v128h, 1>;
407 def VGFMAF : TernaryVRRd<"vgfmaf", 0xE7BC, null_frag, v128f, v128f, 2>;
408 def VGFMAG : TernaryVRRd<"vgfmag", 0xE7BC, null_frag, v128g, v128g, 3>;
411 def VLCB : UnaryVRRa<"vlcb", 0xE7DE, z_vneg, v128b, v128b, 0>;
412 def VLCH : UnaryVRRa<"vlch", 0xE7DE, z_vneg, v128h, v128h, 1>;
413 def VLCF : UnaryVRRa<"vlcf", 0xE7DE, z_vneg, v128f, v128f, 2>;
414 def VLCG : UnaryVRRa<"vlcg", 0xE7DE, z_vneg, v128g, v128g, 3>;
417 def VLPB : UnaryVRRa<"vlpb", 0xE7DF, z_viabs8, v128b, v128b, 0>;
418 def VLPH : UnaryVRRa<"vlph", 0xE7DF, z_viabs16, v128h, v128h, 1>;
419 def VLPF : UnaryVRRa<"vlpf", 0xE7DF, z_viabs32, v128f, v128f, 2>;
420 def VLPG : UnaryVRRa<"vlpg", 0xE7DF, z_viabs64, v128g, v128g, 3>;
423 def VMXB : BinaryVRRc<"vmxb", 0xE7FF, null_frag, v128b, v128b, 0>;
424 def VMXH : BinaryVRRc<"vmxh", 0xE7FF, null_frag, v128h, v128h, 1>;
425 def VMXF : BinaryVRRc<"vmxf", 0xE7FF, null_frag, v128f, v128f, 2>;
426 def VMXG : BinaryVRRc<"vmxg", 0xE7FF, null_frag, v128g, v128g, 3>;
429 def VMXLB : BinaryVRRc<"vmxlb", 0xE7FD, null_frag, v128b, v128b, 0>;
430 def VMXLH : BinaryVRRc<"vmxlh", 0xE7FD, null_frag, v128h, v128h, 1>;
431 def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, null_frag, v128f, v128f, 2>;
432 def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, null_frag, v128g, v128g, 3>;
435 def VMNB : BinaryVRRc<"vmnb", 0xE7FE, null_frag, v128b, v128b, 0>;
436 def VMNH : BinaryVRRc<"vmnh", 0xE7FE, null_frag, v128h, v128h, 1>;
437 def VMNF : BinaryVRRc<"vmnf", 0xE7FE, null_frag, v128f, v128f, 2>;
438 def VMNG : BinaryVRRc<"vmng", 0xE7FE, null_frag, v128g, v128g, 3>;
441 def VMNLB : BinaryVRRc<"vmnlb", 0xE7FC, null_frag, v128b, v128b, 0>;
442 def VMNLH : BinaryVRRc<"vmnlh", 0xE7FC, null_frag, v128h, v128h, 1>;
443 def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, null_frag, v128f, v128f, 2>;
444 def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, null_frag, v128g, v128g, 3>;
446 // Multiply and add low.
447 def VMALB : TernaryVRRd<"vmalb", 0xE7AA, z_muladd, v128b, v128b, 0>;
448 def VMALHW : TernaryVRRd<"vmalhw", 0xE7AA, z_muladd, v128h, v128h, 1>;
449 def VMALF : TernaryVRRd<"vmalf", 0xE7AA, z_muladd, v128f, v128f, 2>;
451 // Multiply and add high.
452 def VMAHB : TernaryVRRd<"vmahb", 0xE7AB, null_frag, v128b, v128b, 0>;
453 def VMAHH : TernaryVRRd<"vmahh", 0xE7AB, null_frag, v128h, v128h, 1>;
454 def VMAHF : TernaryVRRd<"vmahf", 0xE7AB, null_frag, v128f, v128f, 2>;
456 // Multiply and add logical high.
457 def VMALHB : TernaryVRRd<"vmalhb", 0xE7A9, null_frag, v128b, v128b, 0>;
458 def VMALHH : TernaryVRRd<"vmalhh", 0xE7A9, null_frag, v128h, v128h, 1>;
459 def VMALHF : TernaryVRRd<"vmalhf", 0xE7A9, null_frag, v128f, v128f, 2>;
461 // Multiply and add even.
462 def VMAEB : TernaryVRRd<"vmaeb", 0xE7AE, null_frag, v128h, v128b, 0>;
463 def VMAEH : TernaryVRRd<"vmaeh", 0xE7AE, null_frag, v128f, v128h, 1>;
464 def VMAEF : TernaryVRRd<"vmaef", 0xE7AE, null_frag, v128g, v128f, 2>;
466 // Multiply and add logical even.
467 def VMALEB : TernaryVRRd<"vmaleb", 0xE7AC, null_frag, v128h, v128b, 0>;
468 def VMALEH : TernaryVRRd<"vmaleh", 0xE7AC, null_frag, v128f, v128h, 1>;
469 def VMALEF : TernaryVRRd<"vmalef", 0xE7AC, null_frag, v128g, v128f, 2>;
471 // Multiply and add odd.
472 def VMAOB : TernaryVRRd<"vmaob", 0xE7AF, null_frag, v128h, v128b, 0>;
473 def VMAOH : TernaryVRRd<"vmaoh", 0xE7AF, null_frag, v128f, v128h, 1>;
474 def VMAOF : TernaryVRRd<"vmaof", 0xE7AF, null_frag, v128g, v128f, 2>;
476 // Multiply and add logical odd.
477 def VMALOB : TernaryVRRd<"vmalob", 0xE7AD, null_frag, v128h, v128b, 0>;
478 def VMALOH : TernaryVRRd<"vmaloh", 0xE7AD, null_frag, v128f, v128h, 1>;
479 def VMALOF : TernaryVRRd<"vmalof", 0xE7AD, null_frag, v128g, v128f, 2>;
482 def VMHB : BinaryVRRc<"vmhb", 0xE7A3, null_frag, v128b, v128b, 0>;
483 def VMHH : BinaryVRRc<"vmhh", 0xE7A3, null_frag, v128h, v128h, 1>;
484 def VMHF : BinaryVRRc<"vmhf", 0xE7A3, null_frag, v128f, v128f, 2>;
486 // Multiply logical high.
487 def VMLHB : BinaryVRRc<"vmlhb", 0xE7A1, null_frag, v128b, v128b, 0>;
488 def VMLHH : BinaryVRRc<"vmlhh", 0xE7A1, null_frag, v128h, v128h, 1>;
489 def VMLHF : BinaryVRRc<"vmlhf", 0xE7A1, null_frag, v128f, v128f, 2>;
492 def VMLB : BinaryVRRc<"vmlb", 0xE7A2, mul, v128b, v128b, 0>;
493 def VMLHW : BinaryVRRc<"vmlhw", 0xE7A2, mul, v128h, v128h, 1>;
494 def VMLF : BinaryVRRc<"vmlf", 0xE7A2, mul, v128f, v128f, 2>;
497 def VMEB : BinaryVRRc<"vmeb", 0xE7A6, null_frag, v128h, v128b, 0>;
498 def VMEH : BinaryVRRc<"vmeh", 0xE7A6, null_frag, v128f, v128h, 1>;
499 def VMEF : BinaryVRRc<"vmef", 0xE7A6, null_frag, v128g, v128f, 2>;
501 // Multiply logical even.
502 def VMLEB : BinaryVRRc<"vmleb", 0xE7A4, null_frag, v128h, v128b, 0>;
503 def VMLEH : BinaryVRRc<"vmleh", 0xE7A4, null_frag, v128f, v128h, 1>;
504 def VMLEF : BinaryVRRc<"vmlef", 0xE7A4, null_frag, v128g, v128f, 2>;
507 def VMOB : BinaryVRRc<"vmob", 0xE7A7, null_frag, v128h, v128b, 0>;
508 def VMOH : BinaryVRRc<"vmoh", 0xE7A7, null_frag, v128f, v128h, 1>;
509 def VMOF : BinaryVRRc<"vmof", 0xE7A7, null_frag, v128g, v128f, 2>;
511 // Multiply logical odd.
512 def VMLOB : BinaryVRRc<"vmlob", 0xE7A5, null_frag, v128h, v128b, 0>;
513 def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, null_frag, v128f, v128h, 1>;
514 def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, null_frag, v128g, v128f, 2>;
517 def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>;
520 def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>;
523 def VPOPCT : BinaryVRRa<"vpopct", 0xE750>;
524 def : Pat<(v16i8 (z_popcnt VR128:$x)), (VPOPCT VR128:$x, 0)>;
526 // Element rotate left logical (with vector shift amount).
527 def VERLLVB : BinaryVRRc<"verllvb", 0xE773, null_frag, v128b, v128b, 0>;
528 def VERLLVH : BinaryVRRc<"verllvh", 0xE773, null_frag, v128h, v128h, 1>;
529 def VERLLVF : BinaryVRRc<"verllvf", 0xE773, null_frag, v128f, v128f, 2>;
530 def VERLLVG : BinaryVRRc<"verllvg", 0xE773, null_frag, v128g, v128g, 3>;
532 // Element rotate left logical (with scalar shift amount).
533 def VERLLB : BinaryVRSa<"verllb", 0xE733, null_frag, v128b, v128b, 0>;
534 def VERLLH : BinaryVRSa<"verllh", 0xE733, null_frag, v128h, v128h, 1>;
535 def VERLLF : BinaryVRSa<"verllf", 0xE733, null_frag, v128f, v128f, 2>;
536 def VERLLG : BinaryVRSa<"verllg", 0xE733, null_frag, v128g, v128g, 3>;
538 // Element rotate and insert under mask.
539 def VERIMB : QuaternaryVRId<"verimb", 0xE772, null_frag, v128b, v128b, 0>;
540 def VERIMH : QuaternaryVRId<"verimh", 0xE772, null_frag, v128h, v128h, 1>;
541 def VERIMF : QuaternaryVRId<"verimf", 0xE772, null_frag, v128f, v128f, 2>;
542 def VERIMG : QuaternaryVRId<"verimg", 0xE772, null_frag, v128g, v128g, 3>;
544 // Element shift left (with vector shift amount).
545 def VESLVB : BinaryVRRc<"veslvb", 0xE770, z_vshl, v128b, v128b, 0>;
546 def VESLVH : BinaryVRRc<"veslvh", 0xE770, z_vshl, v128h, v128h, 1>;
547 def VESLVF : BinaryVRRc<"veslvf", 0xE770, z_vshl, v128f, v128f, 2>;
548 def VESLVG : BinaryVRRc<"veslvg", 0xE770, z_vshl, v128g, v128g, 3>;
550 // Element shift left (with scalar shift amount).
551 def VESLB : BinaryVRSa<"veslb", 0xE730, z_vshl_by_scalar, v128b, v128b, 0>;
552 def VESLH : BinaryVRSa<"veslh", 0xE730, z_vshl_by_scalar, v128h, v128h, 1>;
553 def VESLF : BinaryVRSa<"veslf", 0xE730, z_vshl_by_scalar, v128f, v128f, 2>;
554 def VESLG : BinaryVRSa<"veslg", 0xE730, z_vshl_by_scalar, v128g, v128g, 3>;
556 // Element shift right arithmetic (with vector shift amount).
557 def VESRAVB : BinaryVRRc<"vesravb", 0xE77A, z_vsra, v128b, v128b, 0>;
558 def VESRAVH : BinaryVRRc<"vesravh", 0xE77A, z_vsra, v128h, v128h, 1>;
559 def VESRAVF : BinaryVRRc<"vesravf", 0xE77A, z_vsra, v128f, v128f, 2>;
560 def VESRAVG : BinaryVRRc<"vesravg", 0xE77A, z_vsra, v128g, v128g, 3>;
562 // Element shift right arithmetic (with scalar shift amount).
563 def VESRAB : BinaryVRSa<"vesrab", 0xE73A, z_vsra_by_scalar, v128b, v128b, 0>;
564 def VESRAH : BinaryVRSa<"vesrah", 0xE73A, z_vsra_by_scalar, v128h, v128h, 1>;
565 def VESRAF : BinaryVRSa<"vesraf", 0xE73A, z_vsra_by_scalar, v128f, v128f, 2>;
566 def VESRAG : BinaryVRSa<"vesrag", 0xE73A, z_vsra_by_scalar, v128g, v128g, 3>;
568 // Element shift right logical (with vector shift amount).
569 def VESRLVB : BinaryVRRc<"vesrlvb", 0xE778, z_vsrl, v128b, v128b, 0>;
570 def VESRLVH : BinaryVRRc<"vesrlvh", 0xE778, z_vsrl, v128h, v128h, 1>;
571 def VESRLVF : BinaryVRRc<"vesrlvf", 0xE778, z_vsrl, v128f, v128f, 2>;
572 def VESRLVG : BinaryVRRc<"vesrlvg", 0xE778, z_vsrl, v128g, v128g, 3>;
574 // Element shift right logical (with scalar shift amount).
575 def VESRLB : BinaryVRSa<"vesrlb", 0xE738, z_vsrl_by_scalar, v128b, v128b, 0>;
576 def VESRLH : BinaryVRSa<"vesrlh", 0xE738, z_vsrl_by_scalar, v128h, v128h, 1>;
577 def VESRLF : BinaryVRSa<"vesrlf", 0xE738, z_vsrl_by_scalar, v128f, v128f, 2>;
578 def VESRLG : BinaryVRSa<"vesrlg", 0xE738, z_vsrl_by_scalar, v128g, v128g, 3>;
581 def VSL : BinaryVRRc<"vsl", 0xE774, null_frag, v128b, v128b>;
583 // Shift left by byte.
584 def VSLB : BinaryVRRc<"vslb", 0xE775, null_frag, v128b, v128b>;
586 // Shift left double by byte.
587 def VSLDB : TernaryVRId<"vsldb", 0xE777, z_shl_double, v128b, v128b, 0>;
589 // Shift right arithmetic.
590 def VSRA : BinaryVRRc<"vsra", 0xE77E, null_frag, v128b, v128b>;
592 // Shift right arithmetic by byte.
593 def VSRAB : BinaryVRRc<"vsrab", 0xE77F, null_frag, v128b, v128b>;
595 // Shift right logical.
596 def VSRL : BinaryVRRc<"vsrl", 0xE77C, null_frag, v128b, v128b>;
598 // Shift right logical by byte.
599 def VSRLB : BinaryVRRc<"vsrlb", 0xE77D, null_frag, v128b, v128b>;
602 def VSB : BinaryVRRc<"vsb", 0xE7F7, sub, v128b, v128b, 0>;
603 def VSH : BinaryVRRc<"vsh", 0xE7F7, sub, v128h, v128h, 1>;
604 def VSF : BinaryVRRc<"vsf", 0xE7F7, sub, v128f, v128f, 2>;
605 def VSG : BinaryVRRc<"vsg", 0xE7F7, sub, v128g, v128g, 3>;
606 def VSQ : BinaryVRRc<"vsq", 0xE7F7, null_frag, v128q, v128q, 4>;
608 // Subtract compute borrow indication.
609 def VSCBIB : BinaryVRRc<"vscbib", 0xE7F5, null_frag, v128b, v128b, 0>;
610 def VSCBIH : BinaryVRRc<"vscbih", 0xE7F5, null_frag, v128h, v128h, 1>;
611 def VSCBIF : BinaryVRRc<"vscbif", 0xE7F5, null_frag, v128f, v128f, 2>;
612 def VSCBIG : BinaryVRRc<"vscbig", 0xE7F5, null_frag, v128g, v128g, 3>;
613 def VSCBIQ : BinaryVRRc<"vscbiq", 0xE7F5, null_frag, v128q, v128q, 4>;
615 // Subtract with borrow indication.
616 def VSBIQ : TernaryVRRd<"vsbiq", 0xE7BF, null_frag, v128q, v128q, 4>;
618 // Subtract with borrow compute borrow indication.
619 def VSBCBIQ : TernaryVRRd<"vsbcbiq", 0xE7BD, null_frag, v128q, v128q, 4>;
621 // Sum across doubleword.
622 def VSUMGH : BinaryVRRc<"vsumgh", 0xE765, z_vsum, v128g, v128h, 1>;
623 def VSUMGF : BinaryVRRc<"vsumgf", 0xE765, z_vsum, v128g, v128f, 2>;
625 // Sum across quadword.
626 def VSUMQF : BinaryVRRc<"vsumqf", 0xE767, z_vsum, v128q, v128f, 2>;
627 def VSUMQG : BinaryVRRc<"vsumqg", 0xE767, z_vsum, v128q, v128g, 3>;
630 def VSUMB : BinaryVRRc<"vsumb", 0xE764, z_vsum, v128f, v128b, 0>;
631 def VSUMH : BinaryVRRc<"vsumh", 0xE764, z_vsum, v128f, v128h, 1>;
634 // Instantiate the bitwise ops for type TYPE.
635 multiclass BitwiseVectorOps<ValueType type> {
636 let Predicates = [FeatureVector] in {
637 def : Pat<(type (and VR128:$x, VR128:$y)), (VN VR128:$x, VR128:$y)>;
638 def : Pat<(type (and VR128:$x, (z_vnot VR128:$y))),
639 (VNC VR128:$x, VR128:$y)>;
640 def : Pat<(type (or VR128:$x, VR128:$y)), (VO VR128:$x, VR128:$y)>;
641 def : Pat<(type (xor VR128:$x, VR128:$y)), (VX VR128:$x, VR128:$y)>;
642 def : Pat<(type (or (and VR128:$x, VR128:$z),
643 (and VR128:$y, (z_vnot VR128:$z)))),
644 (VSEL VR128:$x, VR128:$y, VR128:$z)>;
645 def : Pat<(type (z_vnot (or VR128:$x, VR128:$y))),
646 (VNO VR128:$x, VR128:$y)>;
647 def : Pat<(type (z_vnot VR128:$x)), (VNO VR128:$x, VR128:$x)>;
651 defm : BitwiseVectorOps<v16i8>;
652 defm : BitwiseVectorOps<v8i16>;
653 defm : BitwiseVectorOps<v4i32>;
654 defm : BitwiseVectorOps<v2i64>;
656 // Instantiate additional patterns for absolute-related expressions on
657 // type TYPE. LC is the negate instruction for TYPE and LP is the absolute
659 multiclass IntegerAbsoluteVectorOps<ValueType type, Instruction lc,
660 Instruction lp, int shift> {
661 let Predicates = [FeatureVector] in {
662 def : Pat<(type (vselect (type (z_vicmph_zero VR128:$x)),
663 (z_vneg VR128:$x), VR128:$x)),
665 def : Pat<(type (vselect (type (z_vnot (z_vicmph_zero VR128:$x))),
666 VR128:$x, (z_vneg VR128:$x))),
668 def : Pat<(type (vselect (type (z_vicmpl_zero VR128:$x)),
669 VR128:$x, (z_vneg VR128:$x))),
671 def : Pat<(type (vselect (type (z_vnot (z_vicmpl_zero VR128:$x))),
672 (z_vneg VR128:$x), VR128:$x)),
674 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)),
676 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))),
679 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)),
681 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))),
682 (z_vneg VR128:$x)))),
687 defm : IntegerAbsoluteVectorOps<v16i8, VLCB, VLPB, 7>;
688 defm : IntegerAbsoluteVectorOps<v8i16, VLCH, VLPH, 15>;
689 defm : IntegerAbsoluteVectorOps<v4i32, VLCF, VLPF, 31>;
690 defm : IntegerAbsoluteVectorOps<v2i64, VLCG, VLPG, 63>;
692 // Instantiate minimum- and maximum-related patterns for TYPE. CMPH is the
693 // signed or unsigned "set if greater than" comparison instruction and
694 // MIN and MAX are the associated minimum and maximum instructions.
695 multiclass IntegerMinMaxVectorOps<ValueType type, SDPatternOperator cmph,
696 Instruction min, Instruction max> {
697 let Predicates = [FeatureVector] in {
698 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$x, VR128:$y)),
699 (max VR128:$x, VR128:$y)>;
700 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$y, VR128:$x)),
701 (min VR128:$x, VR128:$y)>;
702 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)),
703 VR128:$x, VR128:$y)),
704 (min VR128:$x, VR128:$y)>;
705 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)),
706 VR128:$y, VR128:$x)),
707 (max VR128:$x, VR128:$y)>;
712 defm : IntegerMinMaxVectorOps<v16i8, z_vicmph, VMNB, VMXB>;
713 defm : IntegerMinMaxVectorOps<v8i16, z_vicmph, VMNH, VMXH>;
714 defm : IntegerMinMaxVectorOps<v4i32, z_vicmph, VMNF, VMXF>;
715 defm : IntegerMinMaxVectorOps<v2i64, z_vicmph, VMNG, VMXG>;
718 defm : IntegerMinMaxVectorOps<v16i8, z_vicmphl, VMNLB, VMXLB>;
719 defm : IntegerMinMaxVectorOps<v8i16, z_vicmphl, VMNLH, VMXLH>;
720 defm : IntegerMinMaxVectorOps<v4i32, z_vicmphl, VMNLF, VMXLF>;
721 defm : IntegerMinMaxVectorOps<v2i64, z_vicmphl, VMNLG, VMXLG>;
723 //===----------------------------------------------------------------------===//
724 // Integer comparison
725 //===----------------------------------------------------------------------===//
727 let Predicates = [FeatureVector] in {
730 def VECB : CompareVRRa<"vecb", 0xE7DB, null_frag, v128b, 0>;
731 def VECH : CompareVRRa<"vech", 0xE7DB, null_frag, v128h, 1>;
732 def VECF : CompareVRRa<"vecf", 0xE7DB, null_frag, v128f, 2>;
733 def VECG : CompareVRRa<"vecg", 0xE7DB, null_frag, v128g, 3>;
736 // Element compare logical.
738 def VECLB : CompareVRRa<"veclb", 0xE7D9, null_frag, v128b, 0>;
739 def VECLH : CompareVRRa<"veclh", 0xE7D9, null_frag, v128h, 1>;
740 def VECLF : CompareVRRa<"veclf", 0xE7D9, null_frag, v128f, 2>;
741 def VECLG : CompareVRRa<"veclg", 0xE7D9, null_frag, v128g, 3>;
745 defm VCEQB : BinaryVRRbSPair<"vceqb", 0xE7F8, z_vicmpe, null_frag,
747 defm VCEQH : BinaryVRRbSPair<"vceqh", 0xE7F8, z_vicmpe, null_frag,
749 defm VCEQF : BinaryVRRbSPair<"vceqf", 0xE7F8, z_vicmpe, null_frag,
751 defm VCEQG : BinaryVRRbSPair<"vceqg", 0xE7F8, z_vicmpe, null_frag,
755 defm VCHB : BinaryVRRbSPair<"vchb", 0xE7FB, z_vicmph, null_frag,
757 defm VCHH : BinaryVRRbSPair<"vchh", 0xE7FB, z_vicmph, null_frag,
759 defm VCHF : BinaryVRRbSPair<"vchf", 0xE7FB, z_vicmph, null_frag,
761 defm VCHG : BinaryVRRbSPair<"vchg", 0xE7FB, z_vicmph, null_frag,
764 // Compare high logical.
765 defm VCHLB : BinaryVRRbSPair<"vchlb", 0xE7F9, z_vicmphl, null_frag,
767 defm VCHLH : BinaryVRRbSPair<"vchlh", 0xE7F9, z_vicmphl, null_frag,
769 defm VCHLF : BinaryVRRbSPair<"vchlf", 0xE7F9, z_vicmphl, null_frag,
771 defm VCHLG : BinaryVRRbSPair<"vchlg", 0xE7F9, z_vicmphl, null_frag,
776 def VTM : CompareVRRa<"vtm", 0xE7D8, null_frag, v128any, 0>;
779 //===----------------------------------------------------------------------===//
780 // Floating-point arithmetic
781 //===----------------------------------------------------------------------===//
783 // See comments in SystemZInstrFP.td for the suppression flags and
785 multiclass VectorRounding<Instruction insn, TypedReg tr> {
786 def : FPConversion<insn, frint, tr, tr, 0, 0>;
787 def : FPConversion<insn, fnearbyint, tr, tr, 4, 0>;
788 def : FPConversion<insn, ffloor, tr, tr, 4, 7>;
789 def : FPConversion<insn, fceil, tr, tr, 4, 6>;
790 def : FPConversion<insn, ftrunc, tr, tr, 4, 5>;
791 def : FPConversion<insn, frnd, tr, tr, 4, 1>;
794 let Predicates = [FeatureVector] in {
796 def VFADB : BinaryVRRc<"vfadb", 0xE7E3, fadd, v128db, v128db, 3, 0>;
797 def WFADB : BinaryVRRc<"wfadb", 0xE7E3, fadd, v64db, v64db, 3, 8>;
799 // Convert from fixed 64-bit.
800 def VCDGB : TernaryVRRa<"vcdgb", 0xE7C3, null_frag, v128db, v128g, 3, 0>;
801 def WCDGB : TernaryVRRa<"wcdgb", 0xE7C3, null_frag, v64db, v64g, 3, 8>;
802 def : FPConversion<VCDGB, sint_to_fp, v128db, v128g, 0, 0>;
804 // Convert from logical 64-bit.
805 def VCDLGB : TernaryVRRa<"vcdlgb", 0xE7C1, null_frag, v128db, v128g, 3, 0>;
806 def WCDLGB : TernaryVRRa<"wcdlgb", 0xE7C1, null_frag, v64db, v64g, 3, 8>;
807 def : FPConversion<VCDLGB, uint_to_fp, v128db, v128g, 0, 0>;
809 // Convert to fixed 64-bit.
810 def VCGDB : TernaryVRRa<"vcgdb", 0xE7C2, null_frag, v128g, v128db, 3, 0>;
811 def WCGDB : TernaryVRRa<"wcgdb", 0xE7C2, null_frag, v64g, v64db, 3, 8>;
812 // Rounding mode should agree with SystemZInstrFP.td.
813 def : FPConversion<VCGDB, fp_to_sint, v128g, v128db, 0, 5>;
815 // Convert to logical 64-bit.
816 def VCLGDB : TernaryVRRa<"vclgdb", 0xE7C0, null_frag, v128g, v128db, 3, 0>;
817 def WCLGDB : TernaryVRRa<"wclgdb", 0xE7C0, null_frag, v64g, v64db, 3, 8>;
818 // Rounding mode should agree with SystemZInstrFP.td.
819 def : FPConversion<VCLGDB, fp_to_uint, v128g, v128db, 0, 5>;
822 def VFDDB : BinaryVRRc<"vfddb", 0xE7E5, fdiv, v128db, v128db, 3, 0>;
823 def WFDDB : BinaryVRRc<"wfddb", 0xE7E5, fdiv, v64db, v64db, 3, 8>;
826 def VFIDB : TernaryVRRa<"vfidb", 0xE7C7, null_frag, v128db, v128db, 3, 0>;
827 def WFIDB : TernaryVRRa<"wfidb", 0xE7C7, null_frag, v64db, v64db, 3, 8>;
828 defm : VectorRounding<VFIDB, v128db>;
829 defm : VectorRounding<WFIDB, v64db>;
832 def VLDEB : UnaryVRRa<"vldeb", 0xE7C4, z_vextend, v128db, v128eb, 2, 0>;
833 def WLDEB : UnaryVRRa<"wldeb", 0xE7C4, fextend, v64db, v32eb, 2, 8>;
836 def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128eb, v128db, 3, 0>;
837 def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32eb, v64db, 3, 8>;
838 def : Pat<(v4f32 (z_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>;
839 def : FPConversion<WLEDB, fround, v32eb, v64db, 0, 0>;
842 def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, fmul, v128db, v128db, 3, 0>;
843 def WFMDB : BinaryVRRc<"wfmdb", 0xE7E7, fmul, v64db, v64db, 3, 8>;
846 def VFMADB : TernaryVRRe<"vfmadb", 0xE78F, fma, v128db, v128db, 0, 3>;
847 def WFMADB : TernaryVRRe<"wfmadb", 0xE78F, fma, v64db, v64db, 8, 3>;
849 // Multiply and subtract.
850 def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, fms, v128db, v128db, 0, 3>;
851 def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, fms, v64db, v64db, 8, 3>;
854 def VFLCDB : UnaryVRRa<"vflcdb", 0xE7CC, fneg, v128db, v128db, 3, 0, 0>;
855 def WFLCDB : UnaryVRRa<"wflcdb", 0xE7CC, fneg, v64db, v64db, 3, 8, 0>;
858 def VFLNDB : UnaryVRRa<"vflndb", 0xE7CC, fnabs, v128db, v128db, 3, 0, 1>;
859 def WFLNDB : UnaryVRRa<"wflndb", 0xE7CC, fnabs, v64db, v64db, 3, 8, 1>;
862 def VFLPDB : UnaryVRRa<"vflpdb", 0xE7CC, fabs, v128db, v128db, 3, 0, 2>;
863 def WFLPDB : UnaryVRRa<"wflpdb", 0xE7CC, fabs, v64db, v64db, 3, 8, 2>;
866 def VFSQDB : UnaryVRRa<"vfsqdb", 0xE7CE, fsqrt, v128db, v128db, 3, 0>;
867 def WFSQDB : UnaryVRRa<"wfsqdb", 0xE7CE, fsqrt, v64db, v64db, 3, 8>;
870 def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, fsub, v128db, v128db, 3, 0>;
871 def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, fsub, v64db, v64db, 3, 8>;
873 // Test data class immediate.
875 def VFTCIDB : BinaryVRIe<"vftcidb", 0xE74A, null_frag, v128g, v128db, 3, 0>;
876 def WFTCIDB : BinaryVRIe<"wftcidb", 0xE74A, null_frag, v64g, v64db, 3, 8>;
880 //===----------------------------------------------------------------------===//
881 // Floating-point comparison
882 //===----------------------------------------------------------------------===//
884 let Predicates = [FeatureVector] in {
887 def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, z_fcmp, v64db, 3>;
889 // Compare and signal scalar.
891 def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, null_frag, v64db, 3>;
894 defm VFCEDB : BinaryVRRcSPair<"vfcedb", 0xE7E8, z_vfcmpe, null_frag,
895 v128g, v128db, 3, 0>;
896 defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag,
900 defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, z_vfcmph, null_frag,
901 v128g, v128db, 3, 0>;
902 defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag,
905 // Compare high or equal.
906 defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, z_vfcmphe, null_frag,
907 v128g, v128db, 3, 0>;
908 defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag,
912 //===----------------------------------------------------------------------===//
914 //===----------------------------------------------------------------------===//
916 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
917 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
918 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
919 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
920 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
922 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
923 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
924 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
925 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
926 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
928 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
929 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
930 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
931 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
932 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
934 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
935 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
936 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
937 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
938 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
940 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
941 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
942 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
943 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
944 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
946 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
947 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
948 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
949 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
950 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
952 //===----------------------------------------------------------------------===//
953 // Replicating scalars
954 //===----------------------------------------------------------------------===//
956 // Define patterns for replicating a scalar GR32 into a vector of type TYPE.
957 // INDEX is 8 minus the element size in bytes.
958 class VectorReplicateScalar<ValueType type, Instruction insn, bits<16> index>
959 : Pat<(type (z_replicate GR32:$scalar)),
960 (insn (VLVGP32 GR32:$scalar, GR32:$scalar), index)>;
962 def : VectorReplicateScalar<v16i8, VREPB, 7>;
963 def : VectorReplicateScalar<v8i16, VREPH, 3>;
964 def : VectorReplicateScalar<v4i32, VREPF, 1>;
966 // i64 replications are just a single isntruction.
967 def : Pat<(v2i64 (z_replicate GR64:$scalar)),
968 (VLVGP GR64:$scalar, GR64:$scalar)>;
970 //===----------------------------------------------------------------------===//
971 // Floating-point insertion and extraction
972 //===----------------------------------------------------------------------===//
974 // Moving 32-bit values between GPRs and FPRs can be done using VLVGF
976 def LEFR : UnaryAliasVRS<VR32, GR32>;
977 def LFER : UnaryAliasVRS<GR64, VR32>;
978 def : Pat<(f32 (bitconvert (i32 GR32:$src))), (LEFR GR32:$src)>;
979 def : Pat<(i32 (bitconvert (f32 VR32:$src))),
980 (EXTRACT_SUBREG (LFER VR32:$src), subreg_l32)>;
982 // Floating-point values are stored in element 0 of the corresponding
983 // vector register. Scalar to vector conversion is just a subreg and
984 // scalar replication can just replicate element 0 of the vector register.
985 multiclass ScalarToVectorFP<Instruction vrep, ValueType vt, RegisterOperand cls,
986 SubRegIndex subreg> {
987 def : Pat<(vt (scalar_to_vector cls:$scalar)),
988 (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg)>;
989 def : Pat<(vt (z_replicate cls:$scalar)),
990 (vrep (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar,
993 defm : ScalarToVectorFP<VREPF, v4f32, FP32, subreg_r32>;
994 defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_r64>;
996 // Match v2f64 insertions. The AddedComplexity counters the 3 added by
997 // TableGen for the base register operand in VLVG-based integer insertions
998 // and ensures that this version is strictly better.
999 let AddedComplexity = 4 in {
1000 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0),
1001 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
1002 subreg_r64), VR128:$vec, 1)>;
1003 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1),
1004 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
1008 // We extract floating-point element X by replicating (for elements other
1009 // than 0) and then taking a high subreg. The AddedComplexity counters the
1010 // 3 added by TableGen for the base register operand in VLGV-based integer
1011 // extractions and ensures that this version is strictly better.
1012 let AddedComplexity = 4 in {
1013 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), 0)),
1014 (EXTRACT_SUBREG VR128:$vec, subreg_r32)>;
1015 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), imm32zx2:$index)),
1016 (EXTRACT_SUBREG (VREPF VR128:$vec, imm32zx2:$index), subreg_r32)>;
1018 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), 0)),
1019 (EXTRACT_SUBREG VR128:$vec, subreg_r64)>;
1020 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), imm32zx1:$index)),
1021 (EXTRACT_SUBREG (VREPG VR128:$vec, imm32zx1:$index), subreg_r64)>;
1024 //===----------------------------------------------------------------------===//
1025 // String instructions
1026 //===----------------------------------------------------------------------===//
1028 let Predicates = [FeatureVector] in {
1029 defm VFAEB : TernaryVRRbSPair<"vfaeb", 0xE782, null_frag, null_frag,
1030 v128b, v128b, 0, 0>;
1031 defm VFAEH : TernaryVRRbSPair<"vfaeh", 0xE782, null_frag, null_frag,
1032 v128h, v128h, 1, 0>;
1033 defm VFAEF : TernaryVRRbSPair<"vfaef", 0xE782, null_frag, null_frag,
1034 v128f, v128f, 2, 0>;
1035 defm VFAEZB : TernaryVRRbSPair<"vfaezb", 0xE782, null_frag, null_frag,
1036 v128b, v128b, 0, 2>;
1037 defm VFAEZH : TernaryVRRbSPair<"vfaezh", 0xE782, null_frag, null_frag,
1038 v128h, v128h, 1, 2>;
1039 defm VFAEZF : TernaryVRRbSPair<"vfaezf", 0xE782, null_frag, null_frag,
1040 v128f, v128f, 2, 2>;
1042 defm VFEEB : BinaryVRRbSPair<"vfeeb", 0xE780, null_frag, null_frag,
1043 v128b, v128b, 0, 0, 1>;
1044 defm VFEEH : BinaryVRRbSPair<"vfeeh", 0xE780, null_frag, null_frag,
1045 v128h, v128h, 1, 0, 1>;
1046 defm VFEEF : BinaryVRRbSPair<"vfeef", 0xE780, null_frag, null_frag,
1047 v128f, v128f, 2, 0, 1>;
1048 defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, null_frag, null_frag,
1049 v128b, v128b, 0, 2, 3>;
1050 defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, null_frag, null_frag,
1051 v128h, v128h, 1, 2, 3>;
1052 defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, null_frag, null_frag,
1053 v128f, v128f, 2, 2, 3>;
1055 defm VFENEB : BinaryVRRbSPair<"vfeneb", 0xE781, null_frag, null_frag,
1056 v128b, v128b, 0, 0, 1>;
1057 defm VFENEH : BinaryVRRbSPair<"vfeneh", 0xE781, null_frag, null_frag,
1058 v128h, v128h, 1, 0, 1>;
1059 defm VFENEF : BinaryVRRbSPair<"vfenef", 0xE781, null_frag, null_frag,
1060 v128f, v128f, 2, 0, 1>;
1061 defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, null_frag, null_frag,
1062 v128b, v128b, 0, 2, 3>;
1063 defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, null_frag, null_frag,
1064 v128h, v128h, 1, 2, 3>;
1065 defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, null_frag, null_frag,
1066 v128f, v128f, 2, 2, 3>;
1068 defm VISTRB : UnaryVRRaSPair<"vistrb", 0xE75C, null_frag, null_frag,
1070 defm VISTRH : UnaryVRRaSPair<"vistrh", 0xE75C, null_frag, null_frag,
1072 defm VISTRF : UnaryVRRaSPair<"vistrf", 0xE75C, null_frag, null_frag,
1075 defm VSTRCB : QuaternaryVRRdSPair<"vstrcb", 0xE78A, null_frag, null_frag,
1076 v128b, v128b, 0, 0>;
1077 defm VSTRCH : QuaternaryVRRdSPair<"vstrch", 0xE78A, null_frag, null_frag,
1078 v128h, v128h, 1, 0>;
1079 defm VSTRCF : QuaternaryVRRdSPair<"vstrcf", 0xE78A, null_frag, null_frag,
1080 v128f, v128f, 2, 0>;
1081 defm VSTRCZB : QuaternaryVRRdSPair<"vstrczb", 0xE78A, null_frag, null_frag,
1082 v128b, v128b, 0, 2>;
1083 defm VSTRCZH : QuaternaryVRRdSPair<"vstrczh", 0xE78A, null_frag, null_frag,
1084 v128h, v128h, 1, 2>;
1085 defm VSTRCZF : QuaternaryVRRdSPair<"vstrczf", 0xE78A, null_frag, null_frag,
1086 v128f, v128f, 2, 2>;