1 //==- SystemZInstrVector.td - SystemZ Vector instructions ------*- tblgen-*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 let Predicates = [FeatureVector] in {
16 def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>;
17 def VLR32 : UnaryAliasVRR<null_frag, v32eb, v32eb>;
18 def VLR64 : UnaryAliasVRR<null_frag, v64db, v64db>;
20 // Load GR from VR element.
21 def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>;
22 def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>;
23 def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>;
24 def VLGVG : BinaryVRSc<"vlgvg", 0xE721, z_vector_extract, v128g, 3>;
26 // Load VR element from GR.
27 def VLVGB : TernaryVRSb<"vlvgb", 0xE722, z_vector_insert,
28 v128b, v128b, GR32, 0>;
29 def VLVGH : TernaryVRSb<"vlvgh", 0xE722, z_vector_insert,
30 v128h, v128h, GR32, 1>;
31 def VLVGF : TernaryVRSb<"vlvgf", 0xE722, z_vector_insert,
32 v128f, v128f, GR32, 2>;
33 def VLVGG : TernaryVRSb<"vlvgg", 0xE722, z_vector_insert,
34 v128g, v128g, GR64, 3>;
36 // Load VR from GRs disjoint.
37 def VLVGP : BinaryVRRf<"vlvgp", 0xE762, z_join_dwords, v128g>;
38 def VLVGP32 : BinaryAliasVRRf<GR32>;
41 // Extractions always assign to the full GR64, even if the element would
42 // fit in the lower 32 bits. Sub-i64 extracts therefore need to take a
43 // subreg of the result.
44 class VectorExtractSubreg<ValueType type, Instruction insn>
45 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)),
46 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>;
48 def : VectorExtractSubreg<v16i8, VLGVB>;
49 def : VectorExtractSubreg<v8i16, VLGVH>;
50 def : VectorExtractSubreg<v4i32, VLGVF>;
52 //===----------------------------------------------------------------------===//
53 // Immediate instructions
54 //===----------------------------------------------------------------------===//
56 let Predicates = [FeatureVector] in {
57 // Generate byte mask.
58 def VZERO : InherentVRIa<"vzero", 0xE744, 0>;
59 def VONE : InherentVRIa<"vone", 0xE744, 0xffff>;
60 def VGBM : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16>;
63 def VGMB : BinaryVRIb<"vgmb", 0xE746, z_rotate_mask, v128b, 0>;
64 def VGMH : BinaryVRIb<"vgmh", 0xE746, z_rotate_mask, v128h, 1>;
65 def VGMF : BinaryVRIb<"vgmf", 0xE746, z_rotate_mask, v128f, 2>;
66 def VGMG : BinaryVRIb<"vgmg", 0xE746, z_rotate_mask, v128g, 3>;
68 // Load element immediate.
70 // We want these instructions to be used ahead of VLVG* where possible.
71 // However, VLVG* takes a variable BD-format index whereas VLEI takes
72 // a plain immediate index. This means that VLVG* has an extra "base"
73 // register operand and is 3 units more complex. Bumping the complexity
74 // of the VLEI* instructions by 4 means that they are strictly better
75 // than VLVG* in cases where both forms match.
76 let AddedComplexity = 4 in {
77 def VLEIB : TernaryVRIa<"vleib", 0xE740, z_vector_insert,
78 v128b, v128b, imm32sx16trunc, imm32zx4>;
79 def VLEIH : TernaryVRIa<"vleih", 0xE741, z_vector_insert,
80 v128h, v128h, imm32sx16trunc, imm32zx3>;
81 def VLEIF : TernaryVRIa<"vleif", 0xE743, z_vector_insert,
82 v128f, v128f, imm32sx16, imm32zx2>;
83 def VLEIG : TernaryVRIa<"vleig", 0xE742, z_vector_insert,
84 v128g, v128g, imm64sx16, imm32zx1>;
87 // Replicate immediate.
88 def VREPIB : UnaryVRIa<"vrepib", 0xE745, z_replicate, v128b, imm32sx16, 0>;
89 def VREPIH : UnaryVRIa<"vrepih", 0xE745, z_replicate, v128h, imm32sx16, 1>;
90 def VREPIF : UnaryVRIa<"vrepif", 0xE745, z_replicate, v128f, imm32sx16, 2>;
91 def VREPIG : UnaryVRIa<"vrepig", 0xE745, z_replicate, v128g, imm32sx16, 3>;
94 //===----------------------------------------------------------------------===//
96 //===----------------------------------------------------------------------===//
98 let Predicates = [FeatureVector] in {
100 def VL : UnaryVRX<"vl", 0xE706, null_frag, v128any, 16>;
102 // Load to block boundary. The number of loaded bytes is only known
103 // at run time. The instruction is really polymorphic, but v128b matches
104 // the return type of the associated intrinsic.
105 def VLBB : BinaryVRX<"vlbb", 0xE707, int_s390_vlbb, v128b, 0>;
107 // Load count to block boundary.
109 def LCBB : InstRXE<0xE727, (outs GR32:$R1),
110 (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
111 "lcbb\t$R1, $XBD2, $M3",
112 [(set GR32:$R1, (int_s390_lcbb bdxaddr12only:$XBD2,
115 // Load with length. The number of loaded bytes is only known at run time.
116 def VLL : BinaryVRSb<"vll", 0xE737, int_s390_vll, 0>;
119 def VLM : LoadMultipleVRSa<"vlm", 0xE736>;
121 // Load and replicate
122 def VLREPB : UnaryVRX<"vlrepb", 0xE705, z_replicate_loadi8, v128b, 1, 0>;
123 def VLREPH : UnaryVRX<"vlreph", 0xE705, z_replicate_loadi16, v128h, 2, 1>;
124 def VLREPF : UnaryVRX<"vlrepf", 0xE705, z_replicate_loadi32, v128f, 4, 2>;
125 def VLREPG : UnaryVRX<"vlrepg", 0xE705, z_replicate_loadi64, v128g, 8, 3>;
126 def : Pat<(v4f32 (z_replicate_loadf32 bdxaddr12only:$addr)),
127 (VLREPF bdxaddr12only:$addr)>;
128 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)),
129 (VLREPG bdxaddr12only:$addr)>;
131 // Use VLREP to load subvectors. These patterns use "12pair" because
132 // LEY and LDY offer full 20-bit displacement fields. It's often better
133 // to use those instructions rather than force a 20-bit displacement
134 // into a GPR temporary.
135 def VL32 : UnaryAliasVRX<load, v32eb, bdxaddr12pair>;
136 def VL64 : UnaryAliasVRX<load, v64db, bdxaddr12pair>;
138 // Load logical element and zero.
139 def VLLEZB : UnaryVRX<"vllezb", 0xE704, z_vllezi8, v128b, 1, 0>;
140 def VLLEZH : UnaryVRX<"vllezh", 0xE704, z_vllezi16, v128h, 2, 1>;
141 def VLLEZF : UnaryVRX<"vllezf", 0xE704, z_vllezi32, v128f, 4, 2>;
142 def VLLEZG : UnaryVRX<"vllezg", 0xE704, z_vllezi64, v128g, 8, 3>;
143 def : Pat<(v4f32 (z_vllezf32 bdxaddr12only:$addr)),
144 (VLLEZF bdxaddr12only:$addr)>;
145 def : Pat<(v2f64 (z_vllezf64 bdxaddr12only:$addr)),
146 (VLLEZG bdxaddr12only:$addr)>;
149 def VLEB : TernaryVRX<"vleb", 0xE700, z_vlei8, v128b, v128b, 1, imm32zx4>;
150 def VLEH : TernaryVRX<"vleh", 0xE701, z_vlei16, v128h, v128h, 2, imm32zx3>;
151 def VLEF : TernaryVRX<"vlef", 0xE703, z_vlei32, v128f, v128f, 4, imm32zx2>;
152 def VLEG : TernaryVRX<"vleg", 0xE702, z_vlei64, v128g, v128g, 8, imm32zx1>;
153 def : Pat<(z_vlef32 (v4f32 VR128:$val), bdxaddr12only:$addr, imm32zx2:$index),
154 (VLEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>;
155 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index),
156 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;
159 def VGEF : TernaryVRV<"vgef", 0xE713, 4, imm32zx2>;
160 def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>;
163 // Use replicating loads if we're inserting a single element into an
164 // undefined vector. This avoids a false dependency on the previous
165 // register contents.
166 multiclass ReplicatePeephole<Instruction vlrep, ValueType vectype,
167 SDPatternOperator load, ValueType scalartype> {
168 def : Pat<(vectype (z_vector_insert
169 (undef), (scalartype (load bdxaddr12only:$addr)), 0)),
170 (vlrep bdxaddr12only:$addr)>;
171 def : Pat<(vectype (scalar_to_vector
172 (scalartype (load bdxaddr12only:$addr)))),
173 (vlrep bdxaddr12only:$addr)>;
175 defm : ReplicatePeephole<VLREPB, v16i8, anyextloadi8, i32>;
176 defm : ReplicatePeephole<VLREPH, v8i16, anyextloadi16, i32>;
177 defm : ReplicatePeephole<VLREPF, v4i32, load, i32>;
178 defm : ReplicatePeephole<VLREPG, v2i64, load, i64>;
179 defm : ReplicatePeephole<VLREPF, v4f32, load, f32>;
180 defm : ReplicatePeephole<VLREPG, v2f64, load, f64>;
182 //===----------------------------------------------------------------------===//
184 //===----------------------------------------------------------------------===//
186 let Predicates = [FeatureVector] in {
188 def VST : StoreVRX<"vst", 0xE70E, null_frag, v128any, 16>;
190 // Store with length. The number of stored bytes is only known at run time.
191 def VSTL : StoreLengthVRSb<"vstl", 0xE73F, int_s390_vstl, 0>;
194 def VSTM : StoreMultipleVRSa<"vstm", 0xE73E>;
197 def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, z_vstei8, v128b, 1, imm32zx4>;
198 def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, z_vstei16, v128h, 2, imm32zx3>;
199 def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, z_vstei32, v128f, 4, imm32zx2>;
200 def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, z_vstei64, v128g, 8, imm32zx1>;
201 def : Pat<(z_vstef32 (v4f32 VR128:$val), bdxaddr12only:$addr,
203 (VSTEF VR128:$val, bdxaddr12only:$addr, imm32zx2:$index)>;
204 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr,
206 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;
208 // Use VSTE to store subvectors. These patterns use "12pair" because
209 // STEY and STDY offer full 20-bit displacement fields. It's often better
210 // to use those instructions rather than force a 20-bit displacement
211 // into a GPR temporary.
212 def VST32 : StoreAliasVRX<store, v32eb, bdxaddr12pair>;
213 def VST64 : StoreAliasVRX<store, v64db, bdxaddr12pair>;
216 def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>;
217 def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>;
220 //===----------------------------------------------------------------------===//
221 // Selects and permutes
222 //===----------------------------------------------------------------------===//
224 let Predicates = [FeatureVector] in {
226 def VMRHB : BinaryVRRc<"vmrhb", 0xE761, z_merge_high, v128b, v128b, 0>;
227 def VMRHH : BinaryVRRc<"vmrhh", 0xE761, z_merge_high, v128h, v128h, 1>;
228 def VMRHF : BinaryVRRc<"vmrhf", 0xE761, z_merge_high, v128f, v128f, 2>;
229 def VMRHG : BinaryVRRc<"vmrhg", 0xE761, z_merge_high, v128g, v128g, 3>;
230 def : BinaryRRWithType<VMRHF, VR128, z_merge_high, v4f32>;
231 def : BinaryRRWithType<VMRHG, VR128, z_merge_high, v2f64>;
234 def VMRLB : BinaryVRRc<"vmrlb", 0xE760, z_merge_low, v128b, v128b, 0>;
235 def VMRLH : BinaryVRRc<"vmrlh", 0xE760, z_merge_low, v128h, v128h, 1>;
236 def VMRLF : BinaryVRRc<"vmrlf", 0xE760, z_merge_low, v128f, v128f, 2>;
237 def VMRLG : BinaryVRRc<"vmrlg", 0xE760, z_merge_low, v128g, v128g, 3>;
238 def : BinaryRRWithType<VMRLF, VR128, z_merge_low, v4f32>;
239 def : BinaryRRWithType<VMRLG, VR128, z_merge_low, v2f64>;
242 def VPERM : TernaryVRRe<"vperm", 0xE78C, z_permute, v128b, v128b>;
244 // Permute doubleword immediate.
245 def VPDI : TernaryVRRc<"vpdi", 0xE784, z_permute_dwords, v128g, v128g>;
248 def VREPB : BinaryVRIc<"vrepb", 0xE74D, z_splat, v128b, v128b, 0>;
249 def VREPH : BinaryVRIc<"vreph", 0xE74D, z_splat, v128h, v128h, 1>;
250 def VREPF : BinaryVRIc<"vrepf", 0xE74D, z_splat, v128f, v128f, 2>;
251 def VREPG : BinaryVRIc<"vrepg", 0xE74D, z_splat, v128g, v128g, 3>;
252 def : Pat<(v4f32 (z_splat VR128:$vec, imm32zx16:$index)),
253 (VREPF VR128:$vec, imm32zx16:$index)>;
254 def : Pat<(v2f64 (z_splat VR128:$vec, imm32zx16:$index)),
255 (VREPG VR128:$vec, imm32zx16:$index)>;
258 def VSEL : TernaryVRRe<"vsel", 0xE78D, null_frag, v128any, v128any>;
261 //===----------------------------------------------------------------------===//
262 // Widening and narrowing
263 //===----------------------------------------------------------------------===//
265 let Predicates = [FeatureVector] in {
267 def VPKH : BinaryVRRc<"vpkh", 0xE794, z_pack, v128b, v128h, 1>;
268 def VPKF : BinaryVRRc<"vpkf", 0xE794, z_pack, v128h, v128f, 2>;
269 def VPKG : BinaryVRRc<"vpkg", 0xE794, z_pack, v128f, v128g, 3>;
272 defm VPKSH : BinaryVRRbSPair<"vpksh", 0xE797, int_s390_vpksh, z_packs_cc,
274 defm VPKSF : BinaryVRRbSPair<"vpksf", 0xE797, int_s390_vpksf, z_packs_cc,
276 defm VPKSG : BinaryVRRbSPair<"vpksg", 0xE797, int_s390_vpksg, z_packs_cc,
279 // Pack saturate logical.
280 defm VPKLSH : BinaryVRRbSPair<"vpklsh", 0xE795, int_s390_vpklsh, z_packls_cc,
282 defm VPKLSF : BinaryVRRbSPair<"vpklsf", 0xE795, int_s390_vpklsf, z_packls_cc,
284 defm VPKLSG : BinaryVRRbSPair<"vpklsg", 0xE795, int_s390_vpklsg, z_packls_cc,
287 // Sign-extend to doubleword.
288 def VSEGB : UnaryVRRa<"vsegb", 0xE75F, z_vsei8, v128g, v128g, 0>;
289 def VSEGH : UnaryVRRa<"vsegh", 0xE75F, z_vsei16, v128g, v128g, 1>;
290 def VSEGF : UnaryVRRa<"vsegf", 0xE75F, z_vsei32, v128g, v128g, 2>;
291 def : Pat<(z_vsei8_by_parts (v16i8 VR128:$src)), (VSEGB VR128:$src)>;
292 def : Pat<(z_vsei16_by_parts (v8i16 VR128:$src)), (VSEGH VR128:$src)>;
293 def : Pat<(z_vsei32_by_parts (v4i32 VR128:$src)), (VSEGF VR128:$src)>;
296 def VUPHB : UnaryVRRa<"vuphb", 0xE7D7, z_unpack_high, v128h, v128b, 0>;
297 def VUPHH : UnaryVRRa<"vuphh", 0xE7D7, z_unpack_high, v128f, v128h, 1>;
298 def VUPHF : UnaryVRRa<"vuphf", 0xE7D7, z_unpack_high, v128g, v128f, 2>;
300 // Unpack logical high.
301 def VUPLHB : UnaryVRRa<"vuplhb", 0xE7D5, z_unpackl_high, v128h, v128b, 0>;
302 def VUPLHH : UnaryVRRa<"vuplhh", 0xE7D5, z_unpackl_high, v128f, v128h, 1>;
303 def VUPLHF : UnaryVRRa<"vuplhf", 0xE7D5, z_unpackl_high, v128g, v128f, 2>;
306 def VUPLB : UnaryVRRa<"vuplb", 0xE7D6, z_unpack_low, v128h, v128b, 0>;
307 def VUPLHW : UnaryVRRa<"vuplhw", 0xE7D6, z_unpack_low, v128f, v128h, 1>;
308 def VUPLF : UnaryVRRa<"vuplf", 0xE7D6, z_unpack_low, v128g, v128f, 2>;
310 // Unpack logical low.
311 def VUPLLB : UnaryVRRa<"vupllb", 0xE7D4, z_unpackl_low, v128h, v128b, 0>;
312 def VUPLLH : UnaryVRRa<"vupllh", 0xE7D4, z_unpackl_low, v128f, v128h, 1>;
313 def VUPLLF : UnaryVRRa<"vupllf", 0xE7D4, z_unpackl_low, v128g, v128f, 2>;
316 //===----------------------------------------------------------------------===//
317 // Instantiating generic operations for specific types.
318 //===----------------------------------------------------------------------===//
320 multiclass GenericVectorOps<ValueType type, ValueType inttype> {
321 let Predicates = [FeatureVector] in {
322 def : Pat<(type (load bdxaddr12only:$addr)),
323 (VL bdxaddr12only:$addr)>;
324 def : Pat<(store (type VR128:$src), bdxaddr12only:$addr),
325 (VST VR128:$src, bdxaddr12only:$addr)>;
326 def : Pat<(type (vselect (inttype VR128:$x), VR128:$y, VR128:$z)),
327 (VSEL VR128:$y, VR128:$z, VR128:$x)>;
328 def : Pat<(type (vselect (inttype (z_vnot VR128:$x)), VR128:$y, VR128:$z)),
329 (VSEL VR128:$z, VR128:$y, VR128:$x)>;
333 defm : GenericVectorOps<v16i8, v16i8>;
334 defm : GenericVectorOps<v8i16, v8i16>;
335 defm : GenericVectorOps<v4i32, v4i32>;
336 defm : GenericVectorOps<v2i64, v2i64>;
337 defm : GenericVectorOps<v4f32, v4i32>;
338 defm : GenericVectorOps<v2f64, v2i64>;
340 //===----------------------------------------------------------------------===//
341 // Integer arithmetic
342 //===----------------------------------------------------------------------===//
344 let Predicates = [FeatureVector] in {
346 def VAB : BinaryVRRc<"vab", 0xE7F3, add, v128b, v128b, 0>;
347 def VAH : BinaryVRRc<"vah", 0xE7F3, add, v128h, v128h, 1>;
348 def VAF : BinaryVRRc<"vaf", 0xE7F3, add, v128f, v128f, 2>;
349 def VAG : BinaryVRRc<"vag", 0xE7F3, add, v128g, v128g, 3>;
350 def VAQ : BinaryVRRc<"vaq", 0xE7F3, int_s390_vaq, v128q, v128q, 4>;
352 // Add compute carry.
353 def VACCB : BinaryVRRc<"vaccb", 0xE7F1, int_s390_vaccb, v128b, v128b, 0>;
354 def VACCH : BinaryVRRc<"vacch", 0xE7F1, int_s390_vacch, v128h, v128h, 1>;
355 def VACCF : BinaryVRRc<"vaccf", 0xE7F1, int_s390_vaccf, v128f, v128f, 2>;
356 def VACCG : BinaryVRRc<"vaccg", 0xE7F1, int_s390_vaccg, v128g, v128g, 3>;
357 def VACCQ : BinaryVRRc<"vaccq", 0xE7F1, int_s390_vaccq, v128q, v128q, 4>;
360 def VACQ : TernaryVRRd<"vacq", 0xE7BB, int_s390_vacq, v128q, v128q, 4>;
362 // Add with carry compute carry.
363 def VACCCQ : TernaryVRRd<"vacccq", 0xE7B9, int_s390_vacccq, v128q, v128q, 4>;
366 def VN : BinaryVRRc<"vn", 0xE768, null_frag, v128any, v128any>;
368 // And with complement.
369 def VNC : BinaryVRRc<"vnc", 0xE769, null_frag, v128any, v128any>;
372 def VAVGB : BinaryVRRc<"vavgb", 0xE7F2, int_s390_vavgb, v128b, v128b, 0>;
373 def VAVGH : BinaryVRRc<"vavgh", 0xE7F2, int_s390_vavgh, v128h, v128h, 1>;
374 def VAVGF : BinaryVRRc<"vavgf", 0xE7F2, int_s390_vavgf, v128f, v128f, 2>;
375 def VAVGG : BinaryVRRc<"vavgg", 0xE7F2, int_s390_vavgg, v128g, v128g, 3>;
378 def VAVGLB : BinaryVRRc<"vavglb", 0xE7F0, int_s390_vavglb, v128b, v128b, 0>;
379 def VAVGLH : BinaryVRRc<"vavglh", 0xE7F0, int_s390_vavglh, v128h, v128h, 1>;
380 def VAVGLF : BinaryVRRc<"vavglf", 0xE7F0, int_s390_vavglf, v128f, v128f, 2>;
381 def VAVGLG : BinaryVRRc<"vavglg", 0xE7F0, int_s390_vavglg, v128g, v128g, 3>;
384 def VCKSM : BinaryVRRc<"vcksm", 0xE766, int_s390_vcksm, v128f, v128f>;
386 // Count leading zeros.
387 def VCLZB : UnaryVRRa<"vclzb", 0xE753, ctlz, v128b, v128b, 0>;
388 def VCLZH : UnaryVRRa<"vclzh", 0xE753, ctlz, v128h, v128h, 1>;
389 def VCLZF : UnaryVRRa<"vclzf", 0xE753, ctlz, v128f, v128f, 2>;
390 def VCLZG : UnaryVRRa<"vclzg", 0xE753, ctlz, v128g, v128g, 3>;
392 // Count trailing zeros.
393 def VCTZB : UnaryVRRa<"vctzb", 0xE752, cttz, v128b, v128b, 0>;
394 def VCTZH : UnaryVRRa<"vctzh", 0xE752, cttz, v128h, v128h, 1>;
395 def VCTZF : UnaryVRRa<"vctzf", 0xE752, cttz, v128f, v128f, 2>;
396 def VCTZG : UnaryVRRa<"vctzg", 0xE752, cttz, v128g, v128g, 3>;
399 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>;
401 // Galois field multiply sum.
402 def VGFMB : BinaryVRRc<"vgfmb", 0xE7B4, int_s390_vgfmb, v128h, v128b, 0>;
403 def VGFMH : BinaryVRRc<"vgfmh", 0xE7B4, int_s390_vgfmh, v128f, v128h, 1>;
404 def VGFMF : BinaryVRRc<"vgfmf", 0xE7B4, int_s390_vgfmf, v128g, v128f, 2>;
405 def VGFMG : BinaryVRRc<"vgfmg", 0xE7B4, int_s390_vgfmg, v128q, v128g, 3>;
407 // Galois field multiply sum and accumulate.
408 def VGFMAB : TernaryVRRd<"vgfmab", 0xE7BC, int_s390_vgfmab, v128h, v128b, 0>;
409 def VGFMAH : TernaryVRRd<"vgfmah", 0xE7BC, int_s390_vgfmah, v128f, v128h, 1>;
410 def VGFMAF : TernaryVRRd<"vgfmaf", 0xE7BC, int_s390_vgfmaf, v128g, v128f, 2>;
411 def VGFMAG : TernaryVRRd<"vgfmag", 0xE7BC, int_s390_vgfmag, v128q, v128g, 3>;
414 def VLCB : UnaryVRRa<"vlcb", 0xE7DE, z_vneg, v128b, v128b, 0>;
415 def VLCH : UnaryVRRa<"vlch", 0xE7DE, z_vneg, v128h, v128h, 1>;
416 def VLCF : UnaryVRRa<"vlcf", 0xE7DE, z_vneg, v128f, v128f, 2>;
417 def VLCG : UnaryVRRa<"vlcg", 0xE7DE, z_vneg, v128g, v128g, 3>;
420 def VLPB : UnaryVRRa<"vlpb", 0xE7DF, z_viabs8, v128b, v128b, 0>;
421 def VLPH : UnaryVRRa<"vlph", 0xE7DF, z_viabs16, v128h, v128h, 1>;
422 def VLPF : UnaryVRRa<"vlpf", 0xE7DF, z_viabs32, v128f, v128f, 2>;
423 def VLPG : UnaryVRRa<"vlpg", 0xE7DF, z_viabs64, v128g, v128g, 3>;
426 def VMXB : BinaryVRRc<"vmxb", 0xE7FF, null_frag, v128b, v128b, 0>;
427 def VMXH : BinaryVRRc<"vmxh", 0xE7FF, null_frag, v128h, v128h, 1>;
428 def VMXF : BinaryVRRc<"vmxf", 0xE7FF, null_frag, v128f, v128f, 2>;
429 def VMXG : BinaryVRRc<"vmxg", 0xE7FF, null_frag, v128g, v128g, 3>;
432 def VMXLB : BinaryVRRc<"vmxlb", 0xE7FD, null_frag, v128b, v128b, 0>;
433 def VMXLH : BinaryVRRc<"vmxlh", 0xE7FD, null_frag, v128h, v128h, 1>;
434 def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, null_frag, v128f, v128f, 2>;
435 def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, null_frag, v128g, v128g, 3>;
438 def VMNB : BinaryVRRc<"vmnb", 0xE7FE, null_frag, v128b, v128b, 0>;
439 def VMNH : BinaryVRRc<"vmnh", 0xE7FE, null_frag, v128h, v128h, 1>;
440 def VMNF : BinaryVRRc<"vmnf", 0xE7FE, null_frag, v128f, v128f, 2>;
441 def VMNG : BinaryVRRc<"vmng", 0xE7FE, null_frag, v128g, v128g, 3>;
444 def VMNLB : BinaryVRRc<"vmnlb", 0xE7FC, null_frag, v128b, v128b, 0>;
445 def VMNLH : BinaryVRRc<"vmnlh", 0xE7FC, null_frag, v128h, v128h, 1>;
446 def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, null_frag, v128f, v128f, 2>;
447 def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, null_frag, v128g, v128g, 3>;
449 // Multiply and add low.
450 def VMALB : TernaryVRRd<"vmalb", 0xE7AA, z_muladd, v128b, v128b, 0>;
451 def VMALHW : TernaryVRRd<"vmalhw", 0xE7AA, z_muladd, v128h, v128h, 1>;
452 def VMALF : TernaryVRRd<"vmalf", 0xE7AA, z_muladd, v128f, v128f, 2>;
454 // Multiply and add high.
455 def VMAHB : TernaryVRRd<"vmahb", 0xE7AB, int_s390_vmahb, v128b, v128b, 0>;
456 def VMAHH : TernaryVRRd<"vmahh", 0xE7AB, int_s390_vmahh, v128h, v128h, 1>;
457 def VMAHF : TernaryVRRd<"vmahf", 0xE7AB, int_s390_vmahf, v128f, v128f, 2>;
459 // Multiply and add logical high.
460 def VMALHB : TernaryVRRd<"vmalhb", 0xE7A9, int_s390_vmalhb, v128b, v128b, 0>;
461 def VMALHH : TernaryVRRd<"vmalhh", 0xE7A9, int_s390_vmalhh, v128h, v128h, 1>;
462 def VMALHF : TernaryVRRd<"vmalhf", 0xE7A9, int_s390_vmalhf, v128f, v128f, 2>;
464 // Multiply and add even.
465 def VMAEB : TernaryVRRd<"vmaeb", 0xE7AE, int_s390_vmaeb, v128h, v128b, 0>;
466 def VMAEH : TernaryVRRd<"vmaeh", 0xE7AE, int_s390_vmaeh, v128f, v128h, 1>;
467 def VMAEF : TernaryVRRd<"vmaef", 0xE7AE, int_s390_vmaef, v128g, v128f, 2>;
469 // Multiply and add logical even.
470 def VMALEB : TernaryVRRd<"vmaleb", 0xE7AC, int_s390_vmaleb, v128h, v128b, 0>;
471 def VMALEH : TernaryVRRd<"vmaleh", 0xE7AC, int_s390_vmaleh, v128f, v128h, 1>;
472 def VMALEF : TernaryVRRd<"vmalef", 0xE7AC, int_s390_vmalef, v128g, v128f, 2>;
474 // Multiply and add odd.
475 def VMAOB : TernaryVRRd<"vmaob", 0xE7AF, int_s390_vmaob, v128h, v128b, 0>;
476 def VMAOH : TernaryVRRd<"vmaoh", 0xE7AF, int_s390_vmaoh, v128f, v128h, 1>;
477 def VMAOF : TernaryVRRd<"vmaof", 0xE7AF, int_s390_vmaof, v128g, v128f, 2>;
479 // Multiply and add logical odd.
480 def VMALOB : TernaryVRRd<"vmalob", 0xE7AD, int_s390_vmalob, v128h, v128b, 0>;
481 def VMALOH : TernaryVRRd<"vmaloh", 0xE7AD, int_s390_vmaloh, v128f, v128h, 1>;
482 def VMALOF : TernaryVRRd<"vmalof", 0xE7AD, int_s390_vmalof, v128g, v128f, 2>;
485 def VMHB : BinaryVRRc<"vmhb", 0xE7A3, int_s390_vmhb, v128b, v128b, 0>;
486 def VMHH : BinaryVRRc<"vmhh", 0xE7A3, int_s390_vmhh, v128h, v128h, 1>;
487 def VMHF : BinaryVRRc<"vmhf", 0xE7A3, int_s390_vmhf, v128f, v128f, 2>;
489 // Multiply logical high.
490 def VMLHB : BinaryVRRc<"vmlhb", 0xE7A1, int_s390_vmlhb, v128b, v128b, 0>;
491 def VMLHH : BinaryVRRc<"vmlhh", 0xE7A1, int_s390_vmlhh, v128h, v128h, 1>;
492 def VMLHF : BinaryVRRc<"vmlhf", 0xE7A1, int_s390_vmlhf, v128f, v128f, 2>;
495 def VMLB : BinaryVRRc<"vmlb", 0xE7A2, mul, v128b, v128b, 0>;
496 def VMLHW : BinaryVRRc<"vmlhw", 0xE7A2, mul, v128h, v128h, 1>;
497 def VMLF : BinaryVRRc<"vmlf", 0xE7A2, mul, v128f, v128f, 2>;
500 def VMEB : BinaryVRRc<"vmeb", 0xE7A6, int_s390_vmeb, v128h, v128b, 0>;
501 def VMEH : BinaryVRRc<"vmeh", 0xE7A6, int_s390_vmeh, v128f, v128h, 1>;
502 def VMEF : BinaryVRRc<"vmef", 0xE7A6, int_s390_vmef, v128g, v128f, 2>;
504 // Multiply logical even.
505 def VMLEB : BinaryVRRc<"vmleb", 0xE7A4, int_s390_vmleb, v128h, v128b, 0>;
506 def VMLEH : BinaryVRRc<"vmleh", 0xE7A4, int_s390_vmleh, v128f, v128h, 1>;
507 def VMLEF : BinaryVRRc<"vmlef", 0xE7A4, int_s390_vmlef, v128g, v128f, 2>;
510 def VMOB : BinaryVRRc<"vmob", 0xE7A7, int_s390_vmob, v128h, v128b, 0>;
511 def VMOH : BinaryVRRc<"vmoh", 0xE7A7, int_s390_vmoh, v128f, v128h, 1>;
512 def VMOF : BinaryVRRc<"vmof", 0xE7A7, int_s390_vmof, v128g, v128f, 2>;
514 // Multiply logical odd.
515 def VMLOB : BinaryVRRc<"vmlob", 0xE7A5, int_s390_vmlob, v128h, v128b, 0>;
516 def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, int_s390_vmloh, v128f, v128h, 1>;
517 def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, int_s390_vmlof, v128g, v128f, 2>;
520 def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>;
523 def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>;
526 def VPOPCT : BinaryVRRa<"vpopct", 0xE750>;
527 def : Pat<(v16i8 (z_popcnt VR128:$x)), (VPOPCT VR128:$x, 0)>;
529 // Element rotate left logical (with vector shift amount).
530 def VERLLVB : BinaryVRRc<"verllvb", 0xE773, int_s390_verllvb,
532 def VERLLVH : BinaryVRRc<"verllvh", 0xE773, int_s390_verllvh,
534 def VERLLVF : BinaryVRRc<"verllvf", 0xE773, int_s390_verllvf,
536 def VERLLVG : BinaryVRRc<"verllvg", 0xE773, int_s390_verllvg,
539 // Element rotate left logical (with scalar shift amount).
540 def VERLLB : BinaryVRSa<"verllb", 0xE733, int_s390_verllb, v128b, v128b, 0>;
541 def VERLLH : BinaryVRSa<"verllh", 0xE733, int_s390_verllh, v128h, v128h, 1>;
542 def VERLLF : BinaryVRSa<"verllf", 0xE733, int_s390_verllf, v128f, v128f, 2>;
543 def VERLLG : BinaryVRSa<"verllg", 0xE733, int_s390_verllg, v128g, v128g, 3>;
545 // Element rotate and insert under mask.
546 def VERIMB : QuaternaryVRId<"verimb", 0xE772, int_s390_verimb, v128b, v128b, 0>;
547 def VERIMH : QuaternaryVRId<"verimh", 0xE772, int_s390_verimh, v128h, v128h, 1>;
548 def VERIMF : QuaternaryVRId<"verimf", 0xE772, int_s390_verimf, v128f, v128f, 2>;
549 def VERIMG : QuaternaryVRId<"verimg", 0xE772, int_s390_verimg, v128g, v128g, 3>;
551 // Element shift left (with vector shift amount).
552 def VESLVB : BinaryVRRc<"veslvb", 0xE770, z_vshl, v128b, v128b, 0>;
553 def VESLVH : BinaryVRRc<"veslvh", 0xE770, z_vshl, v128h, v128h, 1>;
554 def VESLVF : BinaryVRRc<"veslvf", 0xE770, z_vshl, v128f, v128f, 2>;
555 def VESLVG : BinaryVRRc<"veslvg", 0xE770, z_vshl, v128g, v128g, 3>;
557 // Element shift left (with scalar shift amount).
558 def VESLB : BinaryVRSa<"veslb", 0xE730, z_vshl_by_scalar, v128b, v128b, 0>;
559 def VESLH : BinaryVRSa<"veslh", 0xE730, z_vshl_by_scalar, v128h, v128h, 1>;
560 def VESLF : BinaryVRSa<"veslf", 0xE730, z_vshl_by_scalar, v128f, v128f, 2>;
561 def VESLG : BinaryVRSa<"veslg", 0xE730, z_vshl_by_scalar, v128g, v128g, 3>;
563 // Element shift right arithmetic (with vector shift amount).
564 def VESRAVB : BinaryVRRc<"vesravb", 0xE77A, z_vsra, v128b, v128b, 0>;
565 def VESRAVH : BinaryVRRc<"vesravh", 0xE77A, z_vsra, v128h, v128h, 1>;
566 def VESRAVF : BinaryVRRc<"vesravf", 0xE77A, z_vsra, v128f, v128f, 2>;
567 def VESRAVG : BinaryVRRc<"vesravg", 0xE77A, z_vsra, v128g, v128g, 3>;
569 // Element shift right arithmetic (with scalar shift amount).
570 def VESRAB : BinaryVRSa<"vesrab", 0xE73A, z_vsra_by_scalar, v128b, v128b, 0>;
571 def VESRAH : BinaryVRSa<"vesrah", 0xE73A, z_vsra_by_scalar, v128h, v128h, 1>;
572 def VESRAF : BinaryVRSa<"vesraf", 0xE73A, z_vsra_by_scalar, v128f, v128f, 2>;
573 def VESRAG : BinaryVRSa<"vesrag", 0xE73A, z_vsra_by_scalar, v128g, v128g, 3>;
575 // Element shift right logical (with vector shift amount).
576 def VESRLVB : BinaryVRRc<"vesrlvb", 0xE778, z_vsrl, v128b, v128b, 0>;
577 def VESRLVH : BinaryVRRc<"vesrlvh", 0xE778, z_vsrl, v128h, v128h, 1>;
578 def VESRLVF : BinaryVRRc<"vesrlvf", 0xE778, z_vsrl, v128f, v128f, 2>;
579 def VESRLVG : BinaryVRRc<"vesrlvg", 0xE778, z_vsrl, v128g, v128g, 3>;
581 // Element shift right logical (with scalar shift amount).
582 def VESRLB : BinaryVRSa<"vesrlb", 0xE738, z_vsrl_by_scalar, v128b, v128b, 0>;
583 def VESRLH : BinaryVRSa<"vesrlh", 0xE738, z_vsrl_by_scalar, v128h, v128h, 1>;
584 def VESRLF : BinaryVRSa<"vesrlf", 0xE738, z_vsrl_by_scalar, v128f, v128f, 2>;
585 def VESRLG : BinaryVRSa<"vesrlg", 0xE738, z_vsrl_by_scalar, v128g, v128g, 3>;
588 def VSL : BinaryVRRc<"vsl", 0xE774, int_s390_vsl, v128b, v128b>;
590 // Shift left by byte.
591 def VSLB : BinaryVRRc<"vslb", 0xE775, int_s390_vslb, v128b, v128b>;
593 // Shift left double by byte.
594 def VSLDB : TernaryVRId<"vsldb", 0xE777, z_shl_double, v128b, v128b, 0>;
595 def : Pat<(int_s390_vsldb VR128:$x, VR128:$y, imm32zx8:$z),
596 (VSLDB VR128:$x, VR128:$y, imm32zx8:$z)>;
598 // Shift right arithmetic.
599 def VSRA : BinaryVRRc<"vsra", 0xE77E, int_s390_vsra, v128b, v128b>;
601 // Shift right arithmetic by byte.
602 def VSRAB : BinaryVRRc<"vsrab", 0xE77F, int_s390_vsrab, v128b, v128b>;
604 // Shift right logical.
605 def VSRL : BinaryVRRc<"vsrl", 0xE77C, int_s390_vsrl, v128b, v128b>;
607 // Shift right logical by byte.
608 def VSRLB : BinaryVRRc<"vsrlb", 0xE77D, int_s390_vsrlb, v128b, v128b>;
611 def VSB : BinaryVRRc<"vsb", 0xE7F7, sub, v128b, v128b, 0>;
612 def VSH : BinaryVRRc<"vsh", 0xE7F7, sub, v128h, v128h, 1>;
613 def VSF : BinaryVRRc<"vsf", 0xE7F7, sub, v128f, v128f, 2>;
614 def VSG : BinaryVRRc<"vsg", 0xE7F7, sub, v128g, v128g, 3>;
615 def VSQ : BinaryVRRc<"vsq", 0xE7F7, int_s390_vsq, v128q, v128q, 4>;
617 // Subtract compute borrow indication.
618 def VSCBIB : BinaryVRRc<"vscbib", 0xE7F5, int_s390_vscbib, v128b, v128b, 0>;
619 def VSCBIH : BinaryVRRc<"vscbih", 0xE7F5, int_s390_vscbih, v128h, v128h, 1>;
620 def VSCBIF : BinaryVRRc<"vscbif", 0xE7F5, int_s390_vscbif, v128f, v128f, 2>;
621 def VSCBIG : BinaryVRRc<"vscbig", 0xE7F5, int_s390_vscbig, v128g, v128g, 3>;
622 def VSCBIQ : BinaryVRRc<"vscbiq", 0xE7F5, int_s390_vscbiq, v128q, v128q, 4>;
624 // Subtract with borrow indication.
625 def VSBIQ : TernaryVRRd<"vsbiq", 0xE7BF, int_s390_vsbiq, v128q, v128q, 4>;
627 // Subtract with borrow compute borrow indication.
628 def VSBCBIQ : TernaryVRRd<"vsbcbiq", 0xE7BD, int_s390_vsbcbiq,
631 // Sum across doubleword.
632 def VSUMGH : BinaryVRRc<"vsumgh", 0xE765, z_vsum, v128g, v128h, 1>;
633 def VSUMGF : BinaryVRRc<"vsumgf", 0xE765, z_vsum, v128g, v128f, 2>;
635 // Sum across quadword.
636 def VSUMQF : BinaryVRRc<"vsumqf", 0xE767, z_vsum, v128q, v128f, 2>;
637 def VSUMQG : BinaryVRRc<"vsumqg", 0xE767, z_vsum, v128q, v128g, 3>;
640 def VSUMB : BinaryVRRc<"vsumb", 0xE764, z_vsum, v128f, v128b, 0>;
641 def VSUMH : BinaryVRRc<"vsumh", 0xE764, z_vsum, v128f, v128h, 1>;
644 // Instantiate the bitwise ops for type TYPE.
645 multiclass BitwiseVectorOps<ValueType type> {
646 let Predicates = [FeatureVector] in {
647 def : Pat<(type (and VR128:$x, VR128:$y)), (VN VR128:$x, VR128:$y)>;
648 def : Pat<(type (and VR128:$x, (z_vnot VR128:$y))),
649 (VNC VR128:$x, VR128:$y)>;
650 def : Pat<(type (or VR128:$x, VR128:$y)), (VO VR128:$x, VR128:$y)>;
651 def : Pat<(type (xor VR128:$x, VR128:$y)), (VX VR128:$x, VR128:$y)>;
652 def : Pat<(type (or (and VR128:$x, VR128:$z),
653 (and VR128:$y, (z_vnot VR128:$z)))),
654 (VSEL VR128:$x, VR128:$y, VR128:$z)>;
655 def : Pat<(type (z_vnot (or VR128:$x, VR128:$y))),
656 (VNO VR128:$x, VR128:$y)>;
657 def : Pat<(type (z_vnot VR128:$x)), (VNO VR128:$x, VR128:$x)>;
661 defm : BitwiseVectorOps<v16i8>;
662 defm : BitwiseVectorOps<v8i16>;
663 defm : BitwiseVectorOps<v4i32>;
664 defm : BitwiseVectorOps<v2i64>;
666 // Instantiate additional patterns for absolute-related expressions on
667 // type TYPE. LC is the negate instruction for TYPE and LP is the absolute
669 multiclass IntegerAbsoluteVectorOps<ValueType type, Instruction lc,
670 Instruction lp, int shift> {
671 let Predicates = [FeatureVector] in {
672 def : Pat<(type (vselect (type (z_vicmph_zero VR128:$x)),
673 (z_vneg VR128:$x), VR128:$x)),
675 def : Pat<(type (vselect (type (z_vnot (z_vicmph_zero VR128:$x))),
676 VR128:$x, (z_vneg VR128:$x))),
678 def : Pat<(type (vselect (type (z_vicmpl_zero VR128:$x)),
679 VR128:$x, (z_vneg VR128:$x))),
681 def : Pat<(type (vselect (type (z_vnot (z_vicmpl_zero VR128:$x))),
682 (z_vneg VR128:$x), VR128:$x)),
684 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)),
686 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))),
689 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)),
691 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))),
692 (z_vneg VR128:$x)))),
697 defm : IntegerAbsoluteVectorOps<v16i8, VLCB, VLPB, 7>;
698 defm : IntegerAbsoluteVectorOps<v8i16, VLCH, VLPH, 15>;
699 defm : IntegerAbsoluteVectorOps<v4i32, VLCF, VLPF, 31>;
700 defm : IntegerAbsoluteVectorOps<v2i64, VLCG, VLPG, 63>;
702 // Instantiate minimum- and maximum-related patterns for TYPE. CMPH is the
703 // signed or unsigned "set if greater than" comparison instruction and
704 // MIN and MAX are the associated minimum and maximum instructions.
705 multiclass IntegerMinMaxVectorOps<ValueType type, SDPatternOperator cmph,
706 Instruction min, Instruction max> {
707 let Predicates = [FeatureVector] in {
708 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$x, VR128:$y)),
709 (max VR128:$x, VR128:$y)>;
710 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$y, VR128:$x)),
711 (min VR128:$x, VR128:$y)>;
712 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)),
713 VR128:$x, VR128:$y)),
714 (min VR128:$x, VR128:$y)>;
715 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)),
716 VR128:$y, VR128:$x)),
717 (max VR128:$x, VR128:$y)>;
722 defm : IntegerMinMaxVectorOps<v16i8, z_vicmph, VMNB, VMXB>;
723 defm : IntegerMinMaxVectorOps<v8i16, z_vicmph, VMNH, VMXH>;
724 defm : IntegerMinMaxVectorOps<v4i32, z_vicmph, VMNF, VMXF>;
725 defm : IntegerMinMaxVectorOps<v2i64, z_vicmph, VMNG, VMXG>;
728 defm : IntegerMinMaxVectorOps<v16i8, z_vicmphl, VMNLB, VMXLB>;
729 defm : IntegerMinMaxVectorOps<v8i16, z_vicmphl, VMNLH, VMXLH>;
730 defm : IntegerMinMaxVectorOps<v4i32, z_vicmphl, VMNLF, VMXLF>;
731 defm : IntegerMinMaxVectorOps<v2i64, z_vicmphl, VMNLG, VMXLG>;
733 //===----------------------------------------------------------------------===//
734 // Integer comparison
735 //===----------------------------------------------------------------------===//
737 let Predicates = [FeatureVector] in {
740 def VECB : CompareVRRa<"vecb", 0xE7DB, null_frag, v128b, 0>;
741 def VECH : CompareVRRa<"vech", 0xE7DB, null_frag, v128h, 1>;
742 def VECF : CompareVRRa<"vecf", 0xE7DB, null_frag, v128f, 2>;
743 def VECG : CompareVRRa<"vecg", 0xE7DB, null_frag, v128g, 3>;
746 // Element compare logical.
748 def VECLB : CompareVRRa<"veclb", 0xE7D9, null_frag, v128b, 0>;
749 def VECLH : CompareVRRa<"veclh", 0xE7D9, null_frag, v128h, 1>;
750 def VECLF : CompareVRRa<"veclf", 0xE7D9, null_frag, v128f, 2>;
751 def VECLG : CompareVRRa<"veclg", 0xE7D9, null_frag, v128g, 3>;
755 defm VCEQB : BinaryVRRbSPair<"vceqb", 0xE7F8, z_vicmpe, z_vicmpes,
757 defm VCEQH : BinaryVRRbSPair<"vceqh", 0xE7F8, z_vicmpe, z_vicmpes,
759 defm VCEQF : BinaryVRRbSPair<"vceqf", 0xE7F8, z_vicmpe, z_vicmpes,
761 defm VCEQG : BinaryVRRbSPair<"vceqg", 0xE7F8, z_vicmpe, z_vicmpes,
765 defm VCHB : BinaryVRRbSPair<"vchb", 0xE7FB, z_vicmph, z_vicmphs,
767 defm VCHH : BinaryVRRbSPair<"vchh", 0xE7FB, z_vicmph, z_vicmphs,
769 defm VCHF : BinaryVRRbSPair<"vchf", 0xE7FB, z_vicmph, z_vicmphs,
771 defm VCHG : BinaryVRRbSPair<"vchg", 0xE7FB, z_vicmph, z_vicmphs,
774 // Compare high logical.
775 defm VCHLB : BinaryVRRbSPair<"vchlb", 0xE7F9, z_vicmphl, z_vicmphls,
777 defm VCHLH : BinaryVRRbSPair<"vchlh", 0xE7F9, z_vicmphl, z_vicmphls,
779 defm VCHLF : BinaryVRRbSPair<"vchlf", 0xE7F9, z_vicmphl, z_vicmphls,
781 defm VCHLG : BinaryVRRbSPair<"vchlg", 0xE7F9, z_vicmphl, z_vicmphls,
786 def VTM : CompareVRRa<"vtm", 0xE7D8, z_vtm, v128b, 0>;
789 //===----------------------------------------------------------------------===//
790 // Floating-point arithmetic
791 //===----------------------------------------------------------------------===//
793 // See comments in SystemZInstrFP.td for the suppression flags and
795 multiclass VectorRounding<Instruction insn, TypedReg tr> {
796 def : FPConversion<insn, frint, tr, tr, 0, 0>;
797 def : FPConversion<insn, fnearbyint, tr, tr, 4, 0>;
798 def : FPConversion<insn, ffloor, tr, tr, 4, 7>;
799 def : FPConversion<insn, fceil, tr, tr, 4, 6>;
800 def : FPConversion<insn, ftrunc, tr, tr, 4, 5>;
801 def : FPConversion<insn, frnd, tr, tr, 4, 1>;
804 let Predicates = [FeatureVector] in {
806 def VFADB : BinaryVRRc<"vfadb", 0xE7E3, fadd, v128db, v128db, 3, 0>;
807 def WFADB : BinaryVRRc<"wfadb", 0xE7E3, fadd, v64db, v64db, 3, 8>;
809 // Convert from fixed 64-bit.
810 def VCDGB : TernaryVRRa<"vcdgb", 0xE7C3, null_frag, v128db, v128g, 3, 0>;
811 def WCDGB : TernaryVRRa<"wcdgb", 0xE7C3, null_frag, v64db, v64g, 3, 8>;
812 def : FPConversion<VCDGB, sint_to_fp, v128db, v128g, 0, 0>;
814 // Convert from logical 64-bit.
815 def VCDLGB : TernaryVRRa<"vcdlgb", 0xE7C1, null_frag, v128db, v128g, 3, 0>;
816 def WCDLGB : TernaryVRRa<"wcdlgb", 0xE7C1, null_frag, v64db, v64g, 3, 8>;
817 def : FPConversion<VCDLGB, uint_to_fp, v128db, v128g, 0, 0>;
819 // Convert to fixed 64-bit.
820 def VCGDB : TernaryVRRa<"vcgdb", 0xE7C2, null_frag, v128g, v128db, 3, 0>;
821 def WCGDB : TernaryVRRa<"wcgdb", 0xE7C2, null_frag, v64g, v64db, 3, 8>;
822 // Rounding mode should agree with SystemZInstrFP.td.
823 def : FPConversion<VCGDB, fp_to_sint, v128g, v128db, 0, 5>;
825 // Convert to logical 64-bit.
826 def VCLGDB : TernaryVRRa<"vclgdb", 0xE7C0, null_frag, v128g, v128db, 3, 0>;
827 def WCLGDB : TernaryVRRa<"wclgdb", 0xE7C0, null_frag, v64g, v64db, 3, 8>;
828 // Rounding mode should agree with SystemZInstrFP.td.
829 def : FPConversion<VCLGDB, fp_to_uint, v128g, v128db, 0, 5>;
832 def VFDDB : BinaryVRRc<"vfddb", 0xE7E5, fdiv, v128db, v128db, 3, 0>;
833 def WFDDB : BinaryVRRc<"wfddb", 0xE7E5, fdiv, v64db, v64db, 3, 8>;
836 def VFIDB : TernaryVRRa<"vfidb", 0xE7C7, int_s390_vfidb, v128db, v128db, 3, 0>;
837 def WFIDB : TernaryVRRa<"wfidb", 0xE7C7, null_frag, v64db, v64db, 3, 8>;
838 defm : VectorRounding<VFIDB, v128db>;
839 defm : VectorRounding<WFIDB, v64db>;
842 def VLDEB : UnaryVRRa<"vldeb", 0xE7C4, z_vextend, v128db, v128eb, 2, 0>;
843 def WLDEB : UnaryVRRa<"wldeb", 0xE7C4, fextend, v64db, v32eb, 2, 8>;
846 def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128eb, v128db, 3, 0>;
847 def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32eb, v64db, 3, 8>;
848 def : Pat<(v4f32 (z_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>;
849 def : FPConversion<WLEDB, fround, v32eb, v64db, 0, 0>;
852 def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, fmul, v128db, v128db, 3, 0>;
853 def WFMDB : BinaryVRRc<"wfmdb", 0xE7E7, fmul, v64db, v64db, 3, 8>;
856 def VFMADB : TernaryVRRe<"vfmadb", 0xE78F, fma, v128db, v128db, 0, 3>;
857 def WFMADB : TernaryVRRe<"wfmadb", 0xE78F, fma, v64db, v64db, 8, 3>;
859 // Multiply and subtract.
860 def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, fms, v128db, v128db, 0, 3>;
861 def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, fms, v64db, v64db, 8, 3>;
864 def VFLCDB : UnaryVRRa<"vflcdb", 0xE7CC, fneg, v128db, v128db, 3, 0, 0>;
865 def WFLCDB : UnaryVRRa<"wflcdb", 0xE7CC, fneg, v64db, v64db, 3, 8, 0>;
868 def VFLNDB : UnaryVRRa<"vflndb", 0xE7CC, fnabs, v128db, v128db, 3, 0, 1>;
869 def WFLNDB : UnaryVRRa<"wflndb", 0xE7CC, fnabs, v64db, v64db, 3, 8, 1>;
872 def VFLPDB : UnaryVRRa<"vflpdb", 0xE7CC, fabs, v128db, v128db, 3, 0, 2>;
873 def WFLPDB : UnaryVRRa<"wflpdb", 0xE7CC, fabs, v64db, v64db, 3, 8, 2>;
876 def VFSQDB : UnaryVRRa<"vfsqdb", 0xE7CE, fsqrt, v128db, v128db, 3, 0>;
877 def WFSQDB : UnaryVRRa<"wfsqdb", 0xE7CE, fsqrt, v64db, v64db, 3, 8>;
880 def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, fsub, v128db, v128db, 3, 0>;
881 def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, fsub, v64db, v64db, 3, 8>;
883 // Test data class immediate.
885 def VFTCIDB : BinaryVRIe<"vftcidb", 0xE74A, z_vftci, v128g, v128db, 3, 0>;
886 def WFTCIDB : BinaryVRIe<"wftcidb", 0xE74A, null_frag, v64g, v64db, 3, 8>;
890 //===----------------------------------------------------------------------===//
891 // Floating-point comparison
892 //===----------------------------------------------------------------------===//
894 let Predicates = [FeatureVector] in {
897 def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, z_fcmp, v64db, 3>;
899 // Compare and signal scalar.
901 def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, null_frag, v64db, 3>;
904 defm VFCEDB : BinaryVRRcSPair<"vfcedb", 0xE7E8, z_vfcmpe, z_vfcmpes,
905 v128g, v128db, 3, 0>;
906 defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag,
910 defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, z_vfcmph, z_vfcmphs,
911 v128g, v128db, 3, 0>;
912 defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag,
915 // Compare high or equal.
916 defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, z_vfcmphe, z_vfcmphes,
917 v128g, v128db, 3, 0>;
918 defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag,
922 //===----------------------------------------------------------------------===//
924 //===----------------------------------------------------------------------===//
926 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
927 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
928 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
929 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
930 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
932 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
933 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
934 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
935 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
936 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
938 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
939 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
940 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
941 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
942 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
944 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
945 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
946 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
947 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
948 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
950 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
951 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
952 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
953 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
954 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
956 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
957 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
958 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
959 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
960 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
962 //===----------------------------------------------------------------------===//
963 // Replicating scalars
964 //===----------------------------------------------------------------------===//
966 // Define patterns for replicating a scalar GR32 into a vector of type TYPE.
967 // INDEX is 8 minus the element size in bytes.
968 class VectorReplicateScalar<ValueType type, Instruction insn, bits<16> index>
969 : Pat<(type (z_replicate GR32:$scalar)),
970 (insn (VLVGP32 GR32:$scalar, GR32:$scalar), index)>;
972 def : VectorReplicateScalar<v16i8, VREPB, 7>;
973 def : VectorReplicateScalar<v8i16, VREPH, 3>;
974 def : VectorReplicateScalar<v4i32, VREPF, 1>;
976 // i64 replications are just a single isntruction.
977 def : Pat<(v2i64 (z_replicate GR64:$scalar)),
978 (VLVGP GR64:$scalar, GR64:$scalar)>;
980 //===----------------------------------------------------------------------===//
981 // Floating-point insertion and extraction
982 //===----------------------------------------------------------------------===//
984 // Moving 32-bit values between GPRs and FPRs can be done using VLVGF
986 def LEFR : UnaryAliasVRS<VR32, GR32>;
987 def LFER : UnaryAliasVRS<GR64, VR32>;
988 def : Pat<(f32 (bitconvert (i32 GR32:$src))), (LEFR GR32:$src)>;
989 def : Pat<(i32 (bitconvert (f32 VR32:$src))),
990 (EXTRACT_SUBREG (LFER VR32:$src), subreg_l32)>;
992 // Floating-point values are stored in element 0 of the corresponding
993 // vector register. Scalar to vector conversion is just a subreg and
994 // scalar replication can just replicate element 0 of the vector register.
995 multiclass ScalarToVectorFP<Instruction vrep, ValueType vt, RegisterOperand cls,
996 SubRegIndex subreg> {
997 def : Pat<(vt (scalar_to_vector cls:$scalar)),
998 (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg)>;
999 def : Pat<(vt (z_replicate cls:$scalar)),
1000 (vrep (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar,
1003 defm : ScalarToVectorFP<VREPF, v4f32, FP32, subreg_r32>;
1004 defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_r64>;
1006 // Match v2f64 insertions. The AddedComplexity counters the 3 added by
1007 // TableGen for the base register operand in VLVG-based integer insertions
1008 // and ensures that this version is strictly better.
1009 let AddedComplexity = 4 in {
1010 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0),
1011 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
1012 subreg_r64), VR128:$vec, 1)>;
1013 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1),
1014 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
1018 // We extract floating-point element X by replicating (for elements other
1019 // than 0) and then taking a high subreg. The AddedComplexity counters the
1020 // 3 added by TableGen for the base register operand in VLGV-based integer
1021 // extractions and ensures that this version is strictly better.
1022 let AddedComplexity = 4 in {
1023 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), 0)),
1024 (EXTRACT_SUBREG VR128:$vec, subreg_r32)>;
1025 def : Pat<(f32 (z_vector_extract (v4f32 VR128:$vec), imm32zx2:$index)),
1026 (EXTRACT_SUBREG (VREPF VR128:$vec, imm32zx2:$index), subreg_r32)>;
1028 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), 0)),
1029 (EXTRACT_SUBREG VR128:$vec, subreg_r64)>;
1030 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), imm32zx1:$index)),
1031 (EXTRACT_SUBREG (VREPG VR128:$vec, imm32zx1:$index), subreg_r64)>;
1034 //===----------------------------------------------------------------------===//
1035 // String instructions
1036 //===----------------------------------------------------------------------===//
1038 let Predicates = [FeatureVector] in {
1039 defm VFAEB : TernaryVRRbSPair<"vfaeb", 0xE782, int_s390_vfaeb, z_vfae_cc,
1040 v128b, v128b, 0, 0>;
1041 defm VFAEH : TernaryVRRbSPair<"vfaeh", 0xE782, int_s390_vfaeh, z_vfae_cc,
1042 v128h, v128h, 1, 0>;
1043 defm VFAEF : TernaryVRRbSPair<"vfaef", 0xE782, int_s390_vfaef, z_vfae_cc,
1044 v128f, v128f, 2, 0>;
1045 defm VFAEZB : TernaryVRRbSPair<"vfaezb", 0xE782, int_s390_vfaezb, z_vfaez_cc,
1046 v128b, v128b, 0, 2>;
1047 defm VFAEZH : TernaryVRRbSPair<"vfaezh", 0xE782, int_s390_vfaezh, z_vfaez_cc,
1048 v128h, v128h, 1, 2>;
1049 defm VFAEZF : TernaryVRRbSPair<"vfaezf", 0xE782, int_s390_vfaezf, z_vfaez_cc,
1050 v128f, v128f, 2, 2>;
1052 defm VFEEB : BinaryVRRbSPair<"vfeeb", 0xE780, int_s390_vfeeb, z_vfee_cc,
1053 v128b, v128b, 0, 0, 1>;
1054 defm VFEEH : BinaryVRRbSPair<"vfeeh", 0xE780, int_s390_vfeeh, z_vfee_cc,
1055 v128h, v128h, 1, 0, 1>;
1056 defm VFEEF : BinaryVRRbSPair<"vfeef", 0xE780, int_s390_vfeef, z_vfee_cc,
1057 v128f, v128f, 2, 0, 1>;
1058 defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, int_s390_vfeezb, z_vfeez_cc,
1059 v128b, v128b, 0, 2, 3>;
1060 defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, int_s390_vfeezh, z_vfeez_cc,
1061 v128h, v128h, 1, 2, 3>;
1062 defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, int_s390_vfeezf, z_vfeez_cc,
1063 v128f, v128f, 2, 2, 3>;
1065 defm VFENEB : BinaryVRRbSPair<"vfeneb", 0xE781, int_s390_vfeneb, z_vfene_cc,
1066 v128b, v128b, 0, 0, 1>;
1067 defm VFENEH : BinaryVRRbSPair<"vfeneh", 0xE781, int_s390_vfeneh, z_vfene_cc,
1068 v128h, v128h, 1, 0, 1>;
1069 defm VFENEF : BinaryVRRbSPair<"vfenef", 0xE781, int_s390_vfenef, z_vfene_cc,
1070 v128f, v128f, 2, 0, 1>;
1071 defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, int_s390_vfenezb,
1072 z_vfenez_cc, v128b, v128b, 0, 2, 3>;
1073 defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, int_s390_vfenezh,
1074 z_vfenez_cc, v128h, v128h, 1, 2, 3>;
1075 defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, int_s390_vfenezf,
1076 z_vfenez_cc, v128f, v128f, 2, 2, 3>;
1078 defm VISTRB : UnaryVRRaSPair<"vistrb", 0xE75C, int_s390_vistrb, z_vistr_cc,
1080 defm VISTRH : UnaryVRRaSPair<"vistrh", 0xE75C, int_s390_vistrh, z_vistr_cc,
1082 defm VISTRF : UnaryVRRaSPair<"vistrf", 0xE75C, int_s390_vistrf, z_vistr_cc,
1085 defm VSTRCB : QuaternaryVRRdSPair<"vstrcb", 0xE78A, int_s390_vstrcb,
1086 z_vstrc_cc, v128b, v128b, 0, 0>;
1087 defm VSTRCH : QuaternaryVRRdSPair<"vstrch", 0xE78A, int_s390_vstrch,
1088 z_vstrc_cc, v128h, v128h, 1, 0>;
1089 defm VSTRCF : QuaternaryVRRdSPair<"vstrcf", 0xE78A, int_s390_vstrcf,
1090 z_vstrc_cc, v128f, v128f, 2, 0>;
1091 defm VSTRCZB : QuaternaryVRRdSPair<"vstrczb", 0xE78A, int_s390_vstrczb,
1092 z_vstrcz_cc, v128b, v128b, 0, 2>;
1093 defm VSTRCZH : QuaternaryVRRdSPair<"vstrczh", 0xE78A, int_s390_vstrczh,
1094 z_vstrcz_cc, v128h, v128h, 1, 2>;
1095 defm VSTRCZF : QuaternaryVRRdSPair<"vstrczf", 0xE78A, int_s390_vstrczf,
1096 z_vstrcz_cc, v128f, v128f, 2, 2>;