1 //==- SystemZInstrVector.td - SystemZ Vector instructions ------*- tblgen-*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 let Predicates = [FeatureVector] in {
16 def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>;
18 // Load GR from VR element.
19 def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>;
20 def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>;
21 def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>;
22 def VLGVG : BinaryVRSc<"vlgvg", 0xE721, z_vector_extract, v128g, 3>;
24 // Load VR element from GR.
25 def VLVGB : TernaryVRSb<"vlvgb", 0xE722, z_vector_insert,
26 v128b, v128b, GR32, 0>;
27 def VLVGH : TernaryVRSb<"vlvgh", 0xE722, z_vector_insert,
28 v128h, v128h, GR32, 1>;
29 def VLVGF : TernaryVRSb<"vlvgf", 0xE722, z_vector_insert,
30 v128f, v128f, GR32, 2>;
31 def VLVGG : TernaryVRSb<"vlvgg", 0xE722, z_vector_insert,
32 v128g, v128g, GR64, 3>;
34 // Load VR from GRs disjoint.
35 def VLVGP : BinaryVRRf<"vlvgp", 0xE762, z_join_dwords, v128g>;
36 def VLVGP32 : BinaryAliasVRRf<GR32>;
39 // Extractions always assign to the full GR64, even if the element would
40 // fit in the lower 32 bits. Sub-i64 extracts therefore need to take a
41 // subreg of the result.
42 class VectorExtractSubreg<ValueType type, Instruction insn>
43 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)),
44 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>;
46 def : VectorExtractSubreg<v16i8, VLGVB>;
47 def : VectorExtractSubreg<v8i16, VLGVH>;
48 def : VectorExtractSubreg<v4i32, VLGVF>;
50 //===----------------------------------------------------------------------===//
51 // Immediate instructions
52 //===----------------------------------------------------------------------===//
54 let Predicates = [FeatureVector] in {
55 // Generate byte mask.
56 def VZERO : InherentVRIa<"vzero", 0xE744, 0>;
57 def VONE : InherentVRIa<"vone", 0xE744, 0xffff>;
58 def VGBM : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16>;
61 def VGMB : BinaryVRIb<"vgmb", 0xE746, z_rotate_mask, v128b, 0>;
62 def VGMH : BinaryVRIb<"vgmh", 0xE746, z_rotate_mask, v128h, 1>;
63 def VGMF : BinaryVRIb<"vgmf", 0xE746, z_rotate_mask, v128f, 2>;
64 def VGMG : BinaryVRIb<"vgmg", 0xE746, z_rotate_mask, v128g, 3>;
66 // Load element immediate.
68 // We want these instructions to be used ahead of VLVG* where possible.
69 // However, VLVG* takes a variable BD-format index whereas VLEI takes
70 // a plain immediate index. This means that VLVG* has an extra "base"
71 // register operand and is 3 units more complex. Bumping the complexity
72 // of the VLEI* instructions by 4 means that they are strictly better
73 // than VLVG* in cases where both forms match.
74 let AddedComplexity = 4 in {
75 def VLEIB : TernaryVRIa<"vleib", 0xE740, z_vector_insert,
76 v128b, v128b, imm32sx16trunc, imm32zx4>;
77 def VLEIH : TernaryVRIa<"vleih", 0xE741, z_vector_insert,
78 v128h, v128h, imm32sx16trunc, imm32zx3>;
79 def VLEIF : TernaryVRIa<"vleif", 0xE743, z_vector_insert,
80 v128f, v128f, imm32sx16, imm32zx2>;
81 def VLEIG : TernaryVRIa<"vleig", 0xE742, z_vector_insert,
82 v128g, v128g, imm64sx16, imm32zx1>;
85 // Replicate immediate.
86 def VREPIB : UnaryVRIa<"vrepib", 0xE745, z_replicate, v128b, imm32sx16, 0>;
87 def VREPIH : UnaryVRIa<"vrepih", 0xE745, z_replicate, v128h, imm32sx16, 1>;
88 def VREPIF : UnaryVRIa<"vrepif", 0xE745, z_replicate, v128f, imm32sx16, 2>;
89 def VREPIG : UnaryVRIa<"vrepig", 0xE745, z_replicate, v128g, imm32sx16, 3>;
92 //===----------------------------------------------------------------------===//
94 //===----------------------------------------------------------------------===//
96 let Predicates = [FeatureVector] in {
98 def VL : UnaryVRX<"vl", 0xE706, null_frag, v128any, 16>;
100 // Load to block boundary. The number of loaded bytes is only known
102 def VLBB : BinaryVRX<"vlbb", 0xE707, null_frag, v128any, 0>;
104 // Load count to block boundary.
106 def LCBB : InstRXE<0xE727, (outs GR32:$R1),
107 (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
108 "lcbb\t$R1, $XBD2, $M3", []>;
110 // Load with length. The number of loaded bytes is only known at run time.
111 def VLL : BinaryVRSb<"vll", 0xE737, null_frag, 0>;
114 def VLM : LoadMultipleVRSa<"vlm", 0xE736>;
116 // Load and replicate
117 def VLREPB : UnaryVRX<"vlrepb", 0xE705, z_replicate_loadi8, v128b, 1, 0>;
118 def VLREPH : UnaryVRX<"vlreph", 0xE705, z_replicate_loadi16, v128h, 2, 1>;
119 def VLREPF : UnaryVRX<"vlrepf", 0xE705, z_replicate_loadi32, v128f, 4, 2>;
120 def VLREPG : UnaryVRX<"vlrepg", 0xE705, z_replicate_loadi64, v128g, 8, 3>;
121 def : Pat<(v2f64 (z_replicate_loadf64 bdxaddr12only:$addr)),
122 (VLREPG bdxaddr12only:$addr)>;
124 // Load logical element and zero.
125 def VLLEZB : UnaryVRX<"vllezb", 0xE704, z_vllezi8, v128b, 1, 0>;
126 def VLLEZH : UnaryVRX<"vllezh", 0xE704, z_vllezi16, v128h, 2, 1>;
127 def VLLEZF : UnaryVRX<"vllezf", 0xE704, z_vllezi32, v128f, 4, 2>;
128 def VLLEZG : UnaryVRX<"vllezg", 0xE704, z_vllezi64, v128g, 8, 3>;
129 def : Pat<(v2f64 (z_vllezf64 bdxaddr12only:$addr)),
130 (VLLEZG bdxaddr12only:$addr)>;
133 def VLEB : TernaryVRX<"vleb", 0xE700, z_vlei8, v128b, v128b, 1, imm32zx4>;
134 def VLEH : TernaryVRX<"vleh", 0xE701, z_vlei16, v128h, v128h, 2, imm32zx3>;
135 def VLEF : TernaryVRX<"vlef", 0xE703, z_vlei32, v128f, v128f, 4, imm32zx2>;
136 def VLEG : TernaryVRX<"vleg", 0xE702, z_vlei64, v128g, v128g, 8, imm32zx1>;
137 def : Pat<(z_vlef64 (v2f64 VR128:$val), bdxaddr12only:$addr, imm32zx1:$index),
138 (VLEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;
141 def VGEF : TernaryVRV<"vgef", 0xE713, 4, imm32zx2>;
142 def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>;
145 // Use replicating loads if we're inserting a single element into an
146 // undefined vector. This avoids a false dependency on the previous
147 // register contents.
148 multiclass ReplicatePeephole<Instruction vlrep, ValueType vectype,
149 SDPatternOperator load, ValueType scalartype> {
150 def : Pat<(vectype (z_vector_insert
151 (undef), (scalartype (load bdxaddr12only:$addr)), 0)),
152 (vlrep bdxaddr12only:$addr)>;
153 def : Pat<(vectype (scalar_to_vector
154 (scalartype (load bdxaddr12only:$addr)))),
155 (vlrep bdxaddr12only:$addr)>;
157 defm : ReplicatePeephole<VLREPB, v16i8, anyextloadi8, i32>;
158 defm : ReplicatePeephole<VLREPH, v8i16, anyextloadi16, i32>;
159 defm : ReplicatePeephole<VLREPF, v4i32, load, i32>;
160 defm : ReplicatePeephole<VLREPG, v2i64, load, i64>;
161 defm : ReplicatePeephole<VLREPG, v2f64, load, f64>;
163 //===----------------------------------------------------------------------===//
165 //===----------------------------------------------------------------------===//
167 let Predicates = [FeatureVector] in {
169 def VST : StoreVRX<"vst", 0xE70E, null_frag, v128any, 16>;
171 // Store with length. The number of stored bytes is only known at run time.
172 def VSTL : StoreLengthVRSb<"vstl", 0xE73F, null_frag, 0>;
175 def VSTM : StoreMultipleVRSa<"vstm", 0xE73E>;
178 def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, z_vstei8, v128b, 1, imm32zx4>;
179 def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, z_vstei16, v128h, 2, imm32zx3>;
180 def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, z_vstei32, v128f, 4, imm32zx2>;
181 def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, z_vstei64, v128g, 8, imm32zx1>;
182 def : Pat<(z_vstef64 (v2f64 VR128:$val), bdxaddr12only:$addr,
184 (VSTEG VR128:$val, bdxaddr12only:$addr, imm32zx1:$index)>;
187 def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>;
188 def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>;
191 //===----------------------------------------------------------------------===//
192 // Selects and permutes
193 //===----------------------------------------------------------------------===//
195 let Predicates = [FeatureVector] in {
197 def VMRHB : BinaryVRRc<"vmrhb", 0xE761, z_merge_high, v128b, v128b, 0>;
198 def VMRHH : BinaryVRRc<"vmrhh", 0xE761, z_merge_high, v128h, v128h, 1>;
199 def VMRHF : BinaryVRRc<"vmrhf", 0xE761, z_merge_high, v128f, v128f, 2>;
200 def VMRHG : BinaryVRRc<"vmrhg", 0xE761, z_merge_high, v128g, v128g, 3>;
201 def : BinaryRRWithType<VMRHG, VR128, z_merge_high, v2f64>;
204 def VMRLB : BinaryVRRc<"vmrlb", 0xE760, z_merge_low, v128b, v128b, 0>;
205 def VMRLH : BinaryVRRc<"vmrlh", 0xE760, z_merge_low, v128h, v128h, 1>;
206 def VMRLF : BinaryVRRc<"vmrlf", 0xE760, z_merge_low, v128f, v128f, 2>;
207 def VMRLG : BinaryVRRc<"vmrlg", 0xE760, z_merge_low, v128g, v128g, 3>;
208 def : BinaryRRWithType<VMRLG, VR128, z_merge_low, v2f64>;
211 def VPERM : TernaryVRRe<"vperm", 0xE78C, z_permute, v128b, v128b>;
213 // Permute doubleword immediate.
214 def VPDI : TernaryVRRc<"vpdi", 0xE784, z_permute_dwords, v128g, v128g>;
217 def VREPB : BinaryVRIc<"vrepb", 0xE74D, z_splat, v128b, v128b, 0>;
218 def VREPH : BinaryVRIc<"vreph", 0xE74D, z_splat, v128h, v128h, 1>;
219 def VREPF : BinaryVRIc<"vrepf", 0xE74D, z_splat, v128f, v128f, 2>;
220 def VREPG : BinaryVRIc<"vrepg", 0xE74D, z_splat, v128g, v128g, 3>;
221 def : Pat<(v2f64 (z_splat VR128:$vec, imm32zx16:$index)),
222 (VREPG VR128:$vec, imm32zx16:$index)>;
225 def VSEL : TernaryVRRe<"vsel", 0xE78D, null_frag, v128any, v128any>;
228 //===----------------------------------------------------------------------===//
229 // Widening and narrowing
230 //===----------------------------------------------------------------------===//
232 let Predicates = [FeatureVector] in {
234 def VPKH : BinaryVRRc<"vpkh", 0xE794, z_pack, v128b, v128h, 1>;
235 def VPKF : BinaryVRRc<"vpkf", 0xE794, z_pack, v128h, v128f, 2>;
236 def VPKG : BinaryVRRc<"vpkg", 0xE794, z_pack, v128f, v128g, 3>;
239 defm VPKSH : BinaryVRRbSPair<"vpksh", 0xE797, null_frag, null_frag,
241 defm VPKSF : BinaryVRRbSPair<"vpksf", 0xE797, null_frag, null_frag,
243 defm VPKSG : BinaryVRRbSPair<"vpksg", 0xE797, null_frag, null_frag,
246 // Pack saturate logical.
247 defm VPKLSH : BinaryVRRbSPair<"vpklsh", 0xE795, null_frag, null_frag,
249 defm VPKLSF : BinaryVRRbSPair<"vpklsf", 0xE795, null_frag, null_frag,
251 defm VPKLSG : BinaryVRRbSPair<"vpklsg", 0xE795, null_frag, null_frag,
254 // Sign-extend to doubleword.
255 def VSEGB : UnaryVRRa<"vsegb", 0xE75F, z_vsei8, v128g, v128g, 0>;
256 def VSEGH : UnaryVRRa<"vsegh", 0xE75F, z_vsei16, v128g, v128g, 1>;
257 def VSEGF : UnaryVRRa<"vsegf", 0xE75F, z_vsei32, v128g, v128g, 2>;
258 def : Pat<(z_vsei8_by_parts (v16i8 VR128:$src)), (VSEGB VR128:$src)>;
259 def : Pat<(z_vsei16_by_parts (v8i16 VR128:$src)), (VSEGH VR128:$src)>;
260 def : Pat<(z_vsei32_by_parts (v4i32 VR128:$src)), (VSEGF VR128:$src)>;
263 def VUPHB : UnaryVRRa<"vuphb", 0xE7D7, null_frag, v128h, v128b, 0>;
264 def VUPHH : UnaryVRRa<"vuphh", 0xE7D7, null_frag, v128f, v128h, 1>;
265 def VUPHF : UnaryVRRa<"vuphf", 0xE7D7, null_frag, v128g, v128f, 2>;
267 // Unpack logical high.
268 def VUPLHB : UnaryVRRa<"vuplhb", 0xE7D5, null_frag, v128h, v128b, 0>;
269 def VUPLHH : UnaryVRRa<"vuplhh", 0xE7D5, null_frag, v128f, v128h, 1>;
270 def VUPLHF : UnaryVRRa<"vuplhf", 0xE7D5, null_frag, v128g, v128f, 2>;
273 def VUPLB : UnaryVRRa<"vuplb", 0xE7D6, null_frag, v128h, v128b, 0>;
274 def VUPLHW : UnaryVRRa<"vuplhw", 0xE7D6, null_frag, v128f, v128h, 1>;
275 def VUPLF : UnaryVRRa<"vuplf", 0xE7D6, null_frag, v128g, v128f, 2>;
277 // Unpack logical low.
278 def VUPLLB : UnaryVRRa<"vupllb", 0xE7D4, null_frag, v128h, v128b, 0>;
279 def VUPLLH : UnaryVRRa<"vupllh", 0xE7D4, null_frag, v128f, v128h, 1>;
280 def VUPLLF : UnaryVRRa<"vupllf", 0xE7D4, null_frag, v128g, v128f, 2>;
283 //===----------------------------------------------------------------------===//
284 // Instantiating generic operations for specific types.
285 //===----------------------------------------------------------------------===//
287 multiclass GenericVectorOps<ValueType type, ValueType inttype> {
288 let Predicates = [FeatureVector] in {
289 def : Pat<(type (load bdxaddr12only:$addr)),
290 (VL bdxaddr12only:$addr)>;
291 def : Pat<(store (type VR128:$src), bdxaddr12only:$addr),
292 (VST VR128:$src, bdxaddr12only:$addr)>;
293 def : Pat<(type (vselect (inttype VR128:$x), VR128:$y, VR128:$z)),
294 (VSEL VR128:$y, VR128:$z, VR128:$x)>;
295 def : Pat<(type (vselect (inttype (z_vnot VR128:$x)), VR128:$y, VR128:$z)),
296 (VSEL VR128:$z, VR128:$y, VR128:$x)>;
300 defm : GenericVectorOps<v16i8, v16i8>;
301 defm : GenericVectorOps<v8i16, v8i16>;
302 defm : GenericVectorOps<v4i32, v4i32>;
303 defm : GenericVectorOps<v2i64, v2i64>;
304 defm : GenericVectorOps<v2f64, v2i64>;
306 //===----------------------------------------------------------------------===//
307 // Integer arithmetic
308 //===----------------------------------------------------------------------===//
310 let Predicates = [FeatureVector] in {
312 def VAB : BinaryVRRc<"vab", 0xE7F3, add, v128b, v128b, 0>;
313 def VAH : BinaryVRRc<"vah", 0xE7F3, add, v128h, v128h, 1>;
314 def VAF : BinaryVRRc<"vaf", 0xE7F3, add, v128f, v128f, 2>;
315 def VAG : BinaryVRRc<"vag", 0xE7F3, add, v128g, v128g, 3>;
316 def VAQ : BinaryVRRc<"vaq", 0xE7F3, null_frag, v128q, v128q, 4>;
318 // Add compute carry.
319 def VACCB : BinaryVRRc<"vaccb", 0xE7F1, null_frag, v128b, v128b, 0>;
320 def VACCH : BinaryVRRc<"vacch", 0xE7F1, null_frag, v128h, v128h, 1>;
321 def VACCF : BinaryVRRc<"vaccf", 0xE7F1, null_frag, v128f, v128f, 2>;
322 def VACCG : BinaryVRRc<"vaccg", 0xE7F1, null_frag, v128g, v128g, 3>;
323 def VACCQ : BinaryVRRc<"vaccq", 0xE7F1, null_frag, v128q, v128q, 4>;
326 def VACQ : TernaryVRRd<"vacq", 0xE7BB, null_frag, v128q, v128q, 4>;
328 // Add with carry compute carry.
329 def VACCCQ : TernaryVRRd<"vacccq", 0xE7B9, null_frag, v128q, v128q, 4>;
332 def VN : BinaryVRRc<"vn", 0xE768, null_frag, v128any, v128any>;
334 // And with complement.
335 def VNC : BinaryVRRc<"vnc", 0xE769, null_frag, v128any, v128any>;
338 def VAVGB : BinaryVRRc<"vavgb", 0xE7F2, null_frag, v128b, v128b, 0>;
339 def VAVGH : BinaryVRRc<"vavgh", 0xE7F2, null_frag, v128h, v128h, 1>;
340 def VAVGF : BinaryVRRc<"vavgf", 0xE7F2, null_frag, v128f, v128f, 2>;
341 def VAVGG : BinaryVRRc<"vavgg", 0xE7F2, null_frag, v128g, v128g, 3>;
344 def VAVGLB : BinaryVRRc<"vavglb", 0xE7F0, null_frag, v128b, v128b, 0>;
345 def VAVGLH : BinaryVRRc<"vavglh", 0xE7F0, null_frag, v128h, v128h, 1>;
346 def VAVGLF : BinaryVRRc<"vavglf", 0xE7F0, null_frag, v128f, v128f, 2>;
347 def VAVGLG : BinaryVRRc<"vavglg", 0xE7F0, null_frag, v128g, v128g, 3>;
350 def VCKSM : BinaryVRRc<"vcksm", 0xE766, null_frag, v128any, v128any>;
352 // Count leading zeros.
353 def VCLZB : UnaryVRRa<"vclzb", 0xE753, ctlz, v128b, v128b, 0>;
354 def VCLZH : UnaryVRRa<"vclzh", 0xE753, ctlz, v128h, v128h, 1>;
355 def VCLZF : UnaryVRRa<"vclzf", 0xE753, ctlz, v128f, v128f, 2>;
356 def VCLZG : UnaryVRRa<"vclzg", 0xE753, ctlz, v128g, v128g, 3>;
358 // Count trailing zeros.
359 def VCTZB : UnaryVRRa<"vctzb", 0xE752, cttz, v128b, v128b, 0>;
360 def VCTZH : UnaryVRRa<"vctzh", 0xE752, cttz, v128h, v128h, 1>;
361 def VCTZF : UnaryVRRa<"vctzf", 0xE752, cttz, v128f, v128f, 2>;
362 def VCTZG : UnaryVRRa<"vctzg", 0xE752, cttz, v128g, v128g, 3>;
365 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>;
367 // Galois field multiply sum.
368 def VGFMB : BinaryVRRc<"vgfmb", 0xE7B4, null_frag, v128b, v128b, 0>;
369 def VGFMH : BinaryVRRc<"vgfmh", 0xE7B4, null_frag, v128h, v128h, 1>;
370 def VGFMF : BinaryVRRc<"vgfmf", 0xE7B4, null_frag, v128f, v128f, 2>;
371 def VGFMG : BinaryVRRc<"vgfmg", 0xE7B4, null_frag, v128g, v128g, 3>;
373 // Galois field multiply sum and accumulate.
374 def VGFMAB : TernaryVRRd<"vgfmab", 0xE7BC, null_frag, v128b, v128b, 0>;
375 def VGFMAH : TernaryVRRd<"vgfmah", 0xE7BC, null_frag, v128h, v128h, 1>;
376 def VGFMAF : TernaryVRRd<"vgfmaf", 0xE7BC, null_frag, v128f, v128f, 2>;
377 def VGFMAG : TernaryVRRd<"vgfmag", 0xE7BC, null_frag, v128g, v128g, 3>;
380 def VLCB : UnaryVRRa<"vlcb", 0xE7DE, z_vneg, v128b, v128b, 0>;
381 def VLCH : UnaryVRRa<"vlch", 0xE7DE, z_vneg, v128h, v128h, 1>;
382 def VLCF : UnaryVRRa<"vlcf", 0xE7DE, z_vneg, v128f, v128f, 2>;
383 def VLCG : UnaryVRRa<"vlcg", 0xE7DE, z_vneg, v128g, v128g, 3>;
386 def VLPB : UnaryVRRa<"vlpb", 0xE7DF, z_viabs8, v128b, v128b, 0>;
387 def VLPH : UnaryVRRa<"vlph", 0xE7DF, z_viabs16, v128h, v128h, 1>;
388 def VLPF : UnaryVRRa<"vlpf", 0xE7DF, z_viabs32, v128f, v128f, 2>;
389 def VLPG : UnaryVRRa<"vlpg", 0xE7DF, z_viabs64, v128g, v128g, 3>;
392 def VMXB : BinaryVRRc<"vmxb", 0xE7FF, null_frag, v128b, v128b, 0>;
393 def VMXH : BinaryVRRc<"vmxh", 0xE7FF, null_frag, v128h, v128h, 1>;
394 def VMXF : BinaryVRRc<"vmxf", 0xE7FF, null_frag, v128f, v128f, 2>;
395 def VMXG : BinaryVRRc<"vmxg", 0xE7FF, null_frag, v128g, v128g, 3>;
398 def VMXLB : BinaryVRRc<"vmxlb", 0xE7FD, null_frag, v128b, v128b, 0>;
399 def VMXLH : BinaryVRRc<"vmxlh", 0xE7FD, null_frag, v128h, v128h, 1>;
400 def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, null_frag, v128f, v128f, 2>;
401 def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, null_frag, v128g, v128g, 3>;
404 def VMNB : BinaryVRRc<"vmnb", 0xE7FE, null_frag, v128b, v128b, 0>;
405 def VMNH : BinaryVRRc<"vmnh", 0xE7FE, null_frag, v128h, v128h, 1>;
406 def VMNF : BinaryVRRc<"vmnf", 0xE7FE, null_frag, v128f, v128f, 2>;
407 def VMNG : BinaryVRRc<"vmng", 0xE7FE, null_frag, v128g, v128g, 3>;
410 def VMNLB : BinaryVRRc<"vmnlb", 0xE7FC, null_frag, v128b, v128b, 0>;
411 def VMNLH : BinaryVRRc<"vmnlh", 0xE7FC, null_frag, v128h, v128h, 1>;
412 def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, null_frag, v128f, v128f, 2>;
413 def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, null_frag, v128g, v128g, 3>;
415 // Multiply and add low.
416 def VMALB : TernaryVRRd<"vmalb", 0xE7AA, z_muladd, v128b, v128b, 0>;
417 def VMALHW : TernaryVRRd<"vmalhw", 0xE7AA, z_muladd, v128h, v128h, 1>;
418 def VMALF : TernaryVRRd<"vmalf", 0xE7AA, z_muladd, v128f, v128f, 2>;
420 // Multiply and add high.
421 def VMAHB : TernaryVRRd<"vmahb", 0xE7AB, null_frag, v128b, v128b, 0>;
422 def VMAHH : TernaryVRRd<"vmahh", 0xE7AB, null_frag, v128h, v128h, 1>;
423 def VMAHF : TernaryVRRd<"vmahf", 0xE7AB, null_frag, v128f, v128f, 2>;
425 // Multiply and add logical high.
426 def VMALHB : TernaryVRRd<"vmalhb", 0xE7A9, null_frag, v128b, v128b, 0>;
427 def VMALHH : TernaryVRRd<"vmalhh", 0xE7A9, null_frag, v128h, v128h, 1>;
428 def VMALHF : TernaryVRRd<"vmalhf", 0xE7A9, null_frag, v128f, v128f, 2>;
430 // Multiply and add even.
431 def VMAEB : TernaryVRRd<"vmaeb", 0xE7AE, null_frag, v128h, v128b, 0>;
432 def VMAEH : TernaryVRRd<"vmaeh", 0xE7AE, null_frag, v128f, v128h, 1>;
433 def VMAEF : TernaryVRRd<"vmaef", 0xE7AE, null_frag, v128g, v128f, 2>;
435 // Multiply and add logical even.
436 def VMALEB : TernaryVRRd<"vmaleb", 0xE7AC, null_frag, v128h, v128b, 0>;
437 def VMALEH : TernaryVRRd<"vmaleh", 0xE7AC, null_frag, v128f, v128h, 1>;
438 def VMALEF : TernaryVRRd<"vmalef", 0xE7AC, null_frag, v128g, v128f, 2>;
440 // Multiply and add odd.
441 def VMAOB : TernaryVRRd<"vmaob", 0xE7AF, null_frag, v128h, v128b, 0>;
442 def VMAOH : TernaryVRRd<"vmaoh", 0xE7AF, null_frag, v128f, v128h, 1>;
443 def VMAOF : TernaryVRRd<"vmaof", 0xE7AF, null_frag, v128g, v128f, 2>;
445 // Multiply and add logical odd.
446 def VMALOB : TernaryVRRd<"vmalob", 0xE7AD, null_frag, v128h, v128b, 0>;
447 def VMALOH : TernaryVRRd<"vmaloh", 0xE7AD, null_frag, v128f, v128h, 1>;
448 def VMALOF : TernaryVRRd<"vmalof", 0xE7AD, null_frag, v128g, v128f, 2>;
451 def VMHB : BinaryVRRc<"vmhb", 0xE7A3, null_frag, v128b, v128b, 0>;
452 def VMHH : BinaryVRRc<"vmhh", 0xE7A3, null_frag, v128h, v128h, 1>;
453 def VMHF : BinaryVRRc<"vmhf", 0xE7A3, null_frag, v128f, v128f, 2>;
455 // Multiply logical high.
456 def VMLHB : BinaryVRRc<"vmlhb", 0xE7A1, null_frag, v128b, v128b, 0>;
457 def VMLHH : BinaryVRRc<"vmlhh", 0xE7A1, null_frag, v128h, v128h, 1>;
458 def VMLHF : BinaryVRRc<"vmlhf", 0xE7A1, null_frag, v128f, v128f, 2>;
461 def VMLB : BinaryVRRc<"vmlb", 0xE7A2, mul, v128b, v128b, 0>;
462 def VMLHW : BinaryVRRc<"vmlhw", 0xE7A2, mul, v128h, v128h, 1>;
463 def VMLF : BinaryVRRc<"vmlf", 0xE7A2, mul, v128f, v128f, 2>;
466 def VMEB : BinaryVRRc<"vmeb", 0xE7A6, null_frag, v128h, v128b, 0>;
467 def VMEH : BinaryVRRc<"vmeh", 0xE7A6, null_frag, v128f, v128h, 1>;
468 def VMEF : BinaryVRRc<"vmef", 0xE7A6, null_frag, v128g, v128f, 2>;
470 // Multiply logical even.
471 def VMLEB : BinaryVRRc<"vmleb", 0xE7A4, null_frag, v128h, v128b, 0>;
472 def VMLEH : BinaryVRRc<"vmleh", 0xE7A4, null_frag, v128f, v128h, 1>;
473 def VMLEF : BinaryVRRc<"vmlef", 0xE7A4, null_frag, v128g, v128f, 2>;
476 def VMOB : BinaryVRRc<"vmob", 0xE7A7, null_frag, v128h, v128b, 0>;
477 def VMOH : BinaryVRRc<"vmoh", 0xE7A7, null_frag, v128f, v128h, 1>;
478 def VMOF : BinaryVRRc<"vmof", 0xE7A7, null_frag, v128g, v128f, 2>;
480 // Multiply logical odd.
481 def VMLOB : BinaryVRRc<"vmlob", 0xE7A5, null_frag, v128h, v128b, 0>;
482 def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, null_frag, v128f, v128h, 1>;
483 def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, null_frag, v128g, v128f, 2>;
486 def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>;
489 def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>;
492 def VPOPCT : BinaryVRRa<"vpopct", 0xE750>;
493 def : Pat<(v16i8 (z_popcnt VR128:$x)), (VPOPCT VR128:$x, 0)>;
495 // Element rotate left logical (with vector shift amount).
496 def VERLLVB : BinaryVRRc<"verllvb", 0xE773, null_frag, v128b, v128b, 0>;
497 def VERLLVH : BinaryVRRc<"verllvh", 0xE773, null_frag, v128h, v128h, 1>;
498 def VERLLVF : BinaryVRRc<"verllvf", 0xE773, null_frag, v128f, v128f, 2>;
499 def VERLLVG : BinaryVRRc<"verllvg", 0xE773, null_frag, v128g, v128g, 3>;
501 // Element rotate left logical (with scalar shift amount).
502 def VERLLB : BinaryVRSa<"verllb", 0xE733, null_frag, v128b, v128b, 0>;
503 def VERLLH : BinaryVRSa<"verllh", 0xE733, null_frag, v128h, v128h, 1>;
504 def VERLLF : BinaryVRSa<"verllf", 0xE733, null_frag, v128f, v128f, 2>;
505 def VERLLG : BinaryVRSa<"verllg", 0xE733, null_frag, v128g, v128g, 3>;
507 // Element rotate and insert under mask.
508 def VERIMB : QuaternaryVRId<"verimb", 0xE772, null_frag, v128b, v128b, 0>;
509 def VERIMH : QuaternaryVRId<"verimh", 0xE772, null_frag, v128h, v128h, 1>;
510 def VERIMF : QuaternaryVRId<"verimf", 0xE772, null_frag, v128f, v128f, 2>;
511 def VERIMG : QuaternaryVRId<"verimg", 0xE772, null_frag, v128g, v128g, 3>;
513 // Element shift left (with vector shift amount).
514 def VESLVB : BinaryVRRc<"veslvb", 0xE770, z_vshl, v128b, v128b, 0>;
515 def VESLVH : BinaryVRRc<"veslvh", 0xE770, z_vshl, v128h, v128h, 1>;
516 def VESLVF : BinaryVRRc<"veslvf", 0xE770, z_vshl, v128f, v128f, 2>;
517 def VESLVG : BinaryVRRc<"veslvg", 0xE770, z_vshl, v128g, v128g, 3>;
519 // Element shift left (with scalar shift amount).
520 def VESLB : BinaryVRSa<"veslb", 0xE730, z_vshl_by_scalar, v128b, v128b, 0>;
521 def VESLH : BinaryVRSa<"veslh", 0xE730, z_vshl_by_scalar, v128h, v128h, 1>;
522 def VESLF : BinaryVRSa<"veslf", 0xE730, z_vshl_by_scalar, v128f, v128f, 2>;
523 def VESLG : BinaryVRSa<"veslg", 0xE730, z_vshl_by_scalar, v128g, v128g, 3>;
525 // Element shift right arithmetic (with vector shift amount).
526 def VESRAVB : BinaryVRRc<"vesravb", 0xE77A, z_vsra, v128b, v128b, 0>;
527 def VESRAVH : BinaryVRRc<"vesravh", 0xE77A, z_vsra, v128h, v128h, 1>;
528 def VESRAVF : BinaryVRRc<"vesravf", 0xE77A, z_vsra, v128f, v128f, 2>;
529 def VESRAVG : BinaryVRRc<"vesravg", 0xE77A, z_vsra, v128g, v128g, 3>;
531 // Element shift right arithmetic (with scalar shift amount).
532 def VESRAB : BinaryVRSa<"vesrab", 0xE73A, z_vsra_by_scalar, v128b, v128b, 0>;
533 def VESRAH : BinaryVRSa<"vesrah", 0xE73A, z_vsra_by_scalar, v128h, v128h, 1>;
534 def VESRAF : BinaryVRSa<"vesraf", 0xE73A, z_vsra_by_scalar, v128f, v128f, 2>;
535 def VESRAG : BinaryVRSa<"vesrag", 0xE73A, z_vsra_by_scalar, v128g, v128g, 3>;
537 // Element shift right logical (with vector shift amount).
538 def VESRLVB : BinaryVRRc<"vesrlvb", 0xE778, z_vsrl, v128b, v128b, 0>;
539 def VESRLVH : BinaryVRRc<"vesrlvh", 0xE778, z_vsrl, v128h, v128h, 1>;
540 def VESRLVF : BinaryVRRc<"vesrlvf", 0xE778, z_vsrl, v128f, v128f, 2>;
541 def VESRLVG : BinaryVRRc<"vesrlvg", 0xE778, z_vsrl, v128g, v128g, 3>;
543 // Element shift right logical (with scalar shift amount).
544 def VESRLB : BinaryVRSa<"vesrlb", 0xE738, z_vsrl_by_scalar, v128b, v128b, 0>;
545 def VESRLH : BinaryVRSa<"vesrlh", 0xE738, z_vsrl_by_scalar, v128h, v128h, 1>;
546 def VESRLF : BinaryVRSa<"vesrlf", 0xE738, z_vsrl_by_scalar, v128f, v128f, 2>;
547 def VESRLG : BinaryVRSa<"vesrlg", 0xE738, z_vsrl_by_scalar, v128g, v128g, 3>;
550 def VSL : BinaryVRRc<"vsl", 0xE774, null_frag, v128b, v128b>;
552 // Shift left by byte.
553 def VSLB : BinaryVRRc<"vslb", 0xE775, null_frag, v128b, v128b>;
555 // Shift left double by byte.
556 def VSLDB : TernaryVRId<"vsldb", 0xE777, z_shl_double, v128b, v128b, 0>;
558 // Shift right arithmetic.
559 def VSRA : BinaryVRRc<"vsra", 0xE77E, null_frag, v128b, v128b>;
561 // Shift right arithmetic by byte.
562 def VSRAB : BinaryVRRc<"vsrab", 0xE77F, null_frag, v128b, v128b>;
564 // Shift right logical.
565 def VSRL : BinaryVRRc<"vsrl", 0xE77C, null_frag, v128b, v128b>;
567 // Shift right logical by byte.
568 def VSRLB : BinaryVRRc<"vsrlb", 0xE77D, null_frag, v128b, v128b>;
571 def VSB : BinaryVRRc<"vsb", 0xE7F7, sub, v128b, v128b, 0>;
572 def VSH : BinaryVRRc<"vsh", 0xE7F7, sub, v128h, v128h, 1>;
573 def VSF : BinaryVRRc<"vsf", 0xE7F7, sub, v128f, v128f, 2>;
574 def VSG : BinaryVRRc<"vsg", 0xE7F7, sub, v128g, v128g, 3>;
575 def VSQ : BinaryVRRc<"vsq", 0xE7F7, null_frag, v128q, v128q, 4>;
577 // Subtract compute borrow indication.
578 def VSCBIB : BinaryVRRc<"vscbib", 0xE7F5, null_frag, v128b, v128b, 0>;
579 def VSCBIH : BinaryVRRc<"vscbih", 0xE7F5, null_frag, v128h, v128h, 1>;
580 def VSCBIF : BinaryVRRc<"vscbif", 0xE7F5, null_frag, v128f, v128f, 2>;
581 def VSCBIG : BinaryVRRc<"vscbig", 0xE7F5, null_frag, v128g, v128g, 3>;
582 def VSCBIQ : BinaryVRRc<"vscbiq", 0xE7F5, null_frag, v128q, v128q, 4>;
584 // Subtract with borrow indication.
585 def VSBIQ : TernaryVRRd<"vsbiq", 0xE7BF, null_frag, v128q, v128q, 4>;
587 // Subtract with borrow compute borrow indication.
588 def VSBCBIQ : TernaryVRRd<"vsbcbiq", 0xE7BD, null_frag, v128q, v128q, 4>;
590 // Sum across doubleword.
591 def VSUMGH : BinaryVRRc<"vsumgh", 0xE765, z_vsum, v128g, v128h, 1>;
592 def VSUMGF : BinaryVRRc<"vsumgf", 0xE765, z_vsum, v128g, v128f, 2>;
594 // Sum across quadword.
595 def VSUMQF : BinaryVRRc<"vsumqf", 0xE767, z_vsum, v128q, v128f, 2>;
596 def VSUMQG : BinaryVRRc<"vsumqg", 0xE767, z_vsum, v128q, v128g, 3>;
599 def VSUMB : BinaryVRRc<"vsumb", 0xE764, z_vsum, v128f, v128b, 0>;
600 def VSUMH : BinaryVRRc<"vsumh", 0xE764, z_vsum, v128f, v128h, 1>;
603 // Instantiate the bitwise ops for type TYPE.
604 multiclass BitwiseVectorOps<ValueType type> {
605 let Predicates = [FeatureVector] in {
606 def : Pat<(type (and VR128:$x, VR128:$y)), (VN VR128:$x, VR128:$y)>;
607 def : Pat<(type (and VR128:$x, (z_vnot VR128:$y))),
608 (VNC VR128:$x, VR128:$y)>;
609 def : Pat<(type (or VR128:$x, VR128:$y)), (VO VR128:$x, VR128:$y)>;
610 def : Pat<(type (xor VR128:$x, VR128:$y)), (VX VR128:$x, VR128:$y)>;
611 def : Pat<(type (or (and VR128:$x, VR128:$z),
612 (and VR128:$y, (z_vnot VR128:$z)))),
613 (VSEL VR128:$x, VR128:$y, VR128:$z)>;
614 def : Pat<(type (z_vnot (or VR128:$x, VR128:$y))),
615 (VNO VR128:$x, VR128:$y)>;
616 def : Pat<(type (z_vnot VR128:$x)), (VNO VR128:$x, VR128:$x)>;
620 defm : BitwiseVectorOps<v16i8>;
621 defm : BitwiseVectorOps<v8i16>;
622 defm : BitwiseVectorOps<v4i32>;
623 defm : BitwiseVectorOps<v2i64>;
625 // Instantiate additional patterns for absolute-related expressions on
626 // type TYPE. LC is the negate instruction for TYPE and LP is the absolute
628 multiclass IntegerAbsoluteVectorOps<ValueType type, Instruction lc,
629 Instruction lp, int shift> {
630 let Predicates = [FeatureVector] in {
631 def : Pat<(type (vselect (type (z_vicmph_zero VR128:$x)),
632 (z_vneg VR128:$x), VR128:$x)),
634 def : Pat<(type (vselect (type (z_vnot (z_vicmph_zero VR128:$x))),
635 VR128:$x, (z_vneg VR128:$x))),
637 def : Pat<(type (vselect (type (z_vicmpl_zero VR128:$x)),
638 VR128:$x, (z_vneg VR128:$x))),
640 def : Pat<(type (vselect (type (z_vnot (z_vicmpl_zero VR128:$x))),
641 (z_vneg VR128:$x), VR128:$x)),
643 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)),
645 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))),
648 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)),
650 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))),
651 (z_vneg VR128:$x)))),
656 defm : IntegerAbsoluteVectorOps<v16i8, VLCB, VLPB, 7>;
657 defm : IntegerAbsoluteVectorOps<v8i16, VLCH, VLPH, 15>;
658 defm : IntegerAbsoluteVectorOps<v4i32, VLCF, VLPF, 31>;
659 defm : IntegerAbsoluteVectorOps<v2i64, VLCG, VLPG, 63>;
661 // Instantiate minimum- and maximum-related patterns for TYPE. CMPH is the
662 // signed or unsigned "set if greater than" comparison instruction and
663 // MIN and MAX are the associated minimum and maximum instructions.
664 multiclass IntegerMinMaxVectorOps<ValueType type, SDPatternOperator cmph,
665 Instruction min, Instruction max> {
666 let Predicates = [FeatureVector] in {
667 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$x, VR128:$y)),
668 (max VR128:$x, VR128:$y)>;
669 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$y, VR128:$x)),
670 (min VR128:$x, VR128:$y)>;
671 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)),
672 VR128:$x, VR128:$y)),
673 (min VR128:$x, VR128:$y)>;
674 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)),
675 VR128:$y, VR128:$x)),
676 (max VR128:$x, VR128:$y)>;
681 defm : IntegerMinMaxVectorOps<v16i8, z_vicmph, VMNB, VMXB>;
682 defm : IntegerMinMaxVectorOps<v8i16, z_vicmph, VMNH, VMXH>;
683 defm : IntegerMinMaxVectorOps<v4i32, z_vicmph, VMNF, VMXF>;
684 defm : IntegerMinMaxVectorOps<v2i64, z_vicmph, VMNG, VMXG>;
687 defm : IntegerMinMaxVectorOps<v16i8, z_vicmphl, VMNLB, VMXLB>;
688 defm : IntegerMinMaxVectorOps<v8i16, z_vicmphl, VMNLH, VMXLH>;
689 defm : IntegerMinMaxVectorOps<v4i32, z_vicmphl, VMNLF, VMXLF>;
690 defm : IntegerMinMaxVectorOps<v2i64, z_vicmphl, VMNLG, VMXLG>;
692 //===----------------------------------------------------------------------===//
693 // Integer comparison
694 //===----------------------------------------------------------------------===//
696 let Predicates = [FeatureVector] in {
699 def VECB : CompareVRRa<"vecb", 0xE7DB, null_frag, v128b, 0>;
700 def VECH : CompareVRRa<"vech", 0xE7DB, null_frag, v128h, 1>;
701 def VECF : CompareVRRa<"vecf", 0xE7DB, null_frag, v128f, 2>;
702 def VECG : CompareVRRa<"vecg", 0xE7DB, null_frag, v128g, 3>;
705 // Element compare logical.
707 def VECLB : CompareVRRa<"veclb", 0xE7D9, null_frag, v128b, 0>;
708 def VECLH : CompareVRRa<"veclh", 0xE7D9, null_frag, v128h, 1>;
709 def VECLF : CompareVRRa<"veclf", 0xE7D9, null_frag, v128f, 2>;
710 def VECLG : CompareVRRa<"veclg", 0xE7D9, null_frag, v128g, 3>;
714 defm VCEQB : BinaryVRRbSPair<"vceqb", 0xE7F8, z_vicmpe, null_frag,
716 defm VCEQH : BinaryVRRbSPair<"vceqh", 0xE7F8, z_vicmpe, null_frag,
718 defm VCEQF : BinaryVRRbSPair<"vceqf", 0xE7F8, z_vicmpe, null_frag,
720 defm VCEQG : BinaryVRRbSPair<"vceqg", 0xE7F8, z_vicmpe, null_frag,
724 defm VCHB : BinaryVRRbSPair<"vchb", 0xE7FB, z_vicmph, null_frag,
726 defm VCHH : BinaryVRRbSPair<"vchh", 0xE7FB, z_vicmph, null_frag,
728 defm VCHF : BinaryVRRbSPair<"vchf", 0xE7FB, z_vicmph, null_frag,
730 defm VCHG : BinaryVRRbSPair<"vchg", 0xE7FB, z_vicmph, null_frag,
733 // Compare high logical.
734 defm VCHLB : BinaryVRRbSPair<"vchlb", 0xE7F9, z_vicmphl, null_frag,
736 defm VCHLH : BinaryVRRbSPair<"vchlh", 0xE7F9, z_vicmphl, null_frag,
738 defm VCHLF : BinaryVRRbSPair<"vchlf", 0xE7F9, z_vicmphl, null_frag,
740 defm VCHLG : BinaryVRRbSPair<"vchlg", 0xE7F9, z_vicmphl, null_frag,
745 def VTM : CompareVRRa<"vtm", 0xE7D8, null_frag, v128any, 0>;
748 //===----------------------------------------------------------------------===//
749 // Floating-point arithmetic
750 //===----------------------------------------------------------------------===//
752 // See comments in SystemZInstrFP.td for the suppression flags and
754 multiclass VectorRounding<Instruction insn, TypedReg tr> {
755 def : FPConversion<insn, frint, tr, tr, 0, 0>;
756 def : FPConversion<insn, fnearbyint, tr, tr, 4, 0>;
757 def : FPConversion<insn, ffloor, tr, tr, 4, 7>;
758 def : FPConversion<insn, fceil, tr, tr, 4, 6>;
759 def : FPConversion<insn, ftrunc, tr, tr, 4, 5>;
760 def : FPConversion<insn, frnd, tr, tr, 4, 1>;
763 let Predicates = [FeatureVector] in {
765 def VFADB : BinaryVRRc<"vfadb", 0xE7E3, fadd, v128db, v128db, 3, 0>;
766 def WFADB : BinaryVRRc<"wfadb", 0xE7E3, null_frag, v64db, v64db, 3, 8>;
768 // Convert from fixed 64-bit.
769 def VCDGB : TernaryVRRa<"vcdgb", 0xE7C3, null_frag, v128db, v128g, 3, 0>;
770 def WCDGB : TernaryVRRa<"wcdgb", 0xE7C3, null_frag, v64db, v64g, 3, 8>;
771 def : FPConversion<VCDGB, sint_to_fp, v128db, v128g, 0, 0>;
773 // Convert from logical 64-bit.
774 def VCDLGB : TernaryVRRa<"vcdlgb", 0xE7C1, null_frag, v128db, v128g, 3, 0>;
775 def WCDLGB : TernaryVRRa<"wcdlgb", 0xE7C1, null_frag, v64db, v64g, 3, 8>;
776 def : FPConversion<VCDLGB, uint_to_fp, v128db, v128g, 0, 0>;
778 // Convert to fixed 64-bit.
779 def VCGDB : TernaryVRRa<"vcgdb", 0xE7C2, null_frag, v128g, v128db, 3, 0>;
780 def WCGDB : TernaryVRRa<"wcgdb", 0xE7C2, null_frag, v64g, v64db, 3, 8>;
781 // Rounding mode should agree with SystemZInstrFP.td.
782 def : FPConversion<VCGDB, fp_to_sint, v128g, v128db, 0, 5>;
784 // Convert to logical 64-bit.
785 def VCLGDB : TernaryVRRa<"vclgdb", 0xE7C0, null_frag, v128g, v128db, 3, 0>;
786 def WCLGDB : TernaryVRRa<"wclgdb", 0xE7C0, null_frag, v64g, v64db, 3, 8>;
787 // Rounding mode should agree with SystemZInstrFP.td.
788 def : FPConversion<VCLGDB, fp_to_uint, v128g, v128db, 0, 5>;
791 def VFDDB : BinaryVRRc<"vfddb", 0xE7E5, fdiv, v128db, v128db, 3, 0>;
792 def WFDDB : BinaryVRRc<"wfddb", 0xE7E5, null_frag, v64db, v64db, 3, 8>;
795 def VFIDB : TernaryVRRa<"vfidb", 0xE7C7, null_frag, v128db, v128db, 3, 0>;
796 def WFIDB : TernaryVRRa<"wfidb", 0xE7C7, null_frag, v64db, v64db, 3, 8>;
797 defm : VectorRounding<VFIDB, v128db>;
800 def VLDEB : UnaryVRRa<"vldeb", 0xE7C4, null_frag, v128db, v128eb, 2, 0>;
801 def WLDEB : UnaryVRRa<"wldeb", 0xE7C4, null_frag, v64db, v32eb, 2, 8>;
804 def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128eb, v128db, 3, 0>;
805 def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32eb, v64db, 3, 8>;
808 def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, fmul, v128db, v128db, 3, 0>;
809 def WFMDB : BinaryVRRc<"wfmdb", 0xE7E7, null_frag, v64db, v64db, 3, 8>;
812 def VFMADB : TernaryVRRe<"vfmadb", 0xE78F, fma, v128db, v128db, 0, 3>;
813 def WFMADB : TernaryVRRe<"wfmadb", 0xE78F, null_frag, v64db, v64db, 8, 3>;
815 // Multiply and subtract.
816 def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, fms, v128db, v128db, 0, 3>;
817 def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, null_frag, v64db, v64db, 8, 3>;
820 def VFLCDB : UnaryVRRa<"vflcdb", 0xE7CC, fneg, v128db, v128db, 3, 0, 0>;
821 def WFLCDB : UnaryVRRa<"wflcdb", 0xE7CC, null_frag, v64db, v64db, 3, 8, 0>;
824 def VFLNDB : UnaryVRRa<"vflndb", 0xE7CC, fnabs, v128db, v128db, 3, 0, 1>;
825 def WFLNDB : UnaryVRRa<"wflndb", 0xE7CC, null_frag, v64db, v64db, 3, 8, 1>;
828 def VFLPDB : UnaryVRRa<"vflpdb", 0xE7CC, fabs, v128db, v128db, 3, 0, 2>;
829 def WFLPDB : UnaryVRRa<"wflpdb", 0xE7CC, null_frag, v64db, v64db, 3, 8, 2>;
832 def VFSQDB : UnaryVRRa<"vfsqdb", 0xE7CE, fsqrt, v128db, v128db, 3, 0>;
833 def WFSQDB : UnaryVRRa<"wfsqdb", 0xE7CE, null_frag, v64db, v64db, 3, 8>;
836 def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, fsub, v128db, v128db, 3, 0>;
837 def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, null_frag, v64db, v64db, 3, 8>;
839 // Test data class immediate.
841 def VFTCIDB : BinaryVRIe<"vftcidb", 0xE74A, null_frag, v128g, v128db, 3, 0>;
842 def WFTCIDB : BinaryVRIe<"wftcidb", 0xE74A, null_frag, v64g, v64db, 3, 8>;
846 //===----------------------------------------------------------------------===//
847 // Floating-point comparison
848 //===----------------------------------------------------------------------===//
850 let Predicates = [FeatureVector] in {
853 def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, null_frag, v64db, 3>;
855 // Compare and signal scalar.
857 def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, null_frag, v64db, 3>;
860 defm VFCEDB : BinaryVRRcSPair<"vfcedb", 0xE7E8, z_vfcmpe, null_frag,
861 v128g, v128db, 3, 0>;
862 defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag,
866 defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, z_vfcmph, null_frag,
867 v128g, v128db, 3, 0>;
868 defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag,
871 // Compare high or equal.
872 defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, z_vfcmphe, null_frag,
873 v128g, v128db, 3, 0>;
874 defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag,
878 //===----------------------------------------------------------------------===//
880 //===----------------------------------------------------------------------===//
882 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
883 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
884 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
885 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
887 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
888 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
889 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
890 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
892 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
893 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
894 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
895 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
897 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
898 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
899 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
900 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
902 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
903 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
904 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
905 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
907 //===----------------------------------------------------------------------===//
908 // Replicating scalars
909 //===----------------------------------------------------------------------===//
911 // Define patterns for replicating a scalar GR32 into a vector of type TYPE.
912 // INDEX is 8 minus the element size in bytes.
913 class VectorReplicateScalar<ValueType type, Instruction insn, bits<16> index>
914 : Pat<(type (z_replicate GR32:$scalar)),
915 (insn (VLVGP32 GR32:$scalar, GR32:$scalar), index)>;
917 def : VectorReplicateScalar<v16i8, VREPB, 7>;
918 def : VectorReplicateScalar<v8i16, VREPH, 3>;
919 def : VectorReplicateScalar<v4i32, VREPF, 1>;
921 // i64 replications are just a single isntruction.
922 def : Pat<(v2i64 (z_replicate GR64:$scalar)),
923 (VLVGP GR64:$scalar, GR64:$scalar)>;
925 //===----------------------------------------------------------------------===//
926 // Floating-point insertion and extraction
927 //===----------------------------------------------------------------------===//
929 // Floating-point values are stored in element 0 of the corresponding
930 // vector register. Scalar to vector conversion is just a subreg and
931 // scalar replication can just replicate element 0 of the vector register.
932 multiclass ScalarToVectorFP<Instruction vrep, ValueType vt, RegisterOperand cls,
933 SubRegIndex subreg> {
934 def : Pat<(vt (scalar_to_vector cls:$scalar)),
935 (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg)>;
936 def : Pat<(vt (z_replicate cls:$scalar)),
937 (vrep (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar,
940 defm : ScalarToVectorFP<VREPG, v2f64, FP64, subreg_r64>;
942 // Match v2f64 insertions. The AddedComplexity counters the 3 added by
943 // TableGen for the base register operand in VLVG-based integer insertions
944 // and ensures that this version is strictly better.
945 let AddedComplexity = 4 in {
946 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 0),
947 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
948 subreg_r64), VR128:$vec, 1)>;
949 def : Pat<(z_vector_insert (v2f64 VR128:$vec), FP64:$elt, 1),
950 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
954 // We extract f64 element X by replicating (for elements other than 0)
955 // and then taking a high subreg. The AddedComplexity counters the 3
956 // added by TableGen for the base register operand in VLGV-based integer
957 // extractions and ensures that this version is strictly better.
958 let AddedComplexity = 4 in {
959 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), 0)),
960 (EXTRACT_SUBREG VR128:$vec, subreg_r64)>;
961 def : Pat<(f64 (z_vector_extract (v2f64 VR128:$vec), imm32zx1:$index)),
962 (EXTRACT_SUBREG (VREPG VR128:$vec, imm32zx1:$index), subreg_r64)>;
965 //===----------------------------------------------------------------------===//
966 // String instructions
967 //===----------------------------------------------------------------------===//
969 let Predicates = [FeatureVector] in {
970 defm VFAEB : TernaryVRRbSPair<"vfaeb", 0xE782, null_frag, null_frag,
972 defm VFAEH : TernaryVRRbSPair<"vfaeh", 0xE782, null_frag, null_frag,
974 defm VFAEF : TernaryVRRbSPair<"vfaef", 0xE782, null_frag, null_frag,
976 defm VFAEZB : TernaryVRRbSPair<"vfaezb", 0xE782, null_frag, null_frag,
978 defm VFAEZH : TernaryVRRbSPair<"vfaezh", 0xE782, null_frag, null_frag,
980 defm VFAEZF : TernaryVRRbSPair<"vfaezf", 0xE782, null_frag, null_frag,
983 defm VFEEB : BinaryVRRbSPair<"vfeeb", 0xE780, null_frag, null_frag,
984 v128b, v128b, 0, 0, 1>;
985 defm VFEEH : BinaryVRRbSPair<"vfeeh", 0xE780, null_frag, null_frag,
986 v128h, v128h, 1, 0, 1>;
987 defm VFEEF : BinaryVRRbSPair<"vfeef", 0xE780, null_frag, null_frag,
988 v128f, v128f, 2, 0, 1>;
989 defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, null_frag, null_frag,
990 v128b, v128b, 0, 2, 3>;
991 defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, null_frag, null_frag,
992 v128h, v128h, 1, 2, 3>;
993 defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, null_frag, null_frag,
994 v128f, v128f, 2, 2, 3>;
996 defm VFENEB : BinaryVRRbSPair<"vfeneb", 0xE781, null_frag, null_frag,
997 v128b, v128b, 0, 0, 1>;
998 defm VFENEH : BinaryVRRbSPair<"vfeneh", 0xE781, null_frag, null_frag,
999 v128h, v128h, 1, 0, 1>;
1000 defm VFENEF : BinaryVRRbSPair<"vfenef", 0xE781, null_frag, null_frag,
1001 v128f, v128f, 2, 0, 1>;
1002 defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, null_frag, null_frag,
1003 v128b, v128b, 0, 2, 3>;
1004 defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, null_frag, null_frag,
1005 v128h, v128h, 1, 2, 3>;
1006 defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, null_frag, null_frag,
1007 v128f, v128f, 2, 2, 3>;
1009 defm VISTRB : UnaryVRRaSPair<"vistrb", 0xE75C, null_frag, null_frag,
1011 defm VISTRH : UnaryVRRaSPair<"vistrh", 0xE75C, null_frag, null_frag,
1013 defm VISTRF : UnaryVRRaSPair<"vistrf", 0xE75C, null_frag, null_frag,
1016 defm VSTRCB : QuaternaryVRRdSPair<"vstrcb", 0xE78A, null_frag, null_frag,
1017 v128b, v128b, 0, 0>;
1018 defm VSTRCH : QuaternaryVRRdSPair<"vstrch", 0xE78A, null_frag, null_frag,
1019 v128h, v128h, 1, 0>;
1020 defm VSTRCF : QuaternaryVRRdSPair<"vstrcf", 0xE78A, null_frag, null_frag,
1021 v128f, v128f, 2, 0>;
1022 defm VSTRCZB : QuaternaryVRRdSPair<"vstrczb", 0xE78A, null_frag, null_frag,
1023 v128b, v128b, 0, 2>;
1024 defm VSTRCZH : QuaternaryVRRdSPair<"vstrczh", 0xE78A, null_frag, null_frag,
1025 v128h, v128h, 1, 2>;
1026 defm VSTRCZF : QuaternaryVRRdSPair<"vstrczf", 0xE78A, null_frag, null_frag,
1027 v128f, v128f, 2, 2>;