1 //==- SystemZInstrVector.td - SystemZ Vector instructions ------*- tblgen-*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 let Predicates = [FeatureVector] in {
16 def VLR : UnaryVRRa<"vlr", 0xE756, null_frag, v128any, v128any>;
18 // Load GR from VR element.
19 def VLGVB : BinaryVRSc<"vlgvb", 0xE721, null_frag, v128b, 0>;
20 def VLGVH : BinaryVRSc<"vlgvh", 0xE721, null_frag, v128h, 1>;
21 def VLGVF : BinaryVRSc<"vlgvf", 0xE721, null_frag, v128f, 2>;
22 def VLGVG : BinaryVRSc<"vlgvg", 0xE721, z_vector_extract, v128g, 3>;
24 // Load VR element from GR.
25 def VLVGB : TernaryVRSb<"vlvgb", 0xE722, z_vector_insert,
26 v128b, v128b, GR32, 0>;
27 def VLVGH : TernaryVRSb<"vlvgh", 0xE722, z_vector_insert,
28 v128h, v128h, GR32, 1>;
29 def VLVGF : TernaryVRSb<"vlvgf", 0xE722, z_vector_insert,
30 v128f, v128f, GR32, 2>;
31 def VLVGG : TernaryVRSb<"vlvgg", 0xE722, z_vector_insert,
32 v128g, v128g, GR64, 3>;
34 // Load VR from GRs disjoint.
35 def VLVGP : BinaryVRRf<"vlvgp", 0xE762, z_join_dwords, v128g>;
36 def VLVGP32 : BinaryAliasVRRf<GR32>;
39 // Extractions always assign to the full GR64, even if the element would
40 // fit in the lower 32 bits. Sub-i64 extracts therefore need to take a
41 // subreg of the result.
42 class VectorExtractSubreg<ValueType type, Instruction insn>
43 : Pat<(i32 (z_vector_extract (type VR128:$vec), shift12only:$index)),
44 (EXTRACT_SUBREG (insn VR128:$vec, shift12only:$index), subreg_l32)>;
46 def : VectorExtractSubreg<v16i8, VLGVB>;
47 def : VectorExtractSubreg<v8i16, VLGVH>;
48 def : VectorExtractSubreg<v4i32, VLGVF>;
50 //===----------------------------------------------------------------------===//
51 // Immediate instructions
52 //===----------------------------------------------------------------------===//
54 let Predicates = [FeatureVector] in {
55 // Generate byte mask.
56 def VZERO : InherentVRIa<"vzero", 0xE744, 0>;
57 def VONE : InherentVRIa<"vone", 0xE744, 0xffff>;
58 def VGBM : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16>;
61 def VGMB : BinaryVRIb<"vgmb", 0xE746, z_rotate_mask, v128b, 0>;
62 def VGMH : BinaryVRIb<"vgmh", 0xE746, z_rotate_mask, v128h, 1>;
63 def VGMF : BinaryVRIb<"vgmf", 0xE746, z_rotate_mask, v128f, 2>;
64 def VGMG : BinaryVRIb<"vgmg", 0xE746, z_rotate_mask, v128g, 3>;
66 // Load element immediate.
68 // We want these instructions to be used ahead of VLVG* where possible.
69 // However, VLVG* takes a variable BD-format index whereas VLEI takes
70 // a plain immediate index. This means that VLVG* has an extra "base"
71 // register operand and is 3 units more complex. Bumping the complexity
72 // of the VLEI* instructions by 4 means that they are strictly better
73 // than VLVG* in cases where both forms match.
74 let AddedComplexity = 4 in {
75 def VLEIB : TernaryVRIa<"vleib", 0xE740, z_vector_insert,
76 v128b, v128b, imm32sx16trunc, imm32zx4>;
77 def VLEIH : TernaryVRIa<"vleih", 0xE741, z_vector_insert,
78 v128h, v128h, imm32sx16trunc, imm32zx3>;
79 def VLEIF : TernaryVRIa<"vleif", 0xE743, z_vector_insert,
80 v128f, v128f, imm32sx16, imm32zx2>;
81 def VLEIG : TernaryVRIa<"vleig", 0xE742, z_vector_insert,
82 v128g, v128g, imm64sx16, imm32zx1>;
85 // Replicate immediate.
86 def VREPIB : UnaryVRIa<"vrepib", 0xE745, z_replicate, v128b, imm32sx16, 0>;
87 def VREPIH : UnaryVRIa<"vrepih", 0xE745, z_replicate, v128h, imm32sx16, 1>;
88 def VREPIF : UnaryVRIa<"vrepif", 0xE745, z_replicate, v128f, imm32sx16, 2>;
89 def VREPIG : UnaryVRIa<"vrepig", 0xE745, z_replicate, v128g, imm32sx16, 3>;
92 //===----------------------------------------------------------------------===//
94 //===----------------------------------------------------------------------===//
96 let Predicates = [FeatureVector] in {
98 def VL : UnaryVRX<"vl", 0xE706, null_frag, v128any, 16>;
100 // Load to block boundary. The number of loaded bytes is only known
102 def VLBB : BinaryVRX<"vlbb", 0xE707, null_frag, v128any, 0>;
104 // Load count to block boundary.
106 def LCBB : InstRXE<0xE727, (outs GR32:$R1),
107 (ins bdxaddr12only:$XBD2, imm32zx4:$M3),
108 "lcbb\t$R1, $XBD2, $M3", []>;
110 // Load with length. The number of loaded bytes is only known at run time.
111 def VLL : BinaryVRSb<"vll", 0xE737, null_frag, 0>;
114 def VLM : LoadMultipleVRSa<"vlm", 0xE736>;
116 // Load and replicate
117 def VLREPB : UnaryVRX<"vlrepb", 0xE705, z_replicate_loadi8, v128b, 1, 0>;
118 def VLREPH : UnaryVRX<"vlreph", 0xE705, z_replicate_loadi16, v128h, 2, 1>;
119 def VLREPF : UnaryVRX<"vlrepf", 0xE705, z_replicate_loadi32, v128f, 4, 2>;
120 def VLREPG : UnaryVRX<"vlrepg", 0xE705, z_replicate_loadi64, v128g, 8, 3>;
122 // Load logical element and zero.
123 def VLLEZB : UnaryVRX<"vllezb", 0xE704, z_vllezi8, v128b, 1, 0>;
124 def VLLEZH : UnaryVRX<"vllezh", 0xE704, z_vllezi16, v128h, 2, 1>;
125 def VLLEZF : UnaryVRX<"vllezf", 0xE704, z_vllezi32, v128f, 4, 2>;
126 def VLLEZG : UnaryVRX<"vllezg", 0xE704, z_vllezi64, v128g, 8, 3>;
129 def VLEB : TernaryVRX<"vleb", 0xE700, z_vlei8, v128b, v128b, 1, imm32zx4>;
130 def VLEH : TernaryVRX<"vleh", 0xE701, z_vlei16, v128h, v128h, 2, imm32zx3>;
131 def VLEF : TernaryVRX<"vlef", 0xE703, z_vlei32, v128f, v128f, 4, imm32zx2>;
132 def VLEG : TernaryVRX<"vleg", 0xE702, z_vlei64, v128g, v128g, 8, imm32zx1>;
135 def VGEF : TernaryVRV<"vgef", 0xE713, 4, imm32zx2>;
136 def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>;
139 // Use replicating loads if we're inserting a single element into an
140 // undefined vector. This avoids a false dependency on the previous
141 // register contents.
142 multiclass ReplicatePeephole<Instruction vlrep, ValueType vectype,
143 SDPatternOperator load, ValueType scalartype> {
144 def : Pat<(vectype (z_vector_insert
145 (undef), (scalartype (load bdxaddr12only:$addr)), 0)),
146 (vlrep bdxaddr12only:$addr)>;
147 def : Pat<(vectype (scalar_to_vector
148 (scalartype (load bdxaddr12only:$addr)))),
149 (vlrep bdxaddr12only:$addr)>;
151 defm : ReplicatePeephole<VLREPB, v16i8, anyextloadi8, i32>;
152 defm : ReplicatePeephole<VLREPH, v8i16, anyextloadi16, i32>;
153 defm : ReplicatePeephole<VLREPF, v4i32, load, i32>;
154 defm : ReplicatePeephole<VLREPG, v2i64, load, i64>;
156 //===----------------------------------------------------------------------===//
158 //===----------------------------------------------------------------------===//
160 let Predicates = [FeatureVector] in {
162 def VST : StoreVRX<"vst", 0xE70E, null_frag, v128any, 16>;
164 // Store with length. The number of stored bytes is only known at run time.
165 def VSTL : StoreLengthVRSb<"vstl", 0xE73F, null_frag, 0>;
168 def VSTM : StoreMultipleVRSa<"vstm", 0xE73E>;
171 def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, z_vstei8, v128b, 1, imm32zx4>;
172 def VSTEH : StoreBinaryVRX<"vsteh", 0xE709, z_vstei16, v128h, 2, imm32zx3>;
173 def VSTEF : StoreBinaryVRX<"vstef", 0xE70B, z_vstei32, v128f, 4, imm32zx2>;
174 def VSTEG : StoreBinaryVRX<"vsteg", 0xE70A, z_vstei64, v128g, 8, imm32zx1>;
177 def VSCEF : StoreBinaryVRV<"vscef", 0xE71B, 4, imm32zx2>;
178 def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>;
181 //===----------------------------------------------------------------------===//
182 // Selects and permutes
183 //===----------------------------------------------------------------------===//
185 let Predicates = [FeatureVector] in {
187 def VMRHB : BinaryVRRc<"vmrhb", 0xE761, z_merge_high, v128b, v128b, 0>;
188 def VMRHH : BinaryVRRc<"vmrhh", 0xE761, z_merge_high, v128h, v128h, 1>;
189 def VMRHF : BinaryVRRc<"vmrhf", 0xE761, z_merge_high, v128f, v128f, 2>;
190 def VMRHG : BinaryVRRc<"vmrhg", 0xE761, z_merge_high, v128g, v128g, 3>;
193 def VMRLB : BinaryVRRc<"vmrlb", 0xE760, z_merge_low, v128b, v128b, 0>;
194 def VMRLH : BinaryVRRc<"vmrlh", 0xE760, z_merge_low, v128h, v128h, 1>;
195 def VMRLF : BinaryVRRc<"vmrlf", 0xE760, z_merge_low, v128f, v128f, 2>;
196 def VMRLG : BinaryVRRc<"vmrlg", 0xE760, z_merge_low, v128g, v128g, 3>;
199 def VPERM : TernaryVRRe<"vperm", 0xE78C, z_permute, v128b, v128b>;
201 // Permute doubleword immediate.
202 def VPDI : TernaryVRRc<"vpdi", 0xE784, z_permute_dwords, v128g, v128g>;
205 def VREPB : BinaryVRIc<"vrepb", 0xE74D, z_splat, v128b, v128b, 0>;
206 def VREPH : BinaryVRIc<"vreph", 0xE74D, z_splat, v128h, v128h, 1>;
207 def VREPF : BinaryVRIc<"vrepf", 0xE74D, z_splat, v128f, v128f, 2>;
208 def VREPG : BinaryVRIc<"vrepg", 0xE74D, z_splat, v128g, v128g, 3>;
211 def VSEL : TernaryVRRe<"vsel", 0xE78D, null_frag, v128any, v128any>;
214 //===----------------------------------------------------------------------===//
215 // Widening and narrowing
216 //===----------------------------------------------------------------------===//
218 let Predicates = [FeatureVector] in {
220 def VPKH : BinaryVRRc<"vpkh", 0xE794, z_pack, v128b, v128h, 1>;
221 def VPKF : BinaryVRRc<"vpkf", 0xE794, z_pack, v128h, v128f, 2>;
222 def VPKG : BinaryVRRc<"vpkg", 0xE794, z_pack, v128f, v128g, 3>;
225 defm VPKSH : BinaryVRRbSPair<"vpksh", 0xE797, null_frag, null_frag,
227 defm VPKSF : BinaryVRRbSPair<"vpksf", 0xE797, null_frag, null_frag,
229 defm VPKSG : BinaryVRRbSPair<"vpksg", 0xE797, null_frag, null_frag,
232 // Pack saturate logical.
233 defm VPKLSH : BinaryVRRbSPair<"vpklsh", 0xE795, null_frag, null_frag,
235 defm VPKLSF : BinaryVRRbSPair<"vpklsf", 0xE795, null_frag, null_frag,
237 defm VPKLSG : BinaryVRRbSPair<"vpklsg", 0xE795, null_frag, null_frag,
240 // Sign-extend to doubleword.
241 def VSEGB : UnaryVRRa<"vsegb", 0xE75F, z_vsei8, v128g, v128g, 0>;
242 def VSEGH : UnaryVRRa<"vsegh", 0xE75F, z_vsei16, v128g, v128g, 1>;
243 def VSEGF : UnaryVRRa<"vsegf", 0xE75F, z_vsei32, v128g, v128g, 2>;
244 def : Pat<(z_vsei8_by_parts (v16i8 VR128:$src)), (VSEGB VR128:$src)>;
245 def : Pat<(z_vsei16_by_parts (v8i16 VR128:$src)), (VSEGH VR128:$src)>;
246 def : Pat<(z_vsei32_by_parts (v4i32 VR128:$src)), (VSEGF VR128:$src)>;
249 def VUPHB : UnaryVRRa<"vuphb", 0xE7D7, null_frag, v128h, v128b, 0>;
250 def VUPHH : UnaryVRRa<"vuphh", 0xE7D7, null_frag, v128f, v128h, 1>;
251 def VUPHF : UnaryVRRa<"vuphf", 0xE7D7, null_frag, v128g, v128f, 2>;
253 // Unpack logical high.
254 def VUPLHB : UnaryVRRa<"vuplhb", 0xE7D5, null_frag, v128h, v128b, 0>;
255 def VUPLHH : UnaryVRRa<"vuplhh", 0xE7D5, null_frag, v128f, v128h, 1>;
256 def VUPLHF : UnaryVRRa<"vuplhf", 0xE7D5, null_frag, v128g, v128f, 2>;
259 def VUPLB : UnaryVRRa<"vuplb", 0xE7D6, null_frag, v128h, v128b, 0>;
260 def VUPLHW : UnaryVRRa<"vuplhw", 0xE7D6, null_frag, v128f, v128h, 1>;
261 def VUPLF : UnaryVRRa<"vuplf", 0xE7D6, null_frag, v128g, v128f, 2>;
263 // Unpack logical low.
264 def VUPLLB : UnaryVRRa<"vupllb", 0xE7D4, null_frag, v128h, v128b, 0>;
265 def VUPLLH : UnaryVRRa<"vupllh", 0xE7D4, null_frag, v128f, v128h, 1>;
266 def VUPLLF : UnaryVRRa<"vupllf", 0xE7D4, null_frag, v128g, v128f, 2>;
269 //===----------------------------------------------------------------------===//
270 // Instantiating generic operations for specific types.
271 //===----------------------------------------------------------------------===//
273 multiclass GenericVectorOps<ValueType type, ValueType inttype> {
274 let Predicates = [FeatureVector] in {
275 def : Pat<(type (load bdxaddr12only:$addr)),
276 (VL bdxaddr12only:$addr)>;
277 def : Pat<(store (type VR128:$src), bdxaddr12only:$addr),
278 (VST VR128:$src, bdxaddr12only:$addr)>;
279 def : Pat<(type (vselect (inttype VR128:$x), VR128:$y, VR128:$z)),
280 (VSEL VR128:$y, VR128:$z, VR128:$x)>;
281 def : Pat<(type (vselect (inttype (z_vnot VR128:$x)), VR128:$y, VR128:$z)),
282 (VSEL VR128:$z, VR128:$y, VR128:$x)>;
286 defm : GenericVectorOps<v16i8, v16i8>;
287 defm : GenericVectorOps<v8i16, v8i16>;
288 defm : GenericVectorOps<v4i32, v4i32>;
289 defm : GenericVectorOps<v2i64, v2i64>;
291 //===----------------------------------------------------------------------===//
292 // Integer arithmetic
293 //===----------------------------------------------------------------------===//
295 let Predicates = [FeatureVector] in {
297 def VAB : BinaryVRRc<"vab", 0xE7F3, add, v128b, v128b, 0>;
298 def VAH : BinaryVRRc<"vah", 0xE7F3, add, v128h, v128h, 1>;
299 def VAF : BinaryVRRc<"vaf", 0xE7F3, add, v128f, v128f, 2>;
300 def VAG : BinaryVRRc<"vag", 0xE7F3, add, v128g, v128g, 3>;
301 def VAQ : BinaryVRRc<"vaq", 0xE7F3, null_frag, v128q, v128q, 4>;
303 // Add compute carry.
304 def VACCB : BinaryVRRc<"vaccb", 0xE7F1, null_frag, v128b, v128b, 0>;
305 def VACCH : BinaryVRRc<"vacch", 0xE7F1, null_frag, v128h, v128h, 1>;
306 def VACCF : BinaryVRRc<"vaccf", 0xE7F1, null_frag, v128f, v128f, 2>;
307 def VACCG : BinaryVRRc<"vaccg", 0xE7F1, null_frag, v128g, v128g, 3>;
308 def VACCQ : BinaryVRRc<"vaccq", 0xE7F1, null_frag, v128q, v128q, 4>;
311 def VACQ : TernaryVRRd<"vacq", 0xE7BB, null_frag, v128q, v128q, 4>;
313 // Add with carry compute carry.
314 def VACCCQ : TernaryVRRd<"vacccq", 0xE7B9, null_frag, v128q, v128q, 4>;
317 def VN : BinaryVRRc<"vn", 0xE768, null_frag, v128any, v128any>;
319 // And with complement.
320 def VNC : BinaryVRRc<"vnc", 0xE769, null_frag, v128any, v128any>;
323 def VAVGB : BinaryVRRc<"vavgb", 0xE7F2, null_frag, v128b, v128b, 0>;
324 def VAVGH : BinaryVRRc<"vavgh", 0xE7F2, null_frag, v128h, v128h, 1>;
325 def VAVGF : BinaryVRRc<"vavgf", 0xE7F2, null_frag, v128f, v128f, 2>;
326 def VAVGG : BinaryVRRc<"vavgg", 0xE7F2, null_frag, v128g, v128g, 3>;
329 def VAVGLB : BinaryVRRc<"vavglb", 0xE7F0, null_frag, v128b, v128b, 0>;
330 def VAVGLH : BinaryVRRc<"vavglh", 0xE7F0, null_frag, v128h, v128h, 1>;
331 def VAVGLF : BinaryVRRc<"vavglf", 0xE7F0, null_frag, v128f, v128f, 2>;
332 def VAVGLG : BinaryVRRc<"vavglg", 0xE7F0, null_frag, v128g, v128g, 3>;
335 def VCKSM : BinaryVRRc<"vcksm", 0xE766, null_frag, v128any, v128any>;
337 // Count leading zeros.
338 def VCLZB : UnaryVRRa<"vclzb", 0xE753, ctlz, v128b, v128b, 0>;
339 def VCLZH : UnaryVRRa<"vclzh", 0xE753, ctlz, v128h, v128h, 1>;
340 def VCLZF : UnaryVRRa<"vclzf", 0xE753, ctlz, v128f, v128f, 2>;
341 def VCLZG : UnaryVRRa<"vclzg", 0xE753, ctlz, v128g, v128g, 3>;
343 // Count trailing zeros.
344 def VCTZB : UnaryVRRa<"vctzb", 0xE752, cttz, v128b, v128b, 0>;
345 def VCTZH : UnaryVRRa<"vctzh", 0xE752, cttz, v128h, v128h, 1>;
346 def VCTZF : UnaryVRRa<"vctzf", 0xE752, cttz, v128f, v128f, 2>;
347 def VCTZG : UnaryVRRa<"vctzg", 0xE752, cttz, v128g, v128g, 3>;
350 def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>;
352 // Galois field multiply sum.
353 def VGFMB : BinaryVRRc<"vgfmb", 0xE7B4, null_frag, v128b, v128b, 0>;
354 def VGFMH : BinaryVRRc<"vgfmh", 0xE7B4, null_frag, v128h, v128h, 1>;
355 def VGFMF : BinaryVRRc<"vgfmf", 0xE7B4, null_frag, v128f, v128f, 2>;
356 def VGFMG : BinaryVRRc<"vgfmg", 0xE7B4, null_frag, v128g, v128g, 3>;
358 // Galois field multiply sum and accumulate.
359 def VGFMAB : TernaryVRRd<"vgfmab", 0xE7BC, null_frag, v128b, v128b, 0>;
360 def VGFMAH : TernaryVRRd<"vgfmah", 0xE7BC, null_frag, v128h, v128h, 1>;
361 def VGFMAF : TernaryVRRd<"vgfmaf", 0xE7BC, null_frag, v128f, v128f, 2>;
362 def VGFMAG : TernaryVRRd<"vgfmag", 0xE7BC, null_frag, v128g, v128g, 3>;
365 def VLCB : UnaryVRRa<"vlcb", 0xE7DE, z_vneg, v128b, v128b, 0>;
366 def VLCH : UnaryVRRa<"vlch", 0xE7DE, z_vneg, v128h, v128h, 1>;
367 def VLCF : UnaryVRRa<"vlcf", 0xE7DE, z_vneg, v128f, v128f, 2>;
368 def VLCG : UnaryVRRa<"vlcg", 0xE7DE, z_vneg, v128g, v128g, 3>;
371 def VLPB : UnaryVRRa<"vlpb", 0xE7DF, z_viabs8, v128b, v128b, 0>;
372 def VLPH : UnaryVRRa<"vlph", 0xE7DF, z_viabs16, v128h, v128h, 1>;
373 def VLPF : UnaryVRRa<"vlpf", 0xE7DF, z_viabs32, v128f, v128f, 2>;
374 def VLPG : UnaryVRRa<"vlpg", 0xE7DF, z_viabs64, v128g, v128g, 3>;
377 def VMXB : BinaryVRRc<"vmxb", 0xE7FF, null_frag, v128b, v128b, 0>;
378 def VMXH : BinaryVRRc<"vmxh", 0xE7FF, null_frag, v128h, v128h, 1>;
379 def VMXF : BinaryVRRc<"vmxf", 0xE7FF, null_frag, v128f, v128f, 2>;
380 def VMXG : BinaryVRRc<"vmxg", 0xE7FF, null_frag, v128g, v128g, 3>;
383 def VMXLB : BinaryVRRc<"vmxlb", 0xE7FD, null_frag, v128b, v128b, 0>;
384 def VMXLH : BinaryVRRc<"vmxlh", 0xE7FD, null_frag, v128h, v128h, 1>;
385 def VMXLF : BinaryVRRc<"vmxlf", 0xE7FD, null_frag, v128f, v128f, 2>;
386 def VMXLG : BinaryVRRc<"vmxlg", 0xE7FD, null_frag, v128g, v128g, 3>;
389 def VMNB : BinaryVRRc<"vmnb", 0xE7FE, null_frag, v128b, v128b, 0>;
390 def VMNH : BinaryVRRc<"vmnh", 0xE7FE, null_frag, v128h, v128h, 1>;
391 def VMNF : BinaryVRRc<"vmnf", 0xE7FE, null_frag, v128f, v128f, 2>;
392 def VMNG : BinaryVRRc<"vmng", 0xE7FE, null_frag, v128g, v128g, 3>;
395 def VMNLB : BinaryVRRc<"vmnlb", 0xE7FC, null_frag, v128b, v128b, 0>;
396 def VMNLH : BinaryVRRc<"vmnlh", 0xE7FC, null_frag, v128h, v128h, 1>;
397 def VMNLF : BinaryVRRc<"vmnlf", 0xE7FC, null_frag, v128f, v128f, 2>;
398 def VMNLG : BinaryVRRc<"vmnlg", 0xE7FC, null_frag, v128g, v128g, 3>;
400 // Multiply and add low.
401 def VMALB : TernaryVRRd<"vmalb", 0xE7AA, z_muladd, v128b, v128b, 0>;
402 def VMALHW : TernaryVRRd<"vmalhw", 0xE7AA, z_muladd, v128h, v128h, 1>;
403 def VMALF : TernaryVRRd<"vmalf", 0xE7AA, z_muladd, v128f, v128f, 2>;
405 // Multiply and add high.
406 def VMAHB : TernaryVRRd<"vmahb", 0xE7AB, null_frag, v128b, v128b, 0>;
407 def VMAHH : TernaryVRRd<"vmahh", 0xE7AB, null_frag, v128h, v128h, 1>;
408 def VMAHF : TernaryVRRd<"vmahf", 0xE7AB, null_frag, v128f, v128f, 2>;
410 // Multiply and add logical high.
411 def VMALHB : TernaryVRRd<"vmalhb", 0xE7A9, null_frag, v128b, v128b, 0>;
412 def VMALHH : TernaryVRRd<"vmalhh", 0xE7A9, null_frag, v128h, v128h, 1>;
413 def VMALHF : TernaryVRRd<"vmalhf", 0xE7A9, null_frag, v128f, v128f, 2>;
415 // Multiply and add even.
416 def VMAEB : TernaryVRRd<"vmaeb", 0xE7AE, null_frag, v128h, v128b, 0>;
417 def VMAEH : TernaryVRRd<"vmaeh", 0xE7AE, null_frag, v128f, v128h, 1>;
418 def VMAEF : TernaryVRRd<"vmaef", 0xE7AE, null_frag, v128g, v128f, 2>;
420 // Multiply and add logical even.
421 def VMALEB : TernaryVRRd<"vmaleb", 0xE7AC, null_frag, v128h, v128b, 0>;
422 def VMALEH : TernaryVRRd<"vmaleh", 0xE7AC, null_frag, v128f, v128h, 1>;
423 def VMALEF : TernaryVRRd<"vmalef", 0xE7AC, null_frag, v128g, v128f, 2>;
425 // Multiply and add odd.
426 def VMAOB : TernaryVRRd<"vmaob", 0xE7AF, null_frag, v128h, v128b, 0>;
427 def VMAOH : TernaryVRRd<"vmaoh", 0xE7AF, null_frag, v128f, v128h, 1>;
428 def VMAOF : TernaryVRRd<"vmaof", 0xE7AF, null_frag, v128g, v128f, 2>;
430 // Multiply and add logical odd.
431 def VMALOB : TernaryVRRd<"vmalob", 0xE7AD, null_frag, v128h, v128b, 0>;
432 def VMALOH : TernaryVRRd<"vmaloh", 0xE7AD, null_frag, v128f, v128h, 1>;
433 def VMALOF : TernaryVRRd<"vmalof", 0xE7AD, null_frag, v128g, v128f, 2>;
436 def VMHB : BinaryVRRc<"vmhb", 0xE7A3, null_frag, v128b, v128b, 0>;
437 def VMHH : BinaryVRRc<"vmhh", 0xE7A3, null_frag, v128h, v128h, 1>;
438 def VMHF : BinaryVRRc<"vmhf", 0xE7A3, null_frag, v128f, v128f, 2>;
440 // Multiply logical high.
441 def VMLHB : BinaryVRRc<"vmlhb", 0xE7A1, null_frag, v128b, v128b, 0>;
442 def VMLHH : BinaryVRRc<"vmlhh", 0xE7A1, null_frag, v128h, v128h, 1>;
443 def VMLHF : BinaryVRRc<"vmlhf", 0xE7A1, null_frag, v128f, v128f, 2>;
446 def VMLB : BinaryVRRc<"vmlb", 0xE7A2, mul, v128b, v128b, 0>;
447 def VMLHW : BinaryVRRc<"vmlhw", 0xE7A2, mul, v128h, v128h, 1>;
448 def VMLF : BinaryVRRc<"vmlf", 0xE7A2, mul, v128f, v128f, 2>;
451 def VMEB : BinaryVRRc<"vmeb", 0xE7A6, null_frag, v128h, v128b, 0>;
452 def VMEH : BinaryVRRc<"vmeh", 0xE7A6, null_frag, v128f, v128h, 1>;
453 def VMEF : BinaryVRRc<"vmef", 0xE7A6, null_frag, v128g, v128f, 2>;
455 // Multiply logical even.
456 def VMLEB : BinaryVRRc<"vmleb", 0xE7A4, null_frag, v128h, v128b, 0>;
457 def VMLEH : BinaryVRRc<"vmleh", 0xE7A4, null_frag, v128f, v128h, 1>;
458 def VMLEF : BinaryVRRc<"vmlef", 0xE7A4, null_frag, v128g, v128f, 2>;
461 def VMOB : BinaryVRRc<"vmob", 0xE7A7, null_frag, v128h, v128b, 0>;
462 def VMOH : BinaryVRRc<"vmoh", 0xE7A7, null_frag, v128f, v128h, 1>;
463 def VMOF : BinaryVRRc<"vmof", 0xE7A7, null_frag, v128g, v128f, 2>;
465 // Multiply logical odd.
466 def VMLOB : BinaryVRRc<"vmlob", 0xE7A5, null_frag, v128h, v128b, 0>;
467 def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, null_frag, v128f, v128h, 1>;
468 def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, null_frag, v128g, v128f, 2>;
471 def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>;
474 def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>;
477 def VPOPCT : BinaryVRRa<"vpopct", 0xE750>;
478 def : Pat<(v16i8 (z_popcnt VR128:$x)), (VPOPCT VR128:$x, 0)>;
480 // Element rotate left logical (with vector shift amount).
481 def VERLLVB : BinaryVRRc<"verllvb", 0xE773, null_frag, v128b, v128b, 0>;
482 def VERLLVH : BinaryVRRc<"verllvh", 0xE773, null_frag, v128h, v128h, 1>;
483 def VERLLVF : BinaryVRRc<"verllvf", 0xE773, null_frag, v128f, v128f, 2>;
484 def VERLLVG : BinaryVRRc<"verllvg", 0xE773, null_frag, v128g, v128g, 3>;
486 // Element rotate left logical (with scalar shift amount).
487 def VERLLB : BinaryVRSa<"verllb", 0xE733, null_frag, v128b, v128b, 0>;
488 def VERLLH : BinaryVRSa<"verllh", 0xE733, null_frag, v128h, v128h, 1>;
489 def VERLLF : BinaryVRSa<"verllf", 0xE733, null_frag, v128f, v128f, 2>;
490 def VERLLG : BinaryVRSa<"verllg", 0xE733, null_frag, v128g, v128g, 3>;
492 // Element rotate and insert under mask.
493 def VERIMB : QuaternaryVRId<"verimb", 0xE772, null_frag, v128b, v128b, 0>;
494 def VERIMH : QuaternaryVRId<"verimh", 0xE772, null_frag, v128h, v128h, 1>;
495 def VERIMF : QuaternaryVRId<"verimf", 0xE772, null_frag, v128f, v128f, 2>;
496 def VERIMG : QuaternaryVRId<"verimg", 0xE772, null_frag, v128g, v128g, 3>;
498 // Element shift left (with vector shift amount).
499 def VESLVB : BinaryVRRc<"veslvb", 0xE770, z_vshl, v128b, v128b, 0>;
500 def VESLVH : BinaryVRRc<"veslvh", 0xE770, z_vshl, v128h, v128h, 1>;
501 def VESLVF : BinaryVRRc<"veslvf", 0xE770, z_vshl, v128f, v128f, 2>;
502 def VESLVG : BinaryVRRc<"veslvg", 0xE770, z_vshl, v128g, v128g, 3>;
504 // Element shift left (with scalar shift amount).
505 def VESLB : BinaryVRSa<"veslb", 0xE730, z_vshl_by_scalar, v128b, v128b, 0>;
506 def VESLH : BinaryVRSa<"veslh", 0xE730, z_vshl_by_scalar, v128h, v128h, 1>;
507 def VESLF : BinaryVRSa<"veslf", 0xE730, z_vshl_by_scalar, v128f, v128f, 2>;
508 def VESLG : BinaryVRSa<"veslg", 0xE730, z_vshl_by_scalar, v128g, v128g, 3>;
510 // Element shift right arithmetic (with vector shift amount).
511 def VESRAVB : BinaryVRRc<"vesravb", 0xE77A, z_vsra, v128b, v128b, 0>;
512 def VESRAVH : BinaryVRRc<"vesravh", 0xE77A, z_vsra, v128h, v128h, 1>;
513 def VESRAVF : BinaryVRRc<"vesravf", 0xE77A, z_vsra, v128f, v128f, 2>;
514 def VESRAVG : BinaryVRRc<"vesravg", 0xE77A, z_vsra, v128g, v128g, 3>;
516 // Element shift right arithmetic (with scalar shift amount).
517 def VESRAB : BinaryVRSa<"vesrab", 0xE73A, z_vsra_by_scalar, v128b, v128b, 0>;
518 def VESRAH : BinaryVRSa<"vesrah", 0xE73A, z_vsra_by_scalar, v128h, v128h, 1>;
519 def VESRAF : BinaryVRSa<"vesraf", 0xE73A, z_vsra_by_scalar, v128f, v128f, 2>;
520 def VESRAG : BinaryVRSa<"vesrag", 0xE73A, z_vsra_by_scalar, v128g, v128g, 3>;
522 // Element shift right logical (with vector shift amount).
523 def VESRLVB : BinaryVRRc<"vesrlvb", 0xE778, z_vsrl, v128b, v128b, 0>;
524 def VESRLVH : BinaryVRRc<"vesrlvh", 0xE778, z_vsrl, v128h, v128h, 1>;
525 def VESRLVF : BinaryVRRc<"vesrlvf", 0xE778, z_vsrl, v128f, v128f, 2>;
526 def VESRLVG : BinaryVRRc<"vesrlvg", 0xE778, z_vsrl, v128g, v128g, 3>;
528 // Element shift right logical (with scalar shift amount).
529 def VESRLB : BinaryVRSa<"vesrlb", 0xE738, z_vsrl_by_scalar, v128b, v128b, 0>;
530 def VESRLH : BinaryVRSa<"vesrlh", 0xE738, z_vsrl_by_scalar, v128h, v128h, 1>;
531 def VESRLF : BinaryVRSa<"vesrlf", 0xE738, z_vsrl_by_scalar, v128f, v128f, 2>;
532 def VESRLG : BinaryVRSa<"vesrlg", 0xE738, z_vsrl_by_scalar, v128g, v128g, 3>;
535 def VSL : BinaryVRRc<"vsl", 0xE774, null_frag, v128b, v128b>;
537 // Shift left by byte.
538 def VSLB : BinaryVRRc<"vslb", 0xE775, null_frag, v128b, v128b>;
540 // Shift left double by byte.
541 def VSLDB : TernaryVRId<"vsldb", 0xE777, z_shl_double, v128b, v128b, 0>;
543 // Shift right arithmetic.
544 def VSRA : BinaryVRRc<"vsra", 0xE77E, null_frag, v128b, v128b>;
546 // Shift right arithmetic by byte.
547 def VSRAB : BinaryVRRc<"vsrab", 0xE77F, null_frag, v128b, v128b>;
549 // Shift right logical.
550 def VSRL : BinaryVRRc<"vsrl", 0xE77C, null_frag, v128b, v128b>;
552 // Shift right logical by byte.
553 def VSRLB : BinaryVRRc<"vsrlb", 0xE77D, null_frag, v128b, v128b>;
556 def VSB : BinaryVRRc<"vsb", 0xE7F7, sub, v128b, v128b, 0>;
557 def VSH : BinaryVRRc<"vsh", 0xE7F7, sub, v128h, v128h, 1>;
558 def VSF : BinaryVRRc<"vsf", 0xE7F7, sub, v128f, v128f, 2>;
559 def VSG : BinaryVRRc<"vsg", 0xE7F7, sub, v128g, v128g, 3>;
560 def VSQ : BinaryVRRc<"vsq", 0xE7F7, null_frag, v128q, v128q, 4>;
562 // Subtract compute borrow indication.
563 def VSCBIB : BinaryVRRc<"vscbib", 0xE7F5, null_frag, v128b, v128b, 0>;
564 def VSCBIH : BinaryVRRc<"vscbih", 0xE7F5, null_frag, v128h, v128h, 1>;
565 def VSCBIF : BinaryVRRc<"vscbif", 0xE7F5, null_frag, v128f, v128f, 2>;
566 def VSCBIG : BinaryVRRc<"vscbig", 0xE7F5, null_frag, v128g, v128g, 3>;
567 def VSCBIQ : BinaryVRRc<"vscbiq", 0xE7F5, null_frag, v128q, v128q, 4>;
569 // Subtract with borrow indication.
570 def VSBIQ : TernaryVRRd<"vsbiq", 0xE7BF, null_frag, v128q, v128q, 4>;
572 // Subtract with borrow compute borrow indication.
573 def VSBCBIQ : TernaryVRRd<"vsbcbiq", 0xE7BD, null_frag, v128q, v128q, 4>;
575 // Sum across doubleword.
576 def VSUMGH : BinaryVRRc<"vsumgh", 0xE765, z_vsum, v128g, v128h, 1>;
577 def VSUMGF : BinaryVRRc<"vsumgf", 0xE765, z_vsum, v128g, v128f, 2>;
579 // Sum across quadword.
580 def VSUMQF : BinaryVRRc<"vsumqf", 0xE767, z_vsum, v128q, v128f, 2>;
581 def VSUMQG : BinaryVRRc<"vsumqg", 0xE767, z_vsum, v128q, v128g, 3>;
584 def VSUMB : BinaryVRRc<"vsumb", 0xE764, z_vsum, v128f, v128b, 0>;
585 def VSUMH : BinaryVRRc<"vsumh", 0xE764, z_vsum, v128f, v128h, 1>;
588 // Instantiate the bitwise ops for type TYPE.
589 multiclass BitwiseVectorOps<ValueType type> {
590 let Predicates = [FeatureVector] in {
591 def : Pat<(type (and VR128:$x, VR128:$y)), (VN VR128:$x, VR128:$y)>;
592 def : Pat<(type (and VR128:$x, (z_vnot VR128:$y))),
593 (VNC VR128:$x, VR128:$y)>;
594 def : Pat<(type (or VR128:$x, VR128:$y)), (VO VR128:$x, VR128:$y)>;
595 def : Pat<(type (xor VR128:$x, VR128:$y)), (VX VR128:$x, VR128:$y)>;
596 def : Pat<(type (or (and VR128:$x, VR128:$z),
597 (and VR128:$y, (z_vnot VR128:$z)))),
598 (VSEL VR128:$x, VR128:$y, VR128:$z)>;
599 def : Pat<(type (z_vnot (or VR128:$x, VR128:$y))),
600 (VNO VR128:$x, VR128:$y)>;
601 def : Pat<(type (z_vnot VR128:$x)), (VNO VR128:$x, VR128:$x)>;
605 defm : BitwiseVectorOps<v16i8>;
606 defm : BitwiseVectorOps<v8i16>;
607 defm : BitwiseVectorOps<v4i32>;
608 defm : BitwiseVectorOps<v2i64>;
610 // Instantiate additional patterns for absolute-related expressions on
611 // type TYPE. LC is the negate instruction for TYPE and LP is the absolute
613 multiclass IntegerAbsoluteVectorOps<ValueType type, Instruction lc,
614 Instruction lp, int shift> {
615 let Predicates = [FeatureVector] in {
616 def : Pat<(type (vselect (type (z_vicmph_zero VR128:$x)),
617 (z_vneg VR128:$x), VR128:$x)),
619 def : Pat<(type (vselect (type (z_vnot (z_vicmph_zero VR128:$x))),
620 VR128:$x, (z_vneg VR128:$x))),
622 def : Pat<(type (vselect (type (z_vicmpl_zero VR128:$x)),
623 VR128:$x, (z_vneg VR128:$x))),
625 def : Pat<(type (vselect (type (z_vnot (z_vicmpl_zero VR128:$x))),
626 (z_vneg VR128:$x), VR128:$x)),
628 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)),
630 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))),
633 def : Pat<(type (or (and (z_vsra_by_scalar VR128:$x, (i32 shift)),
635 (and (z_vnot (z_vsra_by_scalar VR128:$x, (i32 shift))),
636 (z_vneg VR128:$x)))),
641 defm : IntegerAbsoluteVectorOps<v16i8, VLCB, VLPB, 7>;
642 defm : IntegerAbsoluteVectorOps<v8i16, VLCH, VLPH, 15>;
643 defm : IntegerAbsoluteVectorOps<v4i32, VLCF, VLPF, 31>;
644 defm : IntegerAbsoluteVectorOps<v2i64, VLCG, VLPG, 63>;
646 // Instantiate minimum- and maximum-related patterns for TYPE. CMPH is the
647 // signed or unsigned "set if greater than" comparison instruction and
648 // MIN and MAX are the associated minimum and maximum instructions.
649 multiclass IntegerMinMaxVectorOps<ValueType type, SDPatternOperator cmph,
650 Instruction min, Instruction max> {
651 let Predicates = [FeatureVector] in {
652 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$x, VR128:$y)),
653 (max VR128:$x, VR128:$y)>;
654 def : Pat<(type (vselect (cmph VR128:$x, VR128:$y), VR128:$y, VR128:$x)),
655 (min VR128:$x, VR128:$y)>;
656 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)),
657 VR128:$x, VR128:$y)),
658 (min VR128:$x, VR128:$y)>;
659 def : Pat<(type (vselect (z_vnot (cmph VR128:$x, VR128:$y)),
660 VR128:$y, VR128:$x)),
661 (max VR128:$x, VR128:$y)>;
666 defm : IntegerMinMaxVectorOps<v16i8, z_vicmph, VMNB, VMXB>;
667 defm : IntegerMinMaxVectorOps<v8i16, z_vicmph, VMNH, VMXH>;
668 defm : IntegerMinMaxVectorOps<v4i32, z_vicmph, VMNF, VMXF>;
669 defm : IntegerMinMaxVectorOps<v2i64, z_vicmph, VMNG, VMXG>;
672 defm : IntegerMinMaxVectorOps<v16i8, z_vicmphl, VMNLB, VMXLB>;
673 defm : IntegerMinMaxVectorOps<v8i16, z_vicmphl, VMNLH, VMXLH>;
674 defm : IntegerMinMaxVectorOps<v4i32, z_vicmphl, VMNLF, VMXLF>;
675 defm : IntegerMinMaxVectorOps<v2i64, z_vicmphl, VMNLG, VMXLG>;
677 //===----------------------------------------------------------------------===//
678 // Integer comparison
679 //===----------------------------------------------------------------------===//
681 let Predicates = [FeatureVector] in {
684 def VECB : CompareVRRa<"vecb", 0xE7DB, null_frag, v128b, 0>;
685 def VECH : CompareVRRa<"vech", 0xE7DB, null_frag, v128h, 1>;
686 def VECF : CompareVRRa<"vecf", 0xE7DB, null_frag, v128f, 2>;
687 def VECG : CompareVRRa<"vecg", 0xE7DB, null_frag, v128g, 3>;
690 // Element compare logical.
692 def VECLB : CompareVRRa<"veclb", 0xE7D9, null_frag, v128b, 0>;
693 def VECLH : CompareVRRa<"veclh", 0xE7D9, null_frag, v128h, 1>;
694 def VECLF : CompareVRRa<"veclf", 0xE7D9, null_frag, v128f, 2>;
695 def VECLG : CompareVRRa<"veclg", 0xE7D9, null_frag, v128g, 3>;
699 defm VCEQB : BinaryVRRbSPair<"vceqb", 0xE7F8, z_vicmpe, null_frag,
701 defm VCEQH : BinaryVRRbSPair<"vceqh", 0xE7F8, z_vicmpe, null_frag,
703 defm VCEQF : BinaryVRRbSPair<"vceqf", 0xE7F8, z_vicmpe, null_frag,
705 defm VCEQG : BinaryVRRbSPair<"vceqg", 0xE7F8, z_vicmpe, null_frag,
709 defm VCHB : BinaryVRRbSPair<"vchb", 0xE7FB, z_vicmph, null_frag,
711 defm VCHH : BinaryVRRbSPair<"vchh", 0xE7FB, z_vicmph, null_frag,
713 defm VCHF : BinaryVRRbSPair<"vchf", 0xE7FB, z_vicmph, null_frag,
715 defm VCHG : BinaryVRRbSPair<"vchg", 0xE7FB, z_vicmph, null_frag,
718 // Compare high logical.
719 defm VCHLB : BinaryVRRbSPair<"vchlb", 0xE7F9, z_vicmphl, null_frag,
721 defm VCHLH : BinaryVRRbSPair<"vchlh", 0xE7F9, z_vicmphl, null_frag,
723 defm VCHLF : BinaryVRRbSPair<"vchlf", 0xE7F9, z_vicmphl, null_frag,
725 defm VCHLG : BinaryVRRbSPair<"vchlg", 0xE7F9, z_vicmphl, null_frag,
730 def VTM : CompareVRRa<"vtm", 0xE7D8, null_frag, v128any, 0>;
733 //===----------------------------------------------------------------------===//
734 // Floating-point arithmetic
735 //===----------------------------------------------------------------------===//
737 let Predicates = [FeatureVector] in {
739 def VFADB : BinaryVRRc<"vfadb", 0xE7E3, null_frag, v128db, v128db, 3, 0>;
740 def WFADB : BinaryVRRc<"wfadb", 0xE7E3, null_frag, v64db, v64db, 3, 8>;
742 // Convert from fixed 64-bit.
743 def VCDGB : TernaryVRRa<"vcdgb", 0xE7C3, null_frag, v128db, v128g, 3, 0>;
744 def WCDGB : TernaryVRRa<"wcdgb", 0xE7C3, null_frag, v64db, v64g, 3, 8>;
746 // Convert from logical 64-bit.
747 def VCDLGB : TernaryVRRa<"vcdlgb", 0xE7C1, null_frag, v128db, v128g, 3, 0>;
748 def WCDLGB : TernaryVRRa<"wcdlgb", 0xE7C1, null_frag, v64db, v64g, 3, 8>;
750 // Convert to fixed 64-bit.
751 def VCGDB : TernaryVRRa<"vcgdb", 0xE7C2, null_frag, v128g, v128db, 3, 0>;
752 def WCGDB : TernaryVRRa<"wcgdb", 0xE7C2, null_frag, v64g, v64db, 3, 8>;
754 // Convert to logical 64-bit.
755 def VCLGDB : TernaryVRRa<"vclgdb", 0xE7C0, null_frag, v128g, v128db, 3, 0>;
756 def WCLGDB : TernaryVRRa<"wclgdb", 0xE7C0, null_frag, v64g, v64db, 3, 8>;
759 def VFDDB : BinaryVRRc<"vfddb", 0xE7E5, null_frag, v128db, v128db, 3, 0>;
760 def WFDDB : BinaryVRRc<"wfddb", 0xE7E5, null_frag, v64db, v64db, 3, 8>;
763 def VFIDB : TernaryVRRa<"vfidb", 0xE7C7, null_frag, v128db, v128db, 3, 0>;
764 def WFIDB : TernaryVRRa<"wfidb", 0xE7C7, null_frag, v64db, v64db, 3, 8>;
767 def VLDEB : UnaryVRRa<"vldeb", 0xE7C4, null_frag, v128db, v128eb, 2, 0>;
768 def WLDEB : UnaryVRRa<"wldeb", 0xE7C4, null_frag, v64db, v32eb, 2, 8>;
771 def VLEDB : TernaryVRRa<"vledb", 0xE7C5, null_frag, v128eb, v128db, 3, 0>;
772 def WLEDB : TernaryVRRa<"wledb", 0xE7C5, null_frag, v32eb, v64db, 3, 8>;
775 def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, null_frag, v128db, v128db, 3, 0>;
776 def WFMDB : BinaryVRRc<"wfmdb", 0xE7E7, null_frag, v64db, v64db, 3, 8>;
779 def VFMADB : TernaryVRRe<"vfmadb", 0xE78F, null_frag, v128db, v128db, 0, 3>;
780 def WFMADB : TernaryVRRe<"wfmadb", 0xE78F, null_frag, v64db, v64db, 8, 3>;
782 // Multiply and subtract.
783 def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, null_frag, v128db, v128db, 0, 3>;
784 def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, null_frag, v64db, v64db, 8, 3>;
787 def VFLCDB : UnaryVRRa<"vflcdb", 0xE7CC, null_frag, v128db, v128db, 3, 0, 0>;
788 def WFLCDB : UnaryVRRa<"wflcdb", 0xE7CC, null_frag, v64db, v64db, 3, 8, 0>;
791 def VFLNDB : UnaryVRRa<"vflndb", 0xE7CC, null_frag, v128db, v128db, 3, 0, 1>;
792 def WFLNDB : UnaryVRRa<"wflndb", 0xE7CC, null_frag, v64db, v64db, 3, 8, 1>;
795 def VFLPDB : UnaryVRRa<"vflpdb", 0xE7CC, null_frag, v128db, v128db, 3, 0, 2>;
796 def WFLPDB : UnaryVRRa<"wflpdb", 0xE7CC, null_frag, v64db, v64db, 3, 8, 2>;
799 def VFSQDB : UnaryVRRa<"vfsqdb", 0xE7CE, null_frag, v128db, v128db, 3, 0>;
800 def WFSQDB : UnaryVRRa<"wfsqdb", 0xE7CE, null_frag, v64db, v64db, 3, 8>;
803 def VFSDB : BinaryVRRc<"vfsdb", 0xE7E2, null_frag, v128db, v128db, 3, 0>;
804 def WFSDB : BinaryVRRc<"wfsdb", 0xE7E2, null_frag, v64db, v64db, 3, 8>;
806 // Test data class immediate.
808 def VFTCIDB : BinaryVRIe<"vftcidb", 0xE74A, null_frag, v128g, v128db, 3, 0>;
809 def WFTCIDB : BinaryVRIe<"wftcidb", 0xE74A, null_frag, v64g, v64db, 3, 8>;
813 //===----------------------------------------------------------------------===//
814 // Floating-point comparison
815 //===----------------------------------------------------------------------===//
817 let Predicates = [FeatureVector] in {
820 def WFCDB : CompareVRRa<"wfcdb", 0xE7CB, null_frag, v64db, 3>;
822 // Compare and signal scalar.
824 def WFKDB : CompareVRRa<"wfkdb", 0xE7CA, null_frag, v64db, 3>;
827 defm VFCEDB : BinaryVRRcSPair<"vfcedb", 0xE7E8, null_frag, null_frag,
828 v128g, v128db, 3, 0>;
829 defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag,
833 defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, null_frag, null_frag,
834 v128g, v128db, 3, 0>;
835 defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag,
838 // Compare high or equal.
839 defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, null_frag, null_frag,
840 v128g, v128db, 3, 0>;
841 defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag,
845 //===----------------------------------------------------------------------===//
847 //===----------------------------------------------------------------------===//
849 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
850 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
851 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
853 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
854 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
855 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
857 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
858 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
859 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
861 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
862 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
863 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
865 //===----------------------------------------------------------------------===//
866 // Replicating scalars
867 //===----------------------------------------------------------------------===//
869 // Define patterns for replicating a scalar GR32 into a vector of type TYPE.
870 // INDEX is 8 minus the element size in bytes.
871 class VectorReplicateScalar<ValueType type, Instruction insn, bits<16> index>
872 : Pat<(type (z_replicate GR32:$scalar)),
873 (insn (VLVGP32 GR32:$scalar, GR32:$scalar), index)>;
875 def : VectorReplicateScalar<v16i8, VREPB, 7>;
876 def : VectorReplicateScalar<v8i16, VREPH, 3>;
877 def : VectorReplicateScalar<v4i32, VREPF, 1>;
879 // i64 replications are just a single isntruction.
880 def : Pat<(v2i64 (z_replicate GR64:$scalar)),
881 (VLVGP GR64:$scalar, GR64:$scalar)>;
883 //===----------------------------------------------------------------------===//
884 // String instructions
885 //===----------------------------------------------------------------------===//
887 let Predicates = [FeatureVector] in {
888 defm VFAEB : TernaryVRRbSPair<"vfaeb", 0xE782, null_frag, null_frag,
890 defm VFAEH : TernaryVRRbSPair<"vfaeh", 0xE782, null_frag, null_frag,
892 defm VFAEF : TernaryVRRbSPair<"vfaef", 0xE782, null_frag, null_frag,
894 defm VFAEZB : TernaryVRRbSPair<"vfaezb", 0xE782, null_frag, null_frag,
896 defm VFAEZH : TernaryVRRbSPair<"vfaezh", 0xE782, null_frag, null_frag,
898 defm VFAEZF : TernaryVRRbSPair<"vfaezf", 0xE782, null_frag, null_frag,
901 defm VFEEB : BinaryVRRbSPair<"vfeeb", 0xE780, null_frag, null_frag,
902 v128b, v128b, 0, 0, 1>;
903 defm VFEEH : BinaryVRRbSPair<"vfeeh", 0xE780, null_frag, null_frag,
904 v128h, v128h, 1, 0, 1>;
905 defm VFEEF : BinaryVRRbSPair<"vfeef", 0xE780, null_frag, null_frag,
906 v128f, v128f, 2, 0, 1>;
907 defm VFEEZB : BinaryVRRbSPair<"vfeezb", 0xE780, null_frag, null_frag,
908 v128b, v128b, 0, 2, 3>;
909 defm VFEEZH : BinaryVRRbSPair<"vfeezh", 0xE780, null_frag, null_frag,
910 v128h, v128h, 1, 2, 3>;
911 defm VFEEZF : BinaryVRRbSPair<"vfeezf", 0xE780, null_frag, null_frag,
912 v128f, v128f, 2, 2, 3>;
914 defm VFENEB : BinaryVRRbSPair<"vfeneb", 0xE781, null_frag, null_frag,
915 v128b, v128b, 0, 0, 1>;
916 defm VFENEH : BinaryVRRbSPair<"vfeneh", 0xE781, null_frag, null_frag,
917 v128h, v128h, 1, 0, 1>;
918 defm VFENEF : BinaryVRRbSPair<"vfenef", 0xE781, null_frag, null_frag,
919 v128f, v128f, 2, 0, 1>;
920 defm VFENEZB : BinaryVRRbSPair<"vfenezb", 0xE781, null_frag, null_frag,
921 v128b, v128b, 0, 2, 3>;
922 defm VFENEZH : BinaryVRRbSPair<"vfenezh", 0xE781, null_frag, null_frag,
923 v128h, v128h, 1, 2, 3>;
924 defm VFENEZF : BinaryVRRbSPair<"vfenezf", 0xE781, null_frag, null_frag,
925 v128f, v128f, 2, 2, 3>;
927 defm VISTRB : UnaryVRRaSPair<"vistrb", 0xE75C, null_frag, null_frag,
929 defm VISTRH : UnaryVRRaSPair<"vistrh", 0xE75C, null_frag, null_frag,
931 defm VISTRF : UnaryVRRaSPair<"vistrf", 0xE75C, null_frag, null_frag,
934 defm VSTRCB : QuaternaryVRRdSPair<"vstrcb", 0xE78A, null_frag, null_frag,
936 defm VSTRCH : QuaternaryVRRdSPair<"vstrch", 0xE78A, null_frag, null_frag,
938 defm VSTRCF : QuaternaryVRRdSPair<"vstrcf", 0xE78A, null_frag, null_frag,
940 defm VSTRCZB : QuaternaryVRRdSPair<"vstrczb", 0xE78A, null_frag, null_frag,
942 defm VSTRCZH : QuaternaryVRRdSPair<"vstrczh", 0xE78A, null_frag, null_frag,
944 defm VSTRCZF : QuaternaryVRRdSPair<"vstrczf", 0xE78A, null_frag, null_frag,