1 //===-- SystemZOperands.td - SystemZ instruction operands ----*- tblgen-*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class ImmediateAsmOperand<string name>
17 let RenderMethod = "addImmOperands";
20 // Constructs both a DAG pattern and instruction operand for an immediate
21 // of type VT. PRED returns true if a node is acceptable and XFORM returns
22 // the operand value associated with the node. ASMOP is the name of the
23 // associated asm operand, and also forms the basis of the asm print method.
24 class Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop>
25 : PatLeaf<(vt imm), pred, xform>, Operand<vt> {
26 let PrintMethod = "print"##asmop##"Operand";
27 let DecoderMethod = "decode"##asmop##"Operand";
28 let ParserMatchClass = !cast<AsmOperandClass>(asmop);
31 // Constructs an asm operand for a PC-relative address. SIZE says how
32 // many bits there are.
33 class PCRelAsmOperand<string size> : ImmediateAsmOperand<"PCRel"##size> {
34 let PredicateMethod = "isImm";
35 let ParserMethod = "parsePCRel"##size;
38 // Constructs an operand for a PC-relative address with address type VT.
39 // ASMOP is the associated asm operand.
40 class PCRelOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> {
41 let PrintMethod = "printPCRelOperand";
42 let ParserMatchClass = asmop;
45 // Constructs both a DAG pattern and instruction operand for a PC-relative
46 // address with address size VT. SELF is the name of the operand and
47 // ASMOP is the associated asm operand.
48 class PCRelAddress<ValueType vt, string self, AsmOperandClass asmop>
49 : ComplexPattern<vt, 1, "selectPCRelAddress",
50 [z_pcrel_wrapper, z_pcrel_offset]>,
51 PCRelOperand<vt, asmop> {
52 let MIOperandInfo = (ops !cast<Operand>(self));
55 // Constructs an AsmOperandClass for addressing mode FORMAT, treating the
56 // registers as having BITSIZE bits and displacements as having DISPSIZE bits.
57 // LENGTH is "LenN" for addresses with an N-bit length field, otherwise it
59 class AddressAsmOperand<string format, string bitsize, string dispsize,
62 let Name = format##bitsize##"Disp"##dispsize##length;
63 let ParserMethod = "parse"##format##bitsize;
64 let RenderMethod = "add"##format##"Operands";
67 // Constructs both a DAG pattern and instruction operand for an addressing mode.
68 // FORMAT, BITSIZE, DISPSIZE and LENGTH are the parameters to an associated
69 // AddressAsmOperand. OPERANDS is a list of NUMOPS individual operands
70 // (base register, displacement, etc.). SELTYPE is the type of the memory
71 // operand for selection purposes; sometimes we want different selection
72 // choices for the same underlying addressing mode. SUFFIX is similarly
73 // a suffix appended to the displacement for selection purposes;
74 // e.g. we want to reject small 20-bit displacements if a 12-bit form
75 // also exists, but we want to accept them otherwise.
76 class AddressingMode<string seltype, string bitsize, string dispsize,
77 string suffix, string length, int numops, string format,
79 : ComplexPattern<!cast<ValueType>("i"##bitsize), numops,
80 "select"##seltype##dispsize##suffix##length,
81 [add, sub, or, frameindex, z_adjdynalloc]>,
82 Operand<!cast<ValueType>("i"##bitsize)> {
83 let PrintMethod = "print"##format##"Operand";
84 let EncoderMethod = "get"##format##dispsize##length##"Encoding";
86 "decode"##format##bitsize##"Disp"##dispsize##length##"Operand";
87 let MIOperandInfo = operands;
88 let ParserMatchClass =
89 !cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize##length);
92 // An addressing mode with a base and displacement but no index.
93 class BDMode<string type, string bitsize, string dispsize, string suffix>
94 : AddressingMode<type, bitsize, dispsize, suffix, "", 2, "BDAddr",
95 (ops !cast<RegisterOperand>("ADDR"##bitsize),
96 !cast<Immediate>("disp"##dispsize##"imm"##bitsize))>;
98 // An addressing mode with a base, displacement and index.
99 class BDXMode<string type, string bitsize, string dispsize, string suffix>
100 : AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDXAddr",
101 (ops !cast<RegisterOperand>("ADDR"##bitsize),
102 !cast<Immediate>("disp"##dispsize##"imm"##bitsize),
103 !cast<RegisterOperand>("ADDR"##bitsize))>;
105 // A BDMode paired with an immediate length operand of LENSIZE bits.
106 class BDLMode<string type, string bitsize, string dispsize, string suffix,
108 : AddressingMode<type, bitsize, dispsize, suffix, "Len"##lensize, 3,
110 (ops !cast<RegisterOperand>("ADDR"##bitsize),
111 !cast<Immediate>("disp"##dispsize##"imm"##bitsize),
112 !cast<Immediate>("imm"##bitsize))>;
114 //===----------------------------------------------------------------------===//
115 // Extracting immediate operands from nodes
116 // These all create MVT::i64 nodes to ensure the value is not sign-extended
117 // when converted from an SDNode to a MachineOperand later on.
118 //===----------------------------------------------------------------------===//
120 // Bits 0-15 (counting from the lsb).
121 def LL16 : SDNodeXForm<imm, [{
122 uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL;
123 return CurDAG->getTargetConstant(Value, MVT::i64);
126 // Bits 16-31 (counting from the lsb).
127 def LH16 : SDNodeXForm<imm, [{
128 uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16;
129 return CurDAG->getTargetConstant(Value, MVT::i64);
132 // Bits 32-47 (counting from the lsb).
133 def HL16 : SDNodeXForm<imm, [{
134 uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32;
135 return CurDAG->getTargetConstant(Value, MVT::i64);
138 // Bits 48-63 (counting from the lsb).
139 def HH16 : SDNodeXForm<imm, [{
140 uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48;
141 return CurDAG->getTargetConstant(Value, MVT::i64);
145 def LF32 : SDNodeXForm<imm, [{
146 uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL;
147 return CurDAG->getTargetConstant(Value, MVT::i64);
151 def HF32 : SDNodeXForm<imm, [{
152 uint64_t Value = N->getZExtValue() >> 32;
153 return CurDAG->getTargetConstant(Value, MVT::i64);
156 // Truncate an immediate to a 8-bit signed quantity.
157 def SIMM8 : SDNodeXForm<imm, [{
158 return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), MVT::i64);
161 // Truncate an immediate to a 8-bit unsigned quantity.
162 def UIMM8 : SDNodeXForm<imm, [{
163 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), MVT::i64);
166 // Truncate an immediate to a 16-bit signed quantity.
167 def SIMM16 : SDNodeXForm<imm, [{
168 return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), MVT::i64);
171 // Truncate an immediate to a 16-bit unsigned quantity.
172 def UIMM16 : SDNodeXForm<imm, [{
173 return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), MVT::i64);
176 // Truncate an immediate to a 32-bit signed quantity.
177 def SIMM32 : SDNodeXForm<imm, [{
178 return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), MVT::i64);
181 // Truncate an immediate to a 32-bit unsigned quantity.
182 def UIMM32 : SDNodeXForm<imm, [{
183 return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), MVT::i64);
186 // Negate and then truncate an immediate to a 32-bit unsigned quantity.
187 def NEGIMM32 : SDNodeXForm<imm, [{
188 return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), MVT::i64);
191 //===----------------------------------------------------------------------===//
192 // Immediate asm operands.
193 //===----------------------------------------------------------------------===//
195 def U4Imm : ImmediateAsmOperand<"U4Imm">;
196 def U6Imm : ImmediateAsmOperand<"U6Imm">;
197 def S8Imm : ImmediateAsmOperand<"S8Imm">;
198 def U8Imm : ImmediateAsmOperand<"U8Imm">;
199 def S16Imm : ImmediateAsmOperand<"S16Imm">;
200 def U16Imm : ImmediateAsmOperand<"U16Imm">;
201 def S32Imm : ImmediateAsmOperand<"S32Imm">;
202 def U32Imm : ImmediateAsmOperand<"U32Imm">;
204 //===----------------------------------------------------------------------===//
206 //===----------------------------------------------------------------------===//
208 def uimm8zx4 : Immediate<i8, [{
209 return isUInt<4>(N->getZExtValue());
210 }], NOOP_SDNodeXForm, "U4Imm">;
212 def uimm8zx6 : Immediate<i8, [{
213 return isUInt<6>(N->getZExtValue());
214 }], NOOP_SDNodeXForm, "U6Imm">;
216 def simm8 : Immediate<i8, [{}], SIMM8, "S8Imm">;
217 def uimm8 : Immediate<i8, [{}], UIMM8, "U8Imm">;
219 //===----------------------------------------------------------------------===//
221 //===----------------------------------------------------------------------===//
223 // Immediates for the lower and upper 16 bits of an i32, with the other
224 // bits of the i32 being zero.
225 def imm32ll16 : Immediate<i32, [{
226 return SystemZ::isImmLL(N->getZExtValue());
229 def imm32lh16 : Immediate<i32, [{
230 return SystemZ::isImmLH(N->getZExtValue());
233 // Immediates for the lower and upper 16 bits of an i32, with the other
234 // bits of the i32 being one.
235 def imm32ll16c : Immediate<i32, [{
236 return SystemZ::isImmLL(uint32_t(~N->getZExtValue()));
239 def imm32lh16c : Immediate<i32, [{
240 return SystemZ::isImmLH(uint32_t(~N->getZExtValue()));
244 def imm32sx8 : Immediate<i32, [{
245 return isInt<8>(N->getSExtValue());
248 def imm32zx8 : Immediate<i32, [{
249 return isUInt<8>(N->getZExtValue());
252 def imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">;
254 def imm32sx16 : Immediate<i32, [{
255 return isInt<16>(N->getSExtValue());
256 }], SIMM16, "S16Imm">;
258 def imm32zx16 : Immediate<i32, [{
259 return isUInt<16>(N->getZExtValue());
260 }], UIMM16, "U16Imm">;
262 def imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">;
264 // Full 32-bit immediates. we need both signed and unsigned versions
265 // because the assembler is picky. E.g. AFI requires signed operands
266 // while NILF requires unsigned ones.
267 def simm32 : Immediate<i32, [{}], SIMM32, "S32Imm">;
268 def uimm32 : Immediate<i32, [{}], UIMM32, "U32Imm">;
270 def imm32 : ImmLeaf<i32, [{}]>;
272 //===----------------------------------------------------------------------===//
274 //===----------------------------------------------------------------------===//
276 // Immediates for 16-bit chunks of an i64, with the other bits of the
278 def imm64ll16 : Immediate<i64, [{
279 return SystemZ::isImmLL(N->getZExtValue());
282 def imm64lh16 : Immediate<i64, [{
283 return SystemZ::isImmLH(N->getZExtValue());
286 def imm64hl16 : Immediate<i64, [{
287 return SystemZ::isImmHL(N->getZExtValue());
290 def imm64hh16 : Immediate<i64, [{
291 return SystemZ::isImmHH(N->getZExtValue());
294 // Immediates for 16-bit chunks of an i64, with the other bits of the
296 def imm64ll16c : Immediate<i64, [{
297 return SystemZ::isImmLL(uint64_t(~N->getZExtValue()));
300 def imm64lh16c : Immediate<i64, [{
301 return SystemZ::isImmLH(uint64_t(~N->getZExtValue()));
304 def imm64hl16c : Immediate<i64, [{
305 return SystemZ::isImmHL(uint64_t(~N->getZExtValue()));
308 def imm64hh16c : Immediate<i64, [{
309 return SystemZ::isImmHH(uint64_t(~N->getZExtValue()));
312 // Immediates for the lower and upper 32 bits of an i64, with the other
313 // bits of the i32 being zero.
314 def imm64lf32 : Immediate<i64, [{
315 return SystemZ::isImmLF(N->getZExtValue());
318 def imm64hf32 : Immediate<i64, [{
319 return SystemZ::isImmHF(N->getZExtValue());
322 // Immediates for the lower and upper 32 bits of an i64, with the other
323 // bits of the i32 being one.
324 def imm64lf32c : Immediate<i64, [{
325 return SystemZ::isImmLF(uint64_t(~N->getZExtValue()));
328 def imm64hf32c : Immediate<i64, [{
329 return SystemZ::isImmHF(uint64_t(~N->getZExtValue()));
333 def imm64sx8 : Immediate<i64, [{
334 return isInt<8>(N->getSExtValue());
337 def imm64zx8 : Immediate<i64, [{
338 return isUInt<8>(N->getSExtValue());
341 def imm64sx16 : Immediate<i64, [{
342 return isInt<16>(N->getSExtValue());
343 }], SIMM16, "S16Imm">;
345 def imm64zx16 : Immediate<i64, [{
346 return isUInt<16>(N->getZExtValue());
347 }], UIMM16, "U16Imm">;
349 def imm64sx32 : Immediate<i64, [{
350 return isInt<32>(N->getSExtValue());
351 }], SIMM32, "S32Imm">;
353 def imm64zx32 : Immediate<i64, [{
354 return isUInt<32>(N->getZExtValue());
355 }], UIMM32, "U32Imm">;
357 def imm64zx32n : Immediate<i64, [{
358 return isUInt<32>(-N->getSExtValue());
359 }], NEGIMM32, "U32Imm">;
361 def imm64 : ImmLeaf<i64, [{}]>, Operand<i64>;
363 //===----------------------------------------------------------------------===//
364 // Floating-point immediates
365 //===----------------------------------------------------------------------===//
367 // Floating-point zero.
368 def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
370 // Floating point negative zero.
371 def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>;
373 //===----------------------------------------------------------------------===//
374 // Symbolic address operands
375 //===----------------------------------------------------------------------===//
377 // PC-relative asm operands.
378 def PCRel16 : PCRelAsmOperand<"16">;
379 def PCRel32 : PCRelAsmOperand<"32">;
381 // PC-relative offsets of a basic block. The offset is sign-extended
382 // and multiplied by 2.
383 def brtarget16 : PCRelOperand<OtherVT, PCRel16> {
384 let EncoderMethod = "getPC16DBLEncoding";
385 let DecoderMethod = "decodePC16DBLOperand";
387 def brtarget32 : PCRelOperand<OtherVT, PCRel32> {
388 let EncoderMethod = "getPC32DBLEncoding";
389 let DecoderMethod = "decodePC32DBLOperand";
392 // A PC-relative offset of a global value. The offset is sign-extended
393 // and multiplied by 2.
394 def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> {
395 let EncoderMethod = "getPC32DBLEncoding";
396 let DecoderMethod = "decodePC32DBLOperand";
399 //===----------------------------------------------------------------------===//
401 //===----------------------------------------------------------------------===//
403 // 12-bit displacement operands.
404 def disp12imm32 : Operand<i32>;
405 def disp12imm64 : Operand<i64>;
407 // 20-bit displacement operands.
408 def disp20imm32 : Operand<i32>;
409 def disp20imm64 : Operand<i64>;
411 def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">;
412 def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">;
413 def BDAddr64Disp12 : AddressAsmOperand<"BDAddr", "64", "12">;
414 def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">;
415 def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">;
416 def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">;
417 def BDLAddr64Disp12Len8 : AddressAsmOperand<"BDLAddr", "64", "12", "Len8">;
419 // DAG patterns and operands for addressing modes. Each mode has
420 // the form <type><range><group>[<len>] where:
423 // shift : base + displacement (32-bit)
424 // bdaddr : base + displacement
425 // mviaddr : like bdaddr, but reject cases with a natural index
426 // bdxaddr : base + displacement + index
427 // laaddr : like bdxaddr, but used for Load Address operations
428 // dynalloc : base + displacement + index + ADJDYNALLOC
429 // bdladdr : base + displacement with a length field
431 // <range> is one of:
432 // 12 : the displacement is an unsigned 12-bit value
433 // 20 : the displacement is a signed 20-bit value
435 // <group> is one of:
436 // pair : used when there is an equivalent instruction with the opposite
437 // range value (12 or 20)
438 // only : used when there is no equivalent instruction with the opposite
443 // <empty> : there is no length field
444 // len8 : the length field is 8 bits, with a range of [1, 0x100].
445 def shift12only : BDMode <"BDAddr", "32", "12", "Only">;
446 def shift20only : BDMode <"BDAddr", "32", "20", "Only">;
447 def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">;
448 def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">;
449 def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">;
450 def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">;
451 def mviaddr12pair : BDMode <"MVIAddr", "64", "12", "Pair">;
452 def mviaddr20pair : BDMode <"MVIAddr", "64", "20", "Pair">;
453 def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">;
454 def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">;
455 def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">;
456 def bdxaddr20only128 : BDXMode<"BDXAddr", "64", "20", "Only128">;
457 def bdxaddr20pair : BDXMode<"BDXAddr", "64", "20", "Pair">;
458 def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">;
459 def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">;
460 def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">;
461 def bdladdr12onlylen8 : BDLMode<"BDLAddr", "64", "12", "Only", "8">;
463 //===----------------------------------------------------------------------===//
465 //===----------------------------------------------------------------------===//
467 // Access registers. At present we just use them for accessing the thread
468 // pointer, so we don't expose them as register to LLVM.
469 def AccessReg : AsmOperandClass {
470 let Name = "AccessReg";
471 let ParserMethod = "parseAccessReg";
473 def access_reg : Immediate<i8, [{ return N->getZExtValue() < 16; }],
474 NOOP_SDNodeXForm, "AccessReg"> {
475 let ParserMatchClass = AccessReg;
478 // A 4-bit condition-code mask.
479 def cond4 : PatLeaf<(i8 imm), [{ return (N->getZExtValue() < 16); }]>,
481 let PrintMethod = "printCond4Operand";