1 //===-- SystemZOperands.td - SystemZ instruction operands ----*- tblgen-*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class ImmediateAsmOperand<string name>
17 let RenderMethod = "addImmOperands";
20 // Constructs both a DAG pattern and instruction operand for an immediate
21 // of type VT. PRED returns true if a node is acceptable and XFORM returns
22 // the operand value associated with the node. ASMOP is the name of the
23 // associated asm operand, and also forms the basis of the asm print method.
24 class Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop>
25 : PatLeaf<(vt imm), pred, xform>, Operand<vt> {
26 let PrintMethod = "print"##asmop##"Operand";
27 let DecoderMethod = "decode"##asmop##"Operand";
28 let ParserMatchClass = !cast<AsmOperandClass>(asmop);
31 // Constructs an asm operand for a PC-relative address. SIZE says how
32 // many bits there are.
33 class PCRelAsmOperand<string size> : ImmediateAsmOperand<"PCRel"##size> {
34 let PredicateMethod = "isImm";
35 let ParserMethod = "parsePCRel"##size;
38 // Constructs an operand for a PC-relative address with address type VT.
39 // ASMOP is the associated asm operand.
40 class PCRelOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> {
41 let PrintMethod = "printPCRelOperand";
42 let ParserMatchClass = asmop;
45 // Constructs both a DAG pattern and instruction operand for a PC-relative
46 // address with address size VT. SELF is the name of the operand and
47 // ASMOP is the associated asm operand.
48 class PCRelAddress<ValueType vt, string self, AsmOperandClass asmop>
49 : ComplexPattern<vt, 1, "selectPCRelAddress", [z_pcrel_wrapper]>,
50 PCRelOperand<vt, asmop> {
51 let MIOperandInfo = (ops !cast<Operand>(self));
54 // Constructs an AsmOperandClass for addressing mode FORMAT, treating the
55 // registers as having BITSIZE bits and displacements as having DISPSIZE bits.
56 // LENGTH is "LenN" for addresses with an N-bit length field, otherwise it
58 class AddressAsmOperand<string format, string bitsize, string dispsize,
61 let Name = format##bitsize##"Disp"##dispsize##length;
62 let ParserMethod = "parse"##format##bitsize;
63 let RenderMethod = "add"##format##"Operands";
66 // Constructs both a DAG pattern and instruction operand for an addressing mode.
67 // FORMAT, BITSIZE, DISPSIZE and LENGTH are the parameters to an associated
68 // AddressAsmOperand. OPERANDS is a list of NUMOPS individual operands
69 // (base register, displacement, etc.). SELTYPE is the type of the memory
70 // operand for selection purposes; sometimes we want different selection
71 // choices for the same underlying addressing mode. SUFFIX is similarly
72 // a suffix appended to the displacement for selection purposes;
73 // e.g. we want to reject small 20-bit displacements if a 12-bit form
74 // also exists, but we want to accept them otherwise.
75 class AddressingMode<string seltype, string bitsize, string dispsize,
76 string suffix, string length, int numops, string format,
78 : ComplexPattern<!cast<ValueType>("i"##bitsize), numops,
79 "select"##seltype##dispsize##suffix##length,
80 [add, sub, or, frameindex, z_adjdynalloc]>,
81 Operand<!cast<ValueType>("i"##bitsize)> {
82 let PrintMethod = "print"##format##"Operand";
83 let EncoderMethod = "get"##format##dispsize##length##"Encoding";
85 "decode"##format##bitsize##"Disp"##dispsize##length##"Operand";
86 let MIOperandInfo = operands;
87 let ParserMatchClass =
88 !cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize##length);
91 // An addressing mode with a base and displacement but no index.
92 class BDMode<string type, string bitsize, string dispsize, string suffix>
93 : AddressingMode<type, bitsize, dispsize, suffix, "", 2, "BDAddr",
94 (ops !cast<RegisterOperand>("ADDR"##bitsize),
95 !cast<Immediate>("disp"##dispsize##"imm"##bitsize))>;
97 // An addressing mode with a base, displacement and index.
98 class BDXMode<string type, string bitsize, string dispsize, string suffix>
99 : AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDXAddr",
100 (ops !cast<RegisterOperand>("ADDR"##bitsize),
101 !cast<Immediate>("disp"##dispsize##"imm"##bitsize),
102 !cast<RegisterOperand>("ADDR"##bitsize))>;
104 // A BDMode paired with an immediate length operand of LENSIZE bits.
105 class BDLMode<string type, string bitsize, string dispsize, string suffix,
107 : AddressingMode<type, bitsize, dispsize, suffix, "Len"##lensize, 3,
109 (ops !cast<RegisterOperand>("ADDR"##bitsize),
110 !cast<Immediate>("disp"##dispsize##"imm"##bitsize),
111 !cast<Immediate>("imm"##bitsize))>;
113 //===----------------------------------------------------------------------===//
114 // Extracting immediate operands from nodes
115 // These all create MVT::i64 nodes to ensure the value is not sign-extended
116 // when converted from an SDNode to a MachineOperand later on.
117 //===----------------------------------------------------------------------===//
119 // Bits 0-15 (counting from the lsb).
120 def LL16 : SDNodeXForm<imm, [{
121 uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL;
122 return CurDAG->getTargetConstant(Value, MVT::i64);
125 // Bits 16-31 (counting from the lsb).
126 def LH16 : SDNodeXForm<imm, [{
127 uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16;
128 return CurDAG->getTargetConstant(Value, MVT::i64);
131 // Bits 32-47 (counting from the lsb).
132 def HL16 : SDNodeXForm<imm, [{
133 uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32;
134 return CurDAG->getTargetConstant(Value, MVT::i64);
137 // Bits 48-63 (counting from the lsb).
138 def HH16 : SDNodeXForm<imm, [{
139 uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48;
140 return CurDAG->getTargetConstant(Value, MVT::i64);
144 def LF32 : SDNodeXForm<imm, [{
145 uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL;
146 return CurDAG->getTargetConstant(Value, MVT::i64);
150 def HF32 : SDNodeXForm<imm, [{
151 uint64_t Value = N->getZExtValue() >> 32;
152 return CurDAG->getTargetConstant(Value, MVT::i64);
155 // Truncate an immediate to a 8-bit signed quantity.
156 def SIMM8 : SDNodeXForm<imm, [{
157 return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), MVT::i64);
160 // Truncate an immediate to a 8-bit unsigned quantity.
161 def UIMM8 : SDNodeXForm<imm, [{
162 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), MVT::i64);
165 // Truncate an immediate to a 16-bit signed quantity.
166 def SIMM16 : SDNodeXForm<imm, [{
167 return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), MVT::i64);
170 // Truncate an immediate to a 16-bit unsigned quantity.
171 def UIMM16 : SDNodeXForm<imm, [{
172 return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), MVT::i64);
175 // Truncate an immediate to a 32-bit signed quantity.
176 def SIMM32 : SDNodeXForm<imm, [{
177 return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), MVT::i64);
180 // Truncate an immediate to a 32-bit unsigned quantity.
181 def UIMM32 : SDNodeXForm<imm, [{
182 return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), MVT::i64);
185 // Negate and then truncate an immediate to a 32-bit unsigned quantity.
186 def NEGIMM32 : SDNodeXForm<imm, [{
187 return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), MVT::i64);
190 //===----------------------------------------------------------------------===//
191 // Immediate asm operands.
192 //===----------------------------------------------------------------------===//
194 def U4Imm : ImmediateAsmOperand<"U4Imm">;
195 def U6Imm : ImmediateAsmOperand<"U6Imm">;
196 def S8Imm : ImmediateAsmOperand<"S8Imm">;
197 def U8Imm : ImmediateAsmOperand<"U8Imm">;
198 def S16Imm : ImmediateAsmOperand<"S16Imm">;
199 def U16Imm : ImmediateAsmOperand<"U16Imm">;
200 def S32Imm : ImmediateAsmOperand<"S32Imm">;
201 def U32Imm : ImmediateAsmOperand<"U32Imm">;
203 //===----------------------------------------------------------------------===//
205 //===----------------------------------------------------------------------===//
207 def uimm8zx4 : Immediate<i8, [{
208 return isUInt<4>(N->getZExtValue());
209 }], NOOP_SDNodeXForm, "U4Imm">;
211 def uimm8zx6 : Immediate<i8, [{
212 return isUInt<6>(N->getZExtValue());
213 }], NOOP_SDNodeXForm, "U6Imm">;
215 def simm8 : Immediate<i8, [{}], SIMM8, "S8Imm">;
216 def uimm8 : Immediate<i8, [{}], UIMM8, "U8Imm">;
218 //===----------------------------------------------------------------------===//
220 //===----------------------------------------------------------------------===//
222 // Immediates for the lower and upper 16 bits of an i32, with the other
223 // bits of the i32 being zero.
224 def imm32ll16 : Immediate<i32, [{
225 return SystemZ::isImmLL(N->getZExtValue());
228 def imm32lh16 : Immediate<i32, [{
229 return SystemZ::isImmLH(N->getZExtValue());
232 // Immediates for the lower and upper 16 bits of an i32, with the other
233 // bits of the i32 being one.
234 def imm32ll16c : Immediate<i32, [{
235 return SystemZ::isImmLL(uint32_t(~N->getZExtValue()));
238 def imm32lh16c : Immediate<i32, [{
239 return SystemZ::isImmLH(uint32_t(~N->getZExtValue()));
243 def imm32sx8 : Immediate<i32, [{
244 return isInt<8>(N->getSExtValue());
247 def imm32zx8 : Immediate<i32, [{
248 return isUInt<8>(N->getZExtValue());
251 def imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">;
253 def imm32sx16 : Immediate<i32, [{
254 return isInt<16>(N->getSExtValue());
255 }], SIMM16, "S16Imm">;
257 def imm32zx16 : Immediate<i32, [{
258 return isUInt<16>(N->getZExtValue());
259 }], UIMM16, "U16Imm">;
261 def imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">;
263 // Full 32-bit immediates. we need both signed and unsigned versions
264 // because the assembler is picky. E.g. AFI requires signed operands
265 // while NILF requires unsigned ones.
266 def simm32 : Immediate<i32, [{}], SIMM32, "S32Imm">;
267 def uimm32 : Immediate<i32, [{}], UIMM32, "U32Imm">;
269 def imm32 : ImmLeaf<i32, [{}]>;
271 //===----------------------------------------------------------------------===//
273 //===----------------------------------------------------------------------===//
275 // Immediates for 16-bit chunks of an i64, with the other bits of the
277 def imm64ll16 : Immediate<i64, [{
278 return SystemZ::isImmLL(N->getZExtValue());
281 def imm64lh16 : Immediate<i64, [{
282 return SystemZ::isImmLH(N->getZExtValue());
285 def imm64hl16 : Immediate<i64, [{
286 return SystemZ::isImmHL(N->getZExtValue());
289 def imm64hh16 : Immediate<i64, [{
290 return SystemZ::isImmHH(N->getZExtValue());
293 // Immediates for 16-bit chunks of an i64, with the other bits of the
295 def imm64ll16c : Immediate<i64, [{
296 return SystemZ::isImmLL(uint64_t(~N->getZExtValue()));
299 def imm64lh16c : Immediate<i64, [{
300 return SystemZ::isImmLH(uint64_t(~N->getZExtValue()));
303 def imm64hl16c : Immediate<i64, [{
304 return SystemZ::isImmHL(uint64_t(~N->getZExtValue()));
307 def imm64hh16c : Immediate<i64, [{
308 return SystemZ::isImmHH(uint64_t(~N->getZExtValue()));
311 // Immediates for the lower and upper 32 bits of an i64, with the other
312 // bits of the i32 being zero.
313 def imm64lf32 : Immediate<i64, [{
314 return SystemZ::isImmLF(N->getZExtValue());
317 def imm64hf32 : Immediate<i64, [{
318 return SystemZ::isImmHF(N->getZExtValue());
321 // Immediates for the lower and upper 32 bits of an i64, with the other
322 // bits of the i32 being one.
323 def imm64lf32c : Immediate<i64, [{
324 return SystemZ::isImmLF(uint64_t(~N->getZExtValue()));
327 def imm64hf32c : Immediate<i64, [{
328 return SystemZ::isImmHF(uint64_t(~N->getZExtValue()));
332 def imm64sx8 : Immediate<i64, [{
333 return isInt<8>(N->getSExtValue());
336 def imm64sx16 : Immediate<i64, [{
337 return isInt<16>(N->getSExtValue());
338 }], SIMM16, "S16Imm">;
340 def imm64zx16 : Immediate<i64, [{
341 return isUInt<16>(N->getZExtValue());
342 }], UIMM16, "U16Imm">;
344 def imm64sx32 : Immediate<i64, [{
345 return isInt<32>(N->getSExtValue());
346 }], SIMM32, "S32Imm">;
348 def imm64zx32 : Immediate<i64, [{
349 return isUInt<32>(N->getZExtValue());
350 }], UIMM32, "U32Imm">;
352 def imm64zx32n : Immediate<i64, [{
353 return isUInt<32>(-N->getSExtValue());
354 }], NEGIMM32, "U32Imm">;
356 def imm64 : ImmLeaf<i64, [{}]>;
358 //===----------------------------------------------------------------------===//
359 // Floating-point immediates
360 //===----------------------------------------------------------------------===//
362 // Floating-point zero.
363 def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
365 // Floating point negative zero.
366 def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>;
368 //===----------------------------------------------------------------------===//
369 // Symbolic address operands
370 //===----------------------------------------------------------------------===//
372 // PC-relative asm operands.
373 def PCRel16 : PCRelAsmOperand<"16">;
374 def PCRel32 : PCRelAsmOperand<"32">;
376 // PC-relative offsets of a basic block. The offset is sign-extended
377 // and multiplied by 2.
378 def brtarget16 : PCRelOperand<OtherVT, PCRel16> {
379 let EncoderMethod = "getPC16DBLEncoding";
380 let DecoderMethod = "decodePC16DBLOperand";
382 def brtarget32 : PCRelOperand<OtherVT, PCRel32> {
383 let EncoderMethod = "getPC32DBLEncoding";
384 let DecoderMethod = "decodePC32DBLOperand";
387 // A PC-relative offset of a global value. The offset is sign-extended
388 // and multiplied by 2.
389 def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> {
390 let EncoderMethod = "getPC32DBLEncoding";
391 let DecoderMethod = "decodePC32DBLOperand";
394 // A PC-relative offset of a global value when the value is used as a
395 // call target. The offset is sign-extended and multiplied by 2.
396 def pcrel16call : PCRelAddress<i64, "pcrel16call", PCRel16> {
397 let PrintMethod = "printCallOperand";
398 let EncoderMethod = "getPLT16DBLEncoding";
399 let DecoderMethod = "decodePC16DBLOperand";
401 def pcrel32call : PCRelAddress<i64, "pcrel32call", PCRel32> {
402 let PrintMethod = "printCallOperand";
403 let EncoderMethod = "getPLT32DBLEncoding";
404 let DecoderMethod = "decodePC32DBLOperand";
407 //===----------------------------------------------------------------------===//
409 //===----------------------------------------------------------------------===//
411 // 12-bit displacement operands.
412 def disp12imm32 : Operand<i32>;
413 def disp12imm64 : Operand<i64>;
415 // 20-bit displacement operands.
416 def disp20imm32 : Operand<i32>;
417 def disp20imm64 : Operand<i64>;
419 def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">;
420 def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">;
421 def BDAddr64Disp12 : AddressAsmOperand<"BDAddr", "64", "12">;
422 def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">;
423 def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">;
424 def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">;
425 def BDLAddr64Disp12Len8 : AddressAsmOperand<"BDLAddr", "64", "12", "Len8">;
427 // DAG patterns and operands for addressing modes. Each mode has
428 // the form <type><range><group>[<len>] where:
431 // shift : base + displacement (32-bit)
432 // bdaddr : base + displacement
433 // bdxaddr : base + displacement + index
434 // laaddr : like bdxaddr, but used for Load Address operations
435 // dynalloc : base + displacement + index + ADJDYNALLOC
436 // bdladdr : base + displacement with a length field
438 // <range> is one of:
439 // 12 : the displacement is an unsigned 12-bit value
440 // 20 : the displacement is a signed 20-bit value
442 // <group> is one of:
443 // pair : used when there is an equivalent instruction with the opposite
444 // range value (12 or 20)
445 // only : used when there is no equivalent instruction with the opposite
450 // <empty> : there is no length field
451 // len8 : the length field is 8 bits, with a range of [1, 0x100].
452 def shift12only : BDMode <"BDAddr", "32", "12", "Only">;
453 def shift20only : BDMode <"BDAddr", "32", "20", "Only">;
454 def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">;
455 def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">;
456 def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">;
457 def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">;
458 def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">;
459 def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">;
460 def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">;
461 def bdxaddr20only128 : BDXMode<"BDXAddr", "64", "20", "Only128">;
462 def bdxaddr20pair : BDXMode<"BDXAddr", "64", "20", "Pair">;
463 def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">;
464 def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">;
465 def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">;
466 def bdladdr12onlylen8 : BDLMode<"BDLAddr", "64", "12", "Only", "8">;
468 //===----------------------------------------------------------------------===//
470 //===----------------------------------------------------------------------===//
472 // Access registers. At present we just use them for accessing the thread
473 // pointer, so we don't expose them as register to LLVM.
474 def AccessReg : AsmOperandClass {
475 let Name = "AccessReg";
476 let ParserMethod = "parseAccessReg";
478 def access_reg : Immediate<i8, [{ return N->getZExtValue() < 16; }],
479 NOOP_SDNodeXForm, "AccessReg"> {
480 let ParserMatchClass = AccessReg;
483 // A 4-bit condition-code mask.
484 def cond4 : PatLeaf<(i8 imm), [{ return (N->getZExtValue() < 16); }]>,
486 let PrintMethod = "printCond4Operand";