1 //===-- SystemZOperands.td - SystemZ instruction operands ----*- tblgen-*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class ImmediateAsmOperand<string name>
17 let RenderMethod = "addImmOperands";
20 // Constructs both a DAG pattern and instruction operand for an immediate
21 // of type VT. PRED returns true if a node is acceptable and XFORM returns
22 // the operand value associated with the node. ASMOP is the name of the
23 // associated asm operand, and also forms the basis of the asm print method.
24 class Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop>
25 : PatLeaf<(vt imm), pred, xform>, Operand<vt> {
26 let PrintMethod = "print"##asmop##"Operand";
27 let DecoderMethod = "decode"##asmop##"Operand";
28 let ParserMatchClass = !cast<AsmOperandClass>(asmop);
31 // Constructs an asm operand for a PC-relative address. SIZE says how
32 // many bits there are.
33 class PCRelAsmOperand<string size> : ImmediateAsmOperand<"PCRel"##size> {
34 let PredicateMethod = "isImm";
35 let ParserMethod = "parsePCRel"##size;
38 // Constructs an operand for a PC-relative address with address type VT.
39 // ASMOP is the associated asm operand.
40 class PCRelOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> {
41 let PrintMethod = "printPCRelOperand";
42 let ParserMatchClass = asmop;
45 // Constructs both a DAG pattern and instruction operand for a PC-relative
46 // address with address size VT. SELF is the name of the operand and
47 // ASMOP is the associated asm operand.
48 class PCRelAddress<ValueType vt, string self, AsmOperandClass asmop>
49 : ComplexPattern<vt, 1, "selectPCRelAddress", [z_pcrel_wrapper]>,
50 PCRelOperand<vt, asmop> {
51 let MIOperandInfo = (ops !cast<Operand>(self));
54 // Constructs an AsmOperandClass for addressing mode FORMAT, treating the
55 // registers as having BITSIZE bits and displacements as having DISPSIZE bits.
56 class AddressAsmOperand<string format, string bitsize, string dispsize>
58 let Name = format##bitsize##"Disp"##dispsize;
59 let ParserMethod = "parse"##format##bitsize;
60 let RenderMethod = "add"##format##"Operands";
63 // Constructs both a DAG pattern and instruction operand for an addressing mode.
64 // The mode is selected by custom code in select<TYPE><DISPSIZE><SUFFIX>(),
65 // encoded by custom code in get<FORMAT><DISPSIZE>Encoding() and decoded
66 // by custom code in decode<TYPE><BITSIZE>Disp<DISPSIZE>Operand().
67 // The address registers have BITSIZE bits and displacements have
68 // DISPSIZE bits. NUMOPS is the number of operands that make up an
69 // address and OPERANDS lists the types of those operands using (ops ...).
70 // FORMAT is the type of addressing mode, which needs to match the names
71 // used in AddressAsmOperand.
72 class AddressingMode<string type, string bitsize, string dispsize,
73 string suffix, int numops, string format, dag operands>
74 : ComplexPattern<!cast<ValueType>("i"##bitsize), numops,
75 "select"##type##dispsize##suffix,
76 [add, sub, or, frameindex, z_adjdynalloc]>,
77 Operand<!cast<ValueType>("i"##bitsize)> {
78 let PrintMethod = "print"##format##"Operand";
79 let EncoderMethod = "get"##format##dispsize##"Encoding";
80 let DecoderMethod = "decode"##format##bitsize##"Disp"##dispsize##"Operand";
81 let MIOperandInfo = operands;
82 let ParserMatchClass =
83 !cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize);
86 // An addressing mode with a base and displacement but no index.
87 class BDMode<string type, string bitsize, string dispsize, string suffix>
88 : AddressingMode<type, bitsize, dispsize, suffix, 2, "BDAddr",
89 (ops !cast<RegisterOperand>("ADDR"##bitsize),
90 !cast<Immediate>("disp"##dispsize##"imm"##bitsize))>;
92 // An addressing mode with a base, displacement and index.
93 class BDXMode<string type, string bitsize, string dispsize, string suffix>
94 : AddressingMode<type, bitsize, dispsize, suffix, 3, "BDXAddr",
95 (ops !cast<RegisterOperand>("ADDR"##bitsize),
96 !cast<Immediate>("disp"##dispsize##"imm"##bitsize),
97 !cast<RegisterOperand>("ADDR"##bitsize))>;
99 //===----------------------------------------------------------------------===//
100 // Extracting immediate operands from nodes
101 // These all create MVT::i64 nodes to ensure the value is not sign-extended
102 // when converted from an SDNode to a MachineOperand later on.
103 //===----------------------------------------------------------------------===//
105 // Bits 0-15 (counting from the lsb).
106 def LL16 : SDNodeXForm<imm, [{
107 uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL;
108 return CurDAG->getTargetConstant(Value, MVT::i64);
111 // Bits 16-31 (counting from the lsb).
112 def LH16 : SDNodeXForm<imm, [{
113 uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16;
114 return CurDAG->getTargetConstant(Value, MVT::i64);
117 // Bits 32-47 (counting from the lsb).
118 def HL16 : SDNodeXForm<imm, [{
119 uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32;
120 return CurDAG->getTargetConstant(Value, MVT::i64);
123 // Bits 48-63 (counting from the lsb).
124 def HH16 : SDNodeXForm<imm, [{
125 uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48;
126 return CurDAG->getTargetConstant(Value, MVT::i64);
130 def LF32 : SDNodeXForm<imm, [{
131 uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL;
132 return CurDAG->getTargetConstant(Value, MVT::i64);
136 def HF32 : SDNodeXForm<imm, [{
137 uint64_t Value = N->getZExtValue() >> 32;
138 return CurDAG->getTargetConstant(Value, MVT::i64);
141 // Truncate an immediate to a 8-bit signed quantity.
142 def SIMM8 : SDNodeXForm<imm, [{
143 return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), MVT::i64);
146 // Truncate an immediate to a 8-bit unsigned quantity.
147 def UIMM8 : SDNodeXForm<imm, [{
148 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), MVT::i64);
151 // Truncate an immediate to a 16-bit signed quantity.
152 def SIMM16 : SDNodeXForm<imm, [{
153 return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), MVT::i64);
156 // Truncate an immediate to a 16-bit unsigned quantity.
157 def UIMM16 : SDNodeXForm<imm, [{
158 return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), MVT::i64);
161 // Truncate an immediate to a 32-bit signed quantity.
162 def SIMM32 : SDNodeXForm<imm, [{
163 return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), MVT::i64);
166 // Truncate an immediate to a 32-bit unsigned quantity.
167 def UIMM32 : SDNodeXForm<imm, [{
168 return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), MVT::i64);
171 // Negate and then truncate an immediate to a 32-bit unsigned quantity.
172 def NEGIMM32 : SDNodeXForm<imm, [{
173 return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), MVT::i64);
176 //===----------------------------------------------------------------------===//
177 // Immediate asm operands.
178 //===----------------------------------------------------------------------===//
180 def U4Imm : ImmediateAsmOperand<"U4Imm">;
181 def U6Imm : ImmediateAsmOperand<"U6Imm">;
182 def S8Imm : ImmediateAsmOperand<"S8Imm">;
183 def U8Imm : ImmediateAsmOperand<"U8Imm">;
184 def S16Imm : ImmediateAsmOperand<"S16Imm">;
185 def U16Imm : ImmediateAsmOperand<"U16Imm">;
186 def S32Imm : ImmediateAsmOperand<"S32Imm">;
187 def U32Imm : ImmediateAsmOperand<"U32Imm">;
189 //===----------------------------------------------------------------------===//
191 //===----------------------------------------------------------------------===//
193 def uimm8zx4 : Immediate<i8, [{
194 return isUInt<4>(N->getZExtValue());
195 }], NOOP_SDNodeXForm, "U4Imm">;
197 def uimm8zx6 : Immediate<i8, [{
198 return isUInt<6>(N->getZExtValue());
199 }], NOOP_SDNodeXForm, "U6Imm">;
201 def simm8 : Immediate<i8, [{}], SIMM8, "S8Imm">;
202 def uimm8 : Immediate<i8, [{}], UIMM8, "U8Imm">;
204 //===----------------------------------------------------------------------===//
206 //===----------------------------------------------------------------------===//
208 // Immediates for the lower and upper 16 bits of an i32, with the other
209 // bits of the i32 being zero.
210 def imm32ll16 : Immediate<i32, [{
211 return SystemZ::isImmLL(N->getZExtValue());
214 def imm32lh16 : Immediate<i32, [{
215 return SystemZ::isImmLH(N->getZExtValue());
218 // Immediates for the lower and upper 16 bits of an i32, with the other
219 // bits of the i32 being one.
220 def imm32ll16c : Immediate<i32, [{
221 return SystemZ::isImmLL(uint32_t(~N->getZExtValue()));
224 def imm32lh16c : Immediate<i32, [{
225 return SystemZ::isImmLH(uint32_t(~N->getZExtValue()));
229 def imm32sx8 : Immediate<i32, [{
230 return isInt<8>(N->getSExtValue());
233 def imm32zx8 : Immediate<i32, [{
234 return isUInt<8>(N->getZExtValue());
237 def imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">;
239 def imm32sx16 : Immediate<i32, [{
240 return isInt<16>(N->getSExtValue());
241 }], SIMM16, "S16Imm">;
243 def imm32zx16 : Immediate<i32, [{
244 return isUInt<16>(N->getZExtValue());
245 }], UIMM16, "U16Imm">;
247 def imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">;
249 // Full 32-bit immediates. we need both signed and unsigned versions
250 // because the assembler is picky. E.g. AFI requires signed operands
251 // while NILF requires unsigned ones.
252 def simm32 : Immediate<i32, [{}], SIMM32, "S32Imm">;
253 def uimm32 : Immediate<i32, [{}], UIMM32, "U32Imm">;
255 def imm32 : ImmLeaf<i32, [{}]>;
257 //===----------------------------------------------------------------------===//
259 //===----------------------------------------------------------------------===//
261 // Immediates for 16-bit chunks of an i64, with the other bits of the
263 def imm64ll16 : Immediate<i64, [{
264 return SystemZ::isImmLL(N->getZExtValue());
267 def imm64lh16 : Immediate<i64, [{
268 return SystemZ::isImmLH(N->getZExtValue());
271 def imm64hl16 : Immediate<i64, [{
272 return SystemZ::isImmHL(N->getZExtValue());
275 def imm64hh16 : Immediate<i64, [{
276 return SystemZ::isImmHH(N->getZExtValue());
279 // Immediates for 16-bit chunks of an i64, with the other bits of the
281 def imm64ll16c : Immediate<i64, [{
282 return SystemZ::isImmLL(uint64_t(~N->getZExtValue()));
285 def imm64lh16c : Immediate<i64, [{
286 return SystemZ::isImmLH(uint64_t(~N->getZExtValue()));
289 def imm64hl16c : Immediate<i64, [{
290 return SystemZ::isImmHL(uint64_t(~N->getZExtValue()));
293 def imm64hh16c : Immediate<i64, [{
294 return SystemZ::isImmHH(uint64_t(~N->getZExtValue()));
297 // Immediates for the lower and upper 32 bits of an i64, with the other
298 // bits of the i32 being zero.
299 def imm64lf32 : Immediate<i64, [{
300 return SystemZ::isImmLF(N->getZExtValue());
303 def imm64hf32 : Immediate<i64, [{
304 return SystemZ::isImmHF(N->getZExtValue());
307 // Immediates for the lower and upper 32 bits of an i64, with the other
308 // bits of the i32 being one.
309 def imm64lf32c : Immediate<i64, [{
310 return SystemZ::isImmLF(uint64_t(~N->getZExtValue()));
313 def imm64hf32c : Immediate<i64, [{
314 return SystemZ::isImmHF(uint64_t(~N->getZExtValue()));
318 def imm64sx8 : Immediate<i64, [{
319 return isInt<8>(N->getSExtValue());
322 def imm64sx16 : Immediate<i64, [{
323 return isInt<16>(N->getSExtValue());
324 }], SIMM16, "S16Imm">;
326 def imm64zx16 : Immediate<i64, [{
327 return isUInt<16>(N->getZExtValue());
328 }], UIMM16, "U16Imm">;
330 def imm64sx32 : Immediate<i64, [{
331 return isInt<32>(N->getSExtValue());
332 }], SIMM32, "S32Imm">;
334 def imm64zx32 : Immediate<i64, [{
335 return isUInt<32>(N->getZExtValue());
336 }], UIMM32, "U32Imm">;
338 def imm64zx32n : Immediate<i64, [{
339 return isUInt<32>(-N->getSExtValue());
340 }], NEGIMM32, "U32Imm">;
342 def imm64 : ImmLeaf<i64, [{}]>;
344 //===----------------------------------------------------------------------===//
345 // Floating-point immediates
346 //===----------------------------------------------------------------------===//
348 // Floating-point zero.
349 def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
351 // Floating point negative zero.
352 def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>;
354 //===----------------------------------------------------------------------===//
355 // Symbolic address operands
356 //===----------------------------------------------------------------------===//
358 // PC-relative asm operands.
359 def PCRel16 : PCRelAsmOperand<"16">;
360 def PCRel32 : PCRelAsmOperand<"32">;
362 // PC-relative offsets of a basic block. The offset is sign-extended
363 // and multiplied by 2.
364 def brtarget16 : PCRelOperand<OtherVT, PCRel16> {
365 let EncoderMethod = "getPC16DBLEncoding";
366 let DecoderMethod = "decodePC16DBLOperand";
368 def brtarget32 : PCRelOperand<OtherVT, PCRel32> {
369 let EncoderMethod = "getPC32DBLEncoding";
370 let DecoderMethod = "decodePC32DBLOperand";
373 // A PC-relative offset of a global value. The offset is sign-extended
374 // and multiplied by 2.
375 def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> {
376 let EncoderMethod = "getPC32DBLEncoding";
377 let DecoderMethod = "decodePC32DBLOperand";
380 // A PC-relative offset of a global value when the value is used as a
381 // call target. The offset is sign-extended and multiplied by 2.
382 def pcrel16call : PCRelAddress<i64, "pcrel16call", PCRel16> {
383 let PrintMethod = "printCallOperand";
384 let EncoderMethod = "getPLT16DBLEncoding";
385 let DecoderMethod = "decodePC16DBLOperand";
387 def pcrel32call : PCRelAddress<i64, "pcrel32call", PCRel32> {
388 let PrintMethod = "printCallOperand";
389 let EncoderMethod = "getPLT32DBLEncoding";
390 let DecoderMethod = "decodePC32DBLOperand";
393 //===----------------------------------------------------------------------===//
395 //===----------------------------------------------------------------------===//
397 // 12-bit displacement operands.
398 def disp12imm32 : Operand<i32>;
399 def disp12imm64 : Operand<i64>;
401 // 20-bit displacement operands.
402 def disp20imm32 : Operand<i32>;
403 def disp20imm64 : Operand<i64>;
405 def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">;
406 def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">;
407 def BDAddr64Disp12 : AddressAsmOperand<"BDAddr", "64", "12">;
408 def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">;
409 def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">;
410 def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">;
412 // DAG patterns and operands for addressing modes. Each mode has
413 // the form <type><range><group> where:
416 // shift : base + displacement (32-bit)
417 // bdaddr : base + displacement
418 // bdxaddr : base + displacement + index
419 // laaddr : like bdxaddr, but used for Load Address operations
420 // dynalloc : base + displacement + index + ADJDYNALLOC
422 // <range> is one of:
423 // 12 : the displacement is an unsigned 12-bit value
424 // 20 : the displacement is a signed 20-bit value
426 // <group> is one of:
427 // pair : used when there is an equivalent instruction with the opposite
428 // range value (12 or 20)
429 // only : used when there is no equivalent instruction with the opposite
431 def shift12only : BDMode <"BDAddr", "32", "12", "Only">;
432 def shift20only : BDMode <"BDAddr", "32", "20", "Only">;
433 def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">;
434 def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">;
435 def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">;
436 def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">;
437 def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">;
438 def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">;
439 def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">;
440 def bdxaddr20only128 : BDXMode<"BDXAddr", "64", "20", "Only128">;
441 def bdxaddr20pair : BDXMode<"BDXAddr", "64", "20", "Pair">;
442 def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">;
443 def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">;
444 def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">;
446 //===----------------------------------------------------------------------===//
448 //===----------------------------------------------------------------------===//
450 // Access registers. At present we just use them for accessing the thread
451 // pointer, so we don't expose them as register to LLVM.
452 def AccessReg : AsmOperandClass {
453 let Name = "AccessReg";
454 let ParserMethod = "parseAccessReg";
456 def access_reg : Immediate<i8, [{ return N->getZExtValue() < 16; }],
457 NOOP_SDNodeXForm, "AccessReg"> {
458 let ParserMatchClass = AccessReg;
461 // A 4-bit condition-code mask.
462 def cond4 : PatLeaf<(i8 imm), [{ return (N->getZExtValue() < 16); }]>,
464 let PrintMethod = "printCond4Operand";