1 //===-- SystemZOperands.td - SystemZ instruction operands ----*- tblgen-*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class ImmediateAsmOperand<string name>
17 let RenderMethod = "addImmOperands";
20 // Constructs both a DAG pattern and instruction operand for an immediate
21 // of type VT. PRED returns true if a node is acceptable and XFORM returns
22 // the operand value associated with the node. ASMOP is the name of the
23 // associated asm operand, and also forms the basis of the asm print method.
24 class Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop>
25 : PatLeaf<(vt imm), pred, xform>, Operand<vt> {
26 let PrintMethod = "print"##asmop##"Operand";
27 let ParserMatchClass = !cast<AsmOperandClass>(asmop);
30 // Constructs both a DAG pattern and instruction operand for a PC-relative
31 // address with address size VT. SELF is the name of the operand.
32 class PCRelAddress<ValueType vt, string self>
33 : ComplexPattern<vt, 1, "selectPCRelAddress", [z_pcrel_wrapper]>,
35 let MIOperandInfo = (ops !cast<Operand>(self));
38 // Constructs an AsmOperandClass for addressing mode FORMAT, treating the
39 // registers as having BITSIZE bits and displacements as having DISPSIZE bits.
40 class AddressAsmOperand<string format, string bitsize, string dispsize>
42 let Name = format##bitsize##"Disp"##dispsize;
43 let ParserMethod = "parse"##format##bitsize;
44 let RenderMethod = "add"##format##"Operands";
47 // Constructs both a DAG pattern and instruction operand for an addressing mode.
48 // The mode is selected by custom code in select<TYPE><DISPSIZE><SUFFIX>()
49 // and encoded by custom code in get<FORMAT><DISPSIZE>Encoding().
50 // The address registers have BITSIZE bits and displacements have
51 // DISPSIZE bits. NUMOPS is the number of operands that make up an
52 // address and OPERANDS lists the types of those operands using (ops ...).
53 // FORMAT is the type of addressing mode, which needs to match the names
54 // used in AddressAsmOperand.
55 class AddressingMode<string type, string bitsize, string dispsize,
56 string suffix, int numops, string format, dag operands>
57 : ComplexPattern<!cast<ValueType>("i"##bitsize), numops,
58 "select"##type##dispsize##suffix,
59 [add, sub, or, frameindex, z_adjdynalloc]>,
60 Operand<!cast<ValueType>("i"##bitsize)> {
61 let PrintMethod = "print"##format##"Operand";
62 let EncoderMethod = "get"##format##dispsize##"Encoding";
63 let MIOperandInfo = operands;
64 let ParserMatchClass =
65 !cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize);
68 // An addressing mode with a base and displacement but no index.
69 class BDMode<string type, string bitsize, string dispsize, string suffix>
70 : AddressingMode<type, bitsize, dispsize, suffix, 2, "BDAddr",
71 (ops !cast<RegisterOperand>("ADDR"##bitsize),
72 !cast<Immediate>("disp"##dispsize##"imm"##bitsize))>;
74 // An addressing mode with a base, displacement and index.
75 class BDXMode<string type, string bitsize, string dispsize, string suffix>
76 : AddressingMode<type, bitsize, dispsize, suffix, 3, "BDXAddr",
77 (ops !cast<RegisterOperand>("ADDR"##bitsize),
78 !cast<Immediate>("disp"##dispsize##"imm"##bitsize),
79 !cast<RegisterOperand>("ADDR"##bitsize))>;
81 //===----------------------------------------------------------------------===//
82 // Extracting immediate operands from nodes
83 // These all create MVT::i64 nodes to ensure the value is not sign-extended
84 // when converted from an SDNode to a MachineOperand later on.
85 //===----------------------------------------------------------------------===//
87 // Bits 0-15 (counting from the lsb).
88 def LL16 : SDNodeXForm<imm, [{
89 uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL;
90 return CurDAG->getTargetConstant(Value, MVT::i64);
93 // Bits 16-31 (counting from the lsb).
94 def LH16 : SDNodeXForm<imm, [{
95 uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16;
96 return CurDAG->getTargetConstant(Value, MVT::i64);
99 // Bits 32-47 (counting from the lsb).
100 def HL16 : SDNodeXForm<imm, [{
101 uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32;
102 return CurDAG->getTargetConstant(Value, MVT::i64);
105 // Bits 48-63 (counting from the lsb).
106 def HH16 : SDNodeXForm<imm, [{
107 uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48;
108 return CurDAG->getTargetConstant(Value, MVT::i64);
112 def LF32 : SDNodeXForm<imm, [{
113 uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL;
114 return CurDAG->getTargetConstant(Value, MVT::i64);
118 def HF32 : SDNodeXForm<imm, [{
119 uint64_t Value = N->getZExtValue() >> 32;
120 return CurDAG->getTargetConstant(Value, MVT::i64);
123 // Truncate an immediate to a 8-bit signed quantity.
124 def SIMM8 : SDNodeXForm<imm, [{
125 return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), MVT::i64);
128 // Truncate an immediate to a 8-bit unsigned quantity.
129 def UIMM8 : SDNodeXForm<imm, [{
130 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), MVT::i64);
133 // Truncate an immediate to a 16-bit signed quantity.
134 def SIMM16 : SDNodeXForm<imm, [{
135 return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), MVT::i64);
138 // Truncate an immediate to a 16-bit unsigned quantity.
139 def UIMM16 : SDNodeXForm<imm, [{
140 return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), MVT::i64);
143 // Truncate an immediate to a 32-bit signed quantity.
144 def SIMM32 : SDNodeXForm<imm, [{
145 return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), MVT::i64);
148 // Truncate an immediate to a 32-bit unsigned quantity.
149 def UIMM32 : SDNodeXForm<imm, [{
150 return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), MVT::i64);
153 // Negate and then truncate an immediate to a 32-bit unsigned quantity.
154 def NEGIMM32 : SDNodeXForm<imm, [{
155 return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), MVT::i64);
158 //===----------------------------------------------------------------------===//
159 // Immediate asm operands.
160 //===----------------------------------------------------------------------===//
162 def U4Imm : ImmediateAsmOperand<"U4Imm">;
163 def U6Imm : ImmediateAsmOperand<"U6Imm">;
164 def S8Imm : ImmediateAsmOperand<"S8Imm">;
165 def U8Imm : ImmediateAsmOperand<"U8Imm">;
166 def S16Imm : ImmediateAsmOperand<"S16Imm">;
167 def U16Imm : ImmediateAsmOperand<"U16Imm">;
168 def S32Imm : ImmediateAsmOperand<"S32Imm">;
169 def U32Imm : ImmediateAsmOperand<"U32Imm">;
171 //===----------------------------------------------------------------------===//
173 //===----------------------------------------------------------------------===//
175 def uimm8zx4 : Immediate<i8, [{
176 return isUInt<4>(N->getZExtValue());
177 }], NOOP_SDNodeXForm, "U4Imm">;
179 def uimm8zx6 : Immediate<i8, [{
180 return isUInt<6>(N->getZExtValue());
181 }], NOOP_SDNodeXForm, "U6Imm">;
183 def simm8 : Immediate<i8, [{}], SIMM8, "S8Imm">;
184 def uimm8 : Immediate<i8, [{}], UIMM8, "U8Imm">;
186 //===----------------------------------------------------------------------===//
188 //===----------------------------------------------------------------------===//
190 // Immediates for the lower and upper 16 bits of an i32, with the other
191 // bits of the i32 being zero.
192 def imm32ll16 : Immediate<i32, [{
193 return SystemZ::isImmLL(N->getZExtValue());
196 def imm32lh16 : Immediate<i32, [{
197 return SystemZ::isImmLH(N->getZExtValue());
200 // Immediates for the lower and upper 16 bits of an i32, with the other
201 // bits of the i32 being one.
202 def imm32ll16c : Immediate<i32, [{
203 return SystemZ::isImmLL(uint32_t(~N->getZExtValue()));
206 def imm32lh16c : Immediate<i32, [{
207 return SystemZ::isImmLH(uint32_t(~N->getZExtValue()));
211 def imm32sx8 : Immediate<i32, [{
212 return isInt<8>(N->getSExtValue());
215 def imm32zx8 : Immediate<i32, [{
216 return isUInt<8>(N->getZExtValue());
219 def imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">;
221 def imm32sx16 : Immediate<i32, [{
222 return isInt<16>(N->getSExtValue());
223 }], SIMM16, "S16Imm">;
225 def imm32zx16 : Immediate<i32, [{
226 return isUInt<16>(N->getZExtValue());
227 }], UIMM16, "U16Imm">;
229 def imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">;
231 // Full 32-bit immediates. we need both signed and unsigned versions
232 // because the assembler is picky. E.g. AFI requires signed operands
233 // while NILF requires unsigned ones.
234 def simm32 : Immediate<i32, [{}], SIMM32, "S32Imm">;
235 def uimm32 : Immediate<i32, [{}], UIMM32, "U32Imm">;
237 def imm32 : ImmLeaf<i32, [{}]>;
239 //===----------------------------------------------------------------------===//
241 //===----------------------------------------------------------------------===//
243 // Immediates for 16-bit chunks of an i64, with the other bits of the
245 def imm64ll16 : Immediate<i64, [{
246 return SystemZ::isImmLL(N->getZExtValue());
249 def imm64lh16 : Immediate<i64, [{
250 return SystemZ::isImmLH(N->getZExtValue());
253 def imm64hl16 : Immediate<i64, [{
254 return SystemZ::isImmHL(N->getZExtValue());
257 def imm64hh16 : Immediate<i64, [{
258 return SystemZ::isImmHH(N->getZExtValue());
261 // Immediates for 16-bit chunks of an i64, with the other bits of the
263 def imm64ll16c : Immediate<i64, [{
264 return SystemZ::isImmLL(uint64_t(~N->getZExtValue()));
267 def imm64lh16c : Immediate<i64, [{
268 return SystemZ::isImmLH(uint64_t(~N->getZExtValue()));
271 def imm64hl16c : Immediate<i64, [{
272 return SystemZ::isImmHL(uint64_t(~N->getZExtValue()));
275 def imm64hh16c : Immediate<i64, [{
276 return SystemZ::isImmHH(uint64_t(~N->getZExtValue()));
279 // Immediates for the lower and upper 32 bits of an i64, with the other
280 // bits of the i32 being zero.
281 def imm64lf32 : Immediate<i64, [{
282 return SystemZ::isImmLF(N->getZExtValue());
285 def imm64hf32 : Immediate<i64, [{
286 return SystemZ::isImmHF(N->getZExtValue());
289 // Immediates for the lower and upper 32 bits of an i64, with the other
290 // bits of the i32 being one.
291 def imm64lf32c : Immediate<i64, [{
292 return SystemZ::isImmLF(uint64_t(~N->getZExtValue()));
295 def imm64hf32c : Immediate<i64, [{
296 return SystemZ::isImmHF(uint64_t(~N->getZExtValue()));
300 def imm64sx8 : Immediate<i64, [{
301 return isInt<8>(N->getSExtValue());
304 def imm64sx16 : Immediate<i64, [{
305 return isInt<16>(N->getSExtValue());
306 }], SIMM16, "S16Imm">;
308 def imm64zx16 : Immediate<i64, [{
309 return isUInt<16>(N->getZExtValue());
310 }], UIMM16, "U16Imm">;
312 def imm64sx32 : Immediate<i64, [{
313 return isInt<32>(N->getSExtValue());
314 }], SIMM32, "S32Imm">;
316 def imm64zx32 : Immediate<i64, [{
317 return isUInt<32>(N->getZExtValue());
318 }], UIMM32, "U32Imm">;
320 def imm64zx32n : Immediate<i64, [{
321 return isUInt<32>(-N->getSExtValue());
322 }], NEGIMM32, "U32Imm">;
324 def imm64 : ImmLeaf<i64, [{}]>;
326 //===----------------------------------------------------------------------===//
327 // Floating-point immediates
328 //===----------------------------------------------------------------------===//
330 // Floating-point zero.
331 def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
333 // Floating point negative zero.
334 def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>;
336 //===----------------------------------------------------------------------===//
337 // Symbolic address operands
338 //===----------------------------------------------------------------------===//
340 // PC-relative offsets of a basic block. The offset is sign-extended
341 // and multiplied by 2.
342 def brtarget16 : Operand<OtherVT> {
343 let EncoderMethod = "getPC16DBLEncoding";
345 def brtarget32 : Operand<OtherVT> {
346 let EncoderMethod = "getPC32DBLEncoding";
349 // A PC-relative offset of a global value. The offset is sign-extended
350 // and multiplied by 2.
351 def pcrel32 : PCRelAddress<i64, "pcrel32"> {
352 let EncoderMethod = "getPC32DBLEncoding";
355 // A PC-relative offset of a global value when the value is used as a
356 // call target. The offset is sign-extended and multiplied by 2.
357 def pcrel16call : PCRelAddress<i64, "pcrel16call"> {
358 let PrintMethod = "printCallOperand";
359 let EncoderMethod = "getPLT16DBLEncoding";
361 def pcrel32call : PCRelAddress<i64, "pcrel32call"> {
362 let PrintMethod = "printCallOperand";
363 let EncoderMethod = "getPLT32DBLEncoding";
366 //===----------------------------------------------------------------------===//
368 //===----------------------------------------------------------------------===//
370 // 12-bit displacement operands.
371 def disp12imm32 : Operand<i32>;
372 def disp12imm64 : Operand<i64>;
374 // 20-bit displacement operands.
375 def disp20imm32 : Operand<i32>;
376 def disp20imm64 : Operand<i64>;
378 def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">;
379 def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">;
380 def BDAddr64Disp12 : AddressAsmOperand<"BDAddr", "64", "12">;
381 def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">;
382 def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">;
383 def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">;
385 // DAG patterns and operands for addressing modes. Each mode has
386 // the form <type><range><group> where:
389 // shift : base + displacement (32-bit)
390 // bdaddr : base + displacement
391 // bdxaddr : base + displacement + index
392 // laaddr : like bdxaddr, but used for Load Address operations
393 // dynalloc : base + displacement + index + ADJDYNALLOC
395 // <range> is one of:
396 // 12 : the displacement is an unsigned 12-bit value
397 // 20 : the displacement is a signed 20-bit value
399 // <group> is one of:
400 // pair : used when there is an equivalent instruction with the opposite
401 // range value (12 or 20)
402 // only : used when there is no equivalent instruction with the opposite
404 def shift12only : BDMode <"BDAddr", "32", "12", "Only">;
405 def shift20only : BDMode <"BDAddr", "32", "20", "Only">;
406 def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">;
407 def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">;
408 def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">;
409 def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">;
410 def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">;
411 def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">;
412 def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">;
413 def bdxaddr20only128 : BDXMode<"BDXAddr", "64", "20", "Only128">;
414 def bdxaddr20pair : BDXMode<"BDXAddr", "64", "20", "Pair">;
415 def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">;
416 def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">;
417 def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">;
419 //===----------------------------------------------------------------------===//
421 //===----------------------------------------------------------------------===//
423 // Access registers. At present we just use them for accessing the thread
424 // pointer, so we don't expose them as register to LLVM.
425 def AccessReg : AsmOperandClass {
426 let Name = "AccessReg";
427 let ParserMethod = "parseAccessReg";
429 def access_reg : Immediate<i8, [{ return N->getZExtValue() < 16; }],
430 NOOP_SDNodeXForm, "AccessReg"> {
431 let ParserMatchClass = AccessReg;
434 // A 4-bit condition-code mask.
435 def cond4 : PatLeaf<(i8 imm), [{ return (N->getZExtValue() < 16); }]>,
437 let PrintMethod = "printCond4Operand";