1 //===-- SystemZOperands.td - SystemZ instruction operands ----*- tblgen-*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class ImmediateAsmOperand<string name>
17 let RenderMethod = "addImmOperands";
19 class ImmediateTLSAsmOperand<string name>
22 let RenderMethod = "addImmTLSOperands";
25 // Constructs both a DAG pattern and instruction operand for an immediate
26 // of type VT. PRED returns true if a node is acceptable and XFORM returns
27 // the operand value associated with the node. ASMOP is the name of the
28 // associated asm operand, and also forms the basis of the asm print method.
29 class Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop>
30 : PatLeaf<(vt imm), pred, xform>, Operand<vt> {
31 let PrintMethod = "print"##asmop##"Operand";
32 let DecoderMethod = "decode"##asmop##"Operand";
33 let ParserMatchClass = !cast<AsmOperandClass>(asmop);
36 // Constructs an asm operand for a PC-relative address. SIZE says how
37 // many bits there are.
38 class PCRelAsmOperand<string size> : ImmediateAsmOperand<"PCRel"##size> {
39 let PredicateMethod = "isImm";
40 let ParserMethod = "parsePCRel"##size;
42 class PCRelTLSAsmOperand<string size>
43 : ImmediateTLSAsmOperand<"PCRelTLS"##size> {
44 let PredicateMethod = "isImmTLS";
45 let ParserMethod = "parsePCRelTLS"##size;
48 // Constructs an operand for a PC-relative address with address type VT.
49 // ASMOP is the associated asm operand.
50 class PCRelOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> {
51 let PrintMethod = "printPCRelOperand";
52 let ParserMatchClass = asmop;
54 class PCRelTLSOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> {
55 let PrintMethod = "printPCRelTLSOperand";
56 let ParserMatchClass = asmop;
59 // Constructs both a DAG pattern and instruction operand for a PC-relative
60 // address with address size VT. SELF is the name of the operand and
61 // ASMOP is the associated asm operand.
62 class PCRelAddress<ValueType vt, string self, AsmOperandClass asmop>
63 : ComplexPattern<vt, 1, "selectPCRelAddress",
64 [z_pcrel_wrapper, z_pcrel_offset]>,
65 PCRelOperand<vt, asmop> {
66 let MIOperandInfo = (ops !cast<Operand>(self));
69 // Constructs an AsmOperandClass for addressing mode FORMAT, treating the
70 // registers as having BITSIZE bits and displacements as having DISPSIZE bits.
71 // LENGTH is "LenN" for addresses with an N-bit length field, otherwise it
73 class AddressAsmOperand<string format, string bitsize, string dispsize,
76 let Name = format##bitsize##"Disp"##dispsize##length;
77 let ParserMethod = "parse"##format##bitsize;
78 let RenderMethod = "add"##format##"Operands";
81 // Constructs both a DAG pattern and instruction operand for an addressing mode.
82 // FORMAT, BITSIZE, DISPSIZE and LENGTH are the parameters to an associated
83 // AddressAsmOperand. OPERANDS is a list of NUMOPS individual operands
84 // (base register, displacement, etc.). SELTYPE is the type of the memory
85 // operand for selection purposes; sometimes we want different selection
86 // choices for the same underlying addressing mode. SUFFIX is similarly
87 // a suffix appended to the displacement for selection purposes;
88 // e.g. we want to reject small 20-bit displacements if a 12-bit form
89 // also exists, but we want to accept them otherwise.
90 class AddressingMode<string seltype, string bitsize, string dispsize,
91 string suffix, string length, int numops, string format,
93 : ComplexPattern<!cast<ValueType>("i"##bitsize), numops,
94 "select"##seltype##dispsize##suffix##length,
95 [add, sub, or, frameindex, z_adjdynalloc]>,
96 Operand<!cast<ValueType>("i"##bitsize)> {
97 let PrintMethod = "print"##format##"Operand";
98 let EncoderMethod = "get"##format##dispsize##length##"Encoding";
100 "decode"##format##bitsize##"Disp"##dispsize##length##"Operand";
101 let MIOperandInfo = operands;
102 let ParserMatchClass =
103 !cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize##length);
106 // An addressing mode with a base and displacement but no index.
107 class BDMode<string type, string bitsize, string dispsize, string suffix>
108 : AddressingMode<type, bitsize, dispsize, suffix, "", 2, "BDAddr",
109 (ops !cast<RegisterOperand>("ADDR"##bitsize),
110 !cast<Immediate>("disp"##dispsize##"imm"##bitsize))>;
112 // An addressing mode with a base, displacement and index.
113 class BDXMode<string type, string bitsize, string dispsize, string suffix>
114 : AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDXAddr",
115 (ops !cast<RegisterOperand>("ADDR"##bitsize),
116 !cast<Immediate>("disp"##dispsize##"imm"##bitsize),
117 !cast<RegisterOperand>("ADDR"##bitsize))>;
119 // A BDMode paired with an immediate length operand of LENSIZE bits.
120 class BDLMode<string type, string bitsize, string dispsize, string suffix,
122 : AddressingMode<type, bitsize, dispsize, suffix, "Len"##lensize, 3,
124 (ops !cast<RegisterOperand>("ADDR"##bitsize),
125 !cast<Immediate>("disp"##dispsize##"imm"##bitsize),
126 !cast<Immediate>("imm"##bitsize))>;
128 //===----------------------------------------------------------------------===//
129 // Extracting immediate operands from nodes
130 // These all create MVT::i64 nodes to ensure the value is not sign-extended
131 // when converted from an SDNode to a MachineOperand later on.
132 //===----------------------------------------------------------------------===//
134 // Bits 0-15 (counting from the lsb).
135 def LL16 : SDNodeXForm<imm, [{
136 uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL;
137 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
140 // Bits 16-31 (counting from the lsb).
141 def LH16 : SDNodeXForm<imm, [{
142 uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16;
143 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
146 // Bits 32-47 (counting from the lsb).
147 def HL16 : SDNodeXForm<imm, [{
148 uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32;
149 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
152 // Bits 48-63 (counting from the lsb).
153 def HH16 : SDNodeXForm<imm, [{
154 uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48;
155 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
159 def LF32 : SDNodeXForm<imm, [{
160 uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL;
161 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
165 def HF32 : SDNodeXForm<imm, [{
166 uint64_t Value = N->getZExtValue() >> 32;
167 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
170 // Truncate an immediate to a 8-bit signed quantity.
171 def SIMM8 : SDNodeXForm<imm, [{
172 return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), SDLoc(N),
176 // Truncate an immediate to a 8-bit unsigned quantity.
177 def UIMM8 : SDNodeXForm<imm, [{
178 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), SDLoc(N),
182 // Truncate an immediate to a 16-bit signed quantity.
183 def SIMM16 : SDNodeXForm<imm, [{
184 return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), SDLoc(N),
188 // Truncate an immediate to a 16-bit unsigned quantity.
189 def UIMM16 : SDNodeXForm<imm, [{
190 return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), SDLoc(N),
194 // Truncate an immediate to a 32-bit signed quantity.
195 def SIMM32 : SDNodeXForm<imm, [{
196 return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), SDLoc(N),
200 // Truncate an immediate to a 32-bit unsigned quantity.
201 def UIMM32 : SDNodeXForm<imm, [{
202 return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), SDLoc(N),
206 // Negate and then truncate an immediate to a 32-bit unsigned quantity.
207 def NEGIMM32 : SDNodeXForm<imm, [{
208 return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), SDLoc(N),
212 //===----------------------------------------------------------------------===//
213 // Immediate asm operands.
214 //===----------------------------------------------------------------------===//
216 def U4Imm : ImmediateAsmOperand<"U4Imm">;
217 def U6Imm : ImmediateAsmOperand<"U6Imm">;
218 def S8Imm : ImmediateAsmOperand<"S8Imm">;
219 def U8Imm : ImmediateAsmOperand<"U8Imm">;
220 def S16Imm : ImmediateAsmOperand<"S16Imm">;
221 def U16Imm : ImmediateAsmOperand<"U16Imm">;
222 def S32Imm : ImmediateAsmOperand<"S32Imm">;
223 def U32Imm : ImmediateAsmOperand<"U32Imm">;
225 //===----------------------------------------------------------------------===//
227 //===----------------------------------------------------------------------===//
229 // Immediates for the lower and upper 16 bits of an i32, with the other
230 // bits of the i32 being zero.
231 def imm32ll16 : Immediate<i32, [{
232 return SystemZ::isImmLL(N->getZExtValue());
235 def imm32lh16 : Immediate<i32, [{
236 return SystemZ::isImmLH(N->getZExtValue());
239 // Immediates for the lower and upper 16 bits of an i32, with the other
240 // bits of the i32 being one.
241 def imm32ll16c : Immediate<i32, [{
242 return SystemZ::isImmLL(uint32_t(~N->getZExtValue()));
245 def imm32lh16c : Immediate<i32, [{
246 return SystemZ::isImmLH(uint32_t(~N->getZExtValue()));
250 def imm32zx4 : Immediate<i32, [{
251 return isUInt<4>(N->getZExtValue());
252 }], NOOP_SDNodeXForm, "U4Imm">;
254 def imm32zx6 : Immediate<i32, [{
255 return isUInt<6>(N->getZExtValue());
256 }], NOOP_SDNodeXForm, "U6Imm">;
258 def imm32sx8 : Immediate<i32, [{
259 return isInt<8>(N->getSExtValue());
262 def imm32zx8 : Immediate<i32, [{
263 return isUInt<8>(N->getZExtValue());
266 def imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">;
268 def imm32sx16 : Immediate<i32, [{
269 return isInt<16>(N->getSExtValue());
270 }], SIMM16, "S16Imm">;
272 def imm32zx16 : Immediate<i32, [{
273 return isUInt<16>(N->getZExtValue());
274 }], UIMM16, "U16Imm">;
276 def imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">;
278 // Full 32-bit immediates. we need both signed and unsigned versions
279 // because the assembler is picky. E.g. AFI requires signed operands
280 // while NILF requires unsigned ones.
281 def simm32 : Immediate<i32, [{}], SIMM32, "S32Imm">;
282 def uimm32 : Immediate<i32, [{}], UIMM32, "U32Imm">;
284 def imm32 : ImmLeaf<i32, [{}]>;
286 //===----------------------------------------------------------------------===//
288 //===----------------------------------------------------------------------===//
290 // Immediates for 16-bit chunks of an i64, with the other bits of the
292 def imm64ll16 : Immediate<i64, [{
293 return SystemZ::isImmLL(N->getZExtValue());
296 def imm64lh16 : Immediate<i64, [{
297 return SystemZ::isImmLH(N->getZExtValue());
300 def imm64hl16 : Immediate<i64, [{
301 return SystemZ::isImmHL(N->getZExtValue());
304 def imm64hh16 : Immediate<i64, [{
305 return SystemZ::isImmHH(N->getZExtValue());
308 // Immediates for 16-bit chunks of an i64, with the other bits of the
310 def imm64ll16c : Immediate<i64, [{
311 return SystemZ::isImmLL(uint64_t(~N->getZExtValue()));
314 def imm64lh16c : Immediate<i64, [{
315 return SystemZ::isImmLH(uint64_t(~N->getZExtValue()));
318 def imm64hl16c : Immediate<i64, [{
319 return SystemZ::isImmHL(uint64_t(~N->getZExtValue()));
322 def imm64hh16c : Immediate<i64, [{
323 return SystemZ::isImmHH(uint64_t(~N->getZExtValue()));
326 // Immediates for the lower and upper 32 bits of an i64, with the other
327 // bits of the i32 being zero.
328 def imm64lf32 : Immediate<i64, [{
329 return SystemZ::isImmLF(N->getZExtValue());
332 def imm64hf32 : Immediate<i64, [{
333 return SystemZ::isImmHF(N->getZExtValue());
336 // Immediates for the lower and upper 32 bits of an i64, with the other
337 // bits of the i32 being one.
338 def imm64lf32c : Immediate<i64, [{
339 return SystemZ::isImmLF(uint64_t(~N->getZExtValue()));
342 def imm64hf32c : Immediate<i64, [{
343 return SystemZ::isImmHF(uint64_t(~N->getZExtValue()));
347 def imm64sx8 : Immediate<i64, [{
348 return isInt<8>(N->getSExtValue());
351 def imm64zx8 : Immediate<i64, [{
352 return isUInt<8>(N->getSExtValue());
355 def imm64sx16 : Immediate<i64, [{
356 return isInt<16>(N->getSExtValue());
357 }], SIMM16, "S16Imm">;
359 def imm64zx16 : Immediate<i64, [{
360 return isUInt<16>(N->getZExtValue());
361 }], UIMM16, "U16Imm">;
363 def imm64sx32 : Immediate<i64, [{
364 return isInt<32>(N->getSExtValue());
365 }], SIMM32, "S32Imm">;
367 def imm64zx32 : Immediate<i64, [{
368 return isUInt<32>(N->getZExtValue());
369 }], UIMM32, "U32Imm">;
371 def imm64zx32n : Immediate<i64, [{
372 return isUInt<32>(-N->getSExtValue());
373 }], NEGIMM32, "U32Imm">;
375 def imm64 : ImmLeaf<i64, [{}]>, Operand<i64>;
377 //===----------------------------------------------------------------------===//
378 // Floating-point immediates
379 //===----------------------------------------------------------------------===//
381 // Floating-point zero.
382 def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
384 // Floating point negative zero.
385 def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>;
387 //===----------------------------------------------------------------------===//
388 // Symbolic address operands
389 //===----------------------------------------------------------------------===//
391 // PC-relative asm operands.
392 def PCRel16 : PCRelAsmOperand<"16">;
393 def PCRel32 : PCRelAsmOperand<"32">;
394 def PCRelTLS16 : PCRelTLSAsmOperand<"16">;
395 def PCRelTLS32 : PCRelTLSAsmOperand<"32">;
397 // PC-relative offsets of a basic block. The offset is sign-extended
398 // and multiplied by 2.
399 def brtarget16 : PCRelOperand<OtherVT, PCRel16> {
400 let EncoderMethod = "getPC16DBLEncoding";
401 let DecoderMethod = "decodePC16DBLOperand";
403 def brtarget32 : PCRelOperand<OtherVT, PCRel32> {
404 let EncoderMethod = "getPC32DBLEncoding";
405 let DecoderMethod = "decodePC32DBLOperand";
408 // Variants of brtarget16/32 with an optional additional TLS symbol.
409 // These are used to annotate calls to __tls_get_offset.
410 def tlssym : Operand<i64> { }
411 def brtarget16tls : PCRelTLSOperand<OtherVT, PCRelTLS16> {
412 let MIOperandInfo = (ops brtarget16:$func, tlssym:$sym);
413 let EncoderMethod = "getPC16DBLTLSEncoding";
414 let DecoderMethod = "decodePC16DBLOperand";
416 def brtarget32tls : PCRelTLSOperand<OtherVT, PCRelTLS32> {
417 let MIOperandInfo = (ops brtarget32:$func, tlssym:$sym);
418 let EncoderMethod = "getPC32DBLTLSEncoding";
419 let DecoderMethod = "decodePC32DBLOperand";
422 // A PC-relative offset of a global value. The offset is sign-extended
423 // and multiplied by 2.
424 def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> {
425 let EncoderMethod = "getPC32DBLEncoding";
426 let DecoderMethod = "decodePC32DBLOperand";
429 //===----------------------------------------------------------------------===//
431 //===----------------------------------------------------------------------===//
433 // 12-bit displacement operands.
434 def disp12imm32 : Operand<i32>;
435 def disp12imm64 : Operand<i64>;
437 // 20-bit displacement operands.
438 def disp20imm32 : Operand<i32>;
439 def disp20imm64 : Operand<i64>;
441 def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">;
442 def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">;
443 def BDAddr64Disp12 : AddressAsmOperand<"BDAddr", "64", "12">;
444 def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">;
445 def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">;
446 def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">;
447 def BDLAddr64Disp12Len8 : AddressAsmOperand<"BDLAddr", "64", "12", "Len8">;
449 // DAG patterns and operands for addressing modes. Each mode has
450 // the form <type><range><group>[<len>] where:
453 // shift : base + displacement (32-bit)
454 // bdaddr : base + displacement
455 // mviaddr : like bdaddr, but reject cases with a natural index
456 // bdxaddr : base + displacement + index
457 // laaddr : like bdxaddr, but used for Load Address operations
458 // dynalloc : base + displacement + index + ADJDYNALLOC
459 // bdladdr : base + displacement with a length field
461 // <range> is one of:
462 // 12 : the displacement is an unsigned 12-bit value
463 // 20 : the displacement is a signed 20-bit value
465 // <group> is one of:
466 // pair : used when there is an equivalent instruction with the opposite
467 // range value (12 or 20)
468 // only : used when there is no equivalent instruction with the opposite
473 // <empty> : there is no length field
474 // len8 : the length field is 8 bits, with a range of [1, 0x100].
475 def shift12only : BDMode <"BDAddr", "32", "12", "Only">;
476 def shift20only : BDMode <"BDAddr", "32", "20", "Only">;
477 def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">;
478 def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">;
479 def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">;
480 def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">;
481 def mviaddr12pair : BDMode <"MVIAddr", "64", "12", "Pair">;
482 def mviaddr20pair : BDMode <"MVIAddr", "64", "20", "Pair">;
483 def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">;
484 def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">;
485 def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">;
486 def bdxaddr20only128 : BDXMode<"BDXAddr", "64", "20", "Only128">;
487 def bdxaddr20pair : BDXMode<"BDXAddr", "64", "20", "Pair">;
488 def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">;
489 def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">;
490 def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">;
491 def bdladdr12onlylen8 : BDLMode<"BDLAddr", "64", "12", "Only", "8">;
493 //===----------------------------------------------------------------------===//
495 //===----------------------------------------------------------------------===//
497 // Access registers. At present we just use them for accessing the thread
498 // pointer, so we don't expose them as register to LLVM.
499 def AccessReg : AsmOperandClass {
500 let Name = "AccessReg";
501 let ParserMethod = "parseAccessReg";
503 def access_reg : Immediate<i32, [{ return N->getZExtValue() < 16; }],
504 NOOP_SDNodeXForm, "AccessReg"> {
505 let ParserMatchClass = AccessReg;
508 // A 4-bit condition-code mask.
509 def cond4 : PatLeaf<(i32 imm), [{ return (N->getZExtValue() < 16); }]>,
511 let PrintMethod = "printCond4Operand";