1 //===-- SystemZOperands.td - SystemZ instruction operands ----*- tblgen-*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class ImmediateAsmOperand<string name>
17 let RenderMethod = "addImmOperands";
19 class ImmediateTLSAsmOperand<string name>
22 let RenderMethod = "addImmTLSOperands";
25 // Constructs both a DAG pattern and instruction operand for an immediate
26 // of type VT. PRED returns true if a node is acceptable and XFORM returns
27 // the operand value associated with the node. ASMOP is the name of the
28 // associated asm operand, and also forms the basis of the asm print method.
29 class Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop>
30 : PatLeaf<(vt imm), pred, xform>, Operand<vt> {
31 let PrintMethod = "print"##asmop##"Operand";
32 let DecoderMethod = "decode"##asmop##"Operand";
33 let ParserMatchClass = !cast<AsmOperandClass>(asmop);
36 // Constructs an asm operand for a PC-relative address. SIZE says how
37 // many bits there are.
38 class PCRelAsmOperand<string size> : ImmediateAsmOperand<"PCRel"##size> {
39 let PredicateMethod = "isImm";
40 let ParserMethod = "parsePCRel"##size;
42 class PCRelTLSAsmOperand<string size>
43 : ImmediateTLSAsmOperand<"PCRelTLS"##size> {
44 let PredicateMethod = "isImmTLS";
45 let ParserMethod = "parsePCRelTLS"##size;
48 // Constructs an operand for a PC-relative address with address type VT.
49 // ASMOP is the associated asm operand.
50 class PCRelOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> {
51 let PrintMethod = "printPCRelOperand";
52 let ParserMatchClass = asmop;
54 class PCRelTLSOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> {
55 let PrintMethod = "printPCRelTLSOperand";
56 let ParserMatchClass = asmop;
59 // Constructs both a DAG pattern and instruction operand for a PC-relative
60 // address with address size VT. SELF is the name of the operand and
61 // ASMOP is the associated asm operand.
62 class PCRelAddress<ValueType vt, string self, AsmOperandClass asmop>
63 : ComplexPattern<vt, 1, "selectPCRelAddress",
64 [z_pcrel_wrapper, z_pcrel_offset]>,
65 PCRelOperand<vt, asmop> {
66 let MIOperandInfo = (ops !cast<Operand>(self));
69 // Constructs an AsmOperandClass for addressing mode FORMAT, treating the
70 // registers as having BITSIZE bits and displacements as having DISPSIZE bits.
71 // LENGTH is "LenN" for addresses with an N-bit length field, otherwise it
73 class AddressAsmOperand<string format, string bitsize, string dispsize,
76 let Name = format##bitsize##"Disp"##dispsize##length;
77 let ParserMethod = "parse"##format##bitsize;
78 let RenderMethod = "add"##format##"Operands";
81 // Constructs an instruction operand for an addressing mode. FORMAT,
82 // BITSIZE, DISPSIZE and LENGTH are the parameters to an associated
83 // AddressAsmOperand. OPERANDS is a list of individual operands
84 // (base register, displacement, etc.).
85 class AddressOperand<string bitsize, string dispsize, string length,
86 string format, dag operands>
87 : Operand<!cast<ValueType>("i"##bitsize)> {
88 let PrintMethod = "print"##format##"Operand";
89 let EncoderMethod = "get"##format##dispsize##length##"Encoding";
91 "decode"##format##bitsize##"Disp"##dispsize##length##"Operand";
92 let MIOperandInfo = operands;
93 let ParserMatchClass =
94 !cast<AddressAsmOperand>(format##bitsize##"Disp"##dispsize##length);
97 // Constructs both a DAG pattern and instruction operand for an addressing mode.
98 // FORMAT, BITSIZE, DISPSIZE and LENGTH are the parameters to an associated
99 // AddressAsmOperand. OPERANDS is a list of NUMOPS individual operands
100 // (base register, displacement, etc.). SELTYPE is the type of the memory
101 // operand for selection purposes; sometimes we want different selection
102 // choices for the same underlying addressing mode. SUFFIX is similarly
103 // a suffix appended to the displacement for selection purposes;
104 // e.g. we want to reject small 20-bit displacements if a 12-bit form
105 // also exists, but we want to accept them otherwise.
106 class AddressingMode<string seltype, string bitsize, string dispsize,
107 string suffix, string length, int numops, string format,
109 : ComplexPattern<!cast<ValueType>("i"##bitsize), numops,
110 "select"##seltype##dispsize##suffix##length,
111 [add, sub, or, frameindex, z_adjdynalloc]>,
112 AddressOperand<bitsize, dispsize, length, format, operands>;
114 // An addressing mode with a base and displacement but no index.
115 class BDMode<string type, string bitsize, string dispsize, string suffix>
116 : AddressingMode<type, bitsize, dispsize, suffix, "", 2, "BDAddr",
117 (ops !cast<RegisterOperand>("ADDR"##bitsize),
118 !cast<Immediate>("disp"##dispsize##"imm"##bitsize))>;
120 // An addressing mode with a base, displacement and index.
121 class BDXMode<string type, string bitsize, string dispsize, string suffix>
122 : AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDXAddr",
123 (ops !cast<RegisterOperand>("ADDR"##bitsize),
124 !cast<Immediate>("disp"##dispsize##"imm"##bitsize),
125 !cast<RegisterOperand>("ADDR"##bitsize))>;
127 // A BDMode paired with an immediate length operand of LENSIZE bits.
128 class BDLMode<string type, string bitsize, string dispsize, string suffix,
130 : AddressingMode<type, bitsize, dispsize, suffix, "Len"##lensize, 3,
132 (ops !cast<RegisterOperand>("ADDR"##bitsize),
133 !cast<Immediate>("disp"##dispsize##"imm"##bitsize),
134 !cast<Immediate>("imm"##bitsize))>;
136 // An addressing mode with a base, displacement and a vector index.
137 class BDVMode<string bitsize, string dispsize>
138 : AddressOperand<bitsize, dispsize, "", "BDVAddr",
139 (ops !cast<RegisterOperand>("ADDR"##bitsize),
140 !cast<Immediate>("disp"##dispsize##"imm"##bitsize),
141 !cast<RegisterOperand>("VR128"))>;
143 //===----------------------------------------------------------------------===//
144 // Extracting immediate operands from nodes
145 // These all create MVT::i64 nodes to ensure the value is not sign-extended
146 // when converted from an SDNode to a MachineOperand later on.
147 //===----------------------------------------------------------------------===//
149 // Bits 0-15 (counting from the lsb).
150 def LL16 : SDNodeXForm<imm, [{
151 uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL;
152 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
155 // Bits 16-31 (counting from the lsb).
156 def LH16 : SDNodeXForm<imm, [{
157 uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16;
158 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
161 // Bits 32-47 (counting from the lsb).
162 def HL16 : SDNodeXForm<imm, [{
163 uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32;
164 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
167 // Bits 48-63 (counting from the lsb).
168 def HH16 : SDNodeXForm<imm, [{
169 uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48;
170 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
174 def LF32 : SDNodeXForm<imm, [{
175 uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL;
176 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
180 def HF32 : SDNodeXForm<imm, [{
181 uint64_t Value = N->getZExtValue() >> 32;
182 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
185 // Truncate an immediate to a 8-bit signed quantity.
186 def SIMM8 : SDNodeXForm<imm, [{
187 return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), SDLoc(N),
191 // Truncate an immediate to a 8-bit unsigned quantity.
192 def UIMM8 : SDNodeXForm<imm, [{
193 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), SDLoc(N),
197 // Truncate an immediate to a 8-bit unsigned quantity and mask off low bit.
198 def UIMM8EVEN : SDNodeXForm<imm, [{
199 return CurDAG->getTargetConstant(N->getZExtValue() & 0xfe, SDLoc(N),
203 // Truncate an immediate to a 12-bit unsigned quantity.
204 def UIMM12 : SDNodeXForm<imm, [{
205 return CurDAG->getTargetConstant(N->getZExtValue() & 0xfff, SDLoc(N),
209 // Truncate an immediate to a 16-bit signed quantity.
210 def SIMM16 : SDNodeXForm<imm, [{
211 return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), SDLoc(N),
215 // Truncate an immediate to a 16-bit unsigned quantity.
216 def UIMM16 : SDNodeXForm<imm, [{
217 return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), SDLoc(N),
221 // Truncate an immediate to a 32-bit signed quantity.
222 def SIMM32 : SDNodeXForm<imm, [{
223 return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), SDLoc(N),
227 // Truncate an immediate to a 32-bit unsigned quantity.
228 def UIMM32 : SDNodeXForm<imm, [{
229 return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), SDLoc(N),
233 // Negate and then truncate an immediate to a 32-bit unsigned quantity.
234 def NEGIMM32 : SDNodeXForm<imm, [{
235 return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), SDLoc(N),
239 //===----------------------------------------------------------------------===//
240 // Immediate asm operands.
241 //===----------------------------------------------------------------------===//
243 def U1Imm : ImmediateAsmOperand<"U1Imm">;
244 def U2Imm : ImmediateAsmOperand<"U2Imm">;
245 def U3Imm : ImmediateAsmOperand<"U3Imm">;
246 def U4Imm : ImmediateAsmOperand<"U4Imm">;
247 def U6Imm : ImmediateAsmOperand<"U6Imm">;
248 def S8Imm : ImmediateAsmOperand<"S8Imm">;
249 def U8Imm : ImmediateAsmOperand<"U8Imm">;
250 def U12Imm : ImmediateAsmOperand<"U12Imm">;
251 def S16Imm : ImmediateAsmOperand<"S16Imm">;
252 def U16Imm : ImmediateAsmOperand<"U16Imm">;
253 def S32Imm : ImmediateAsmOperand<"S32Imm">;
254 def U32Imm : ImmediateAsmOperand<"U32Imm">;
256 //===----------------------------------------------------------------------===//
258 //===----------------------------------------------------------------------===//
260 // Immediates for the lower and upper 16 bits of an i32, with the other
261 // bits of the i32 being zero.
262 def imm32ll16 : Immediate<i32, [{
263 return SystemZ::isImmLL(N->getZExtValue());
266 def imm32lh16 : Immediate<i32, [{
267 return SystemZ::isImmLH(N->getZExtValue());
270 // Immediates for the lower and upper 16 bits of an i32, with the other
271 // bits of the i32 being one.
272 def imm32ll16c : Immediate<i32, [{
273 return SystemZ::isImmLL(uint32_t(~N->getZExtValue()));
276 def imm32lh16c : Immediate<i32, [{
277 return SystemZ::isImmLH(uint32_t(~N->getZExtValue()));
281 def imm32zx1 : Immediate<i32, [{
282 return isUInt<1>(N->getZExtValue());
283 }], NOOP_SDNodeXForm, "U1Imm">;
285 def imm32zx2 : Immediate<i32, [{
286 return isUInt<2>(N->getZExtValue());
287 }], NOOP_SDNodeXForm, "U2Imm">;
289 def imm32zx3 : Immediate<i32, [{
290 return isUInt<3>(N->getZExtValue());
291 }], NOOP_SDNodeXForm, "U3Imm">;
293 def imm32zx4 : Immediate<i32, [{
294 return isUInt<4>(N->getZExtValue());
295 }], NOOP_SDNodeXForm, "U4Imm">;
297 // Note: this enforces an even value during code generation only.
298 // When used from the assembler, any 4-bit value is allowed.
299 def imm32zx4even : Immediate<i32, [{
300 return isUInt<4>(N->getZExtValue());
301 }], UIMM8EVEN, "U4Imm">;
303 def imm32zx6 : Immediate<i32, [{
304 return isUInt<6>(N->getZExtValue());
305 }], NOOP_SDNodeXForm, "U6Imm">;
307 def imm32sx8 : Immediate<i32, [{
308 return isInt<8>(N->getSExtValue());
311 def imm32zx8 : Immediate<i32, [{
312 return isUInt<8>(N->getZExtValue());
315 def imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">;
317 def imm32zx12 : Immediate<i32, [{
318 return isUInt<12>(N->getZExtValue());
319 }], UIMM12, "U12Imm">;
321 def imm32sx16 : Immediate<i32, [{
322 return isInt<16>(N->getSExtValue());
323 }], SIMM16, "S16Imm">;
325 def imm32zx16 : Immediate<i32, [{
326 return isUInt<16>(N->getZExtValue());
327 }], UIMM16, "U16Imm">;
329 def imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">;
331 // Full 32-bit immediates. we need both signed and unsigned versions
332 // because the assembler is picky. E.g. AFI requires signed operands
333 // while NILF requires unsigned ones.
334 def simm32 : Immediate<i32, [{}], SIMM32, "S32Imm">;
335 def uimm32 : Immediate<i32, [{}], UIMM32, "U32Imm">;
337 def imm32 : ImmLeaf<i32, [{}]>;
339 //===----------------------------------------------------------------------===//
341 //===----------------------------------------------------------------------===//
343 // Immediates for 16-bit chunks of an i64, with the other bits of the
345 def imm64ll16 : Immediate<i64, [{
346 return SystemZ::isImmLL(N->getZExtValue());
349 def imm64lh16 : Immediate<i64, [{
350 return SystemZ::isImmLH(N->getZExtValue());
353 def imm64hl16 : Immediate<i64, [{
354 return SystemZ::isImmHL(N->getZExtValue());
357 def imm64hh16 : Immediate<i64, [{
358 return SystemZ::isImmHH(N->getZExtValue());
361 // Immediates for 16-bit chunks of an i64, with the other bits of the
363 def imm64ll16c : Immediate<i64, [{
364 return SystemZ::isImmLL(uint64_t(~N->getZExtValue()));
367 def imm64lh16c : Immediate<i64, [{
368 return SystemZ::isImmLH(uint64_t(~N->getZExtValue()));
371 def imm64hl16c : Immediate<i64, [{
372 return SystemZ::isImmHL(uint64_t(~N->getZExtValue()));
375 def imm64hh16c : Immediate<i64, [{
376 return SystemZ::isImmHH(uint64_t(~N->getZExtValue()));
379 // Immediates for the lower and upper 32 bits of an i64, with the other
380 // bits of the i32 being zero.
381 def imm64lf32 : Immediate<i64, [{
382 return SystemZ::isImmLF(N->getZExtValue());
385 def imm64hf32 : Immediate<i64, [{
386 return SystemZ::isImmHF(N->getZExtValue());
389 // Immediates for the lower and upper 32 bits of an i64, with the other
390 // bits of the i32 being one.
391 def imm64lf32c : Immediate<i64, [{
392 return SystemZ::isImmLF(uint64_t(~N->getZExtValue()));
395 def imm64hf32c : Immediate<i64, [{
396 return SystemZ::isImmHF(uint64_t(~N->getZExtValue()));
400 def imm64sx8 : Immediate<i64, [{
401 return isInt<8>(N->getSExtValue());
404 def imm64zx8 : Immediate<i64, [{
405 return isUInt<8>(N->getSExtValue());
408 def imm64sx16 : Immediate<i64, [{
409 return isInt<16>(N->getSExtValue());
410 }], SIMM16, "S16Imm">;
412 def imm64zx16 : Immediate<i64, [{
413 return isUInt<16>(N->getZExtValue());
414 }], UIMM16, "U16Imm">;
416 def imm64sx32 : Immediate<i64, [{
417 return isInt<32>(N->getSExtValue());
418 }], SIMM32, "S32Imm">;
420 def imm64zx32 : Immediate<i64, [{
421 return isUInt<32>(N->getZExtValue());
422 }], UIMM32, "U32Imm">;
424 def imm64zx32n : Immediate<i64, [{
425 return isUInt<32>(-N->getSExtValue());
426 }], NEGIMM32, "U32Imm">;
428 def imm64 : ImmLeaf<i64, [{}]>, Operand<i64>;
430 //===----------------------------------------------------------------------===//
431 // Floating-point immediates
432 //===----------------------------------------------------------------------===//
434 // Floating-point zero.
435 def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
437 // Floating point negative zero.
438 def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>;
440 //===----------------------------------------------------------------------===//
441 // Symbolic address operands
442 //===----------------------------------------------------------------------===//
444 // PC-relative asm operands.
445 def PCRel16 : PCRelAsmOperand<"16">;
446 def PCRel32 : PCRelAsmOperand<"32">;
447 def PCRelTLS16 : PCRelTLSAsmOperand<"16">;
448 def PCRelTLS32 : PCRelTLSAsmOperand<"32">;
450 // PC-relative offsets of a basic block. The offset is sign-extended
451 // and multiplied by 2.
452 def brtarget16 : PCRelOperand<OtherVT, PCRel16> {
453 let EncoderMethod = "getPC16DBLEncoding";
454 let DecoderMethod = "decodePC16DBLOperand";
456 def brtarget32 : PCRelOperand<OtherVT, PCRel32> {
457 let EncoderMethod = "getPC32DBLEncoding";
458 let DecoderMethod = "decodePC32DBLOperand";
461 // Variants of brtarget16/32 with an optional additional TLS symbol.
462 // These are used to annotate calls to __tls_get_offset.
463 def tlssym : Operand<i64> { }
464 def brtarget16tls : PCRelTLSOperand<OtherVT, PCRelTLS16> {
465 let MIOperandInfo = (ops brtarget16:$func, tlssym:$sym);
466 let EncoderMethod = "getPC16DBLTLSEncoding";
467 let DecoderMethod = "decodePC16DBLOperand";
469 def brtarget32tls : PCRelTLSOperand<OtherVT, PCRelTLS32> {
470 let MIOperandInfo = (ops brtarget32:$func, tlssym:$sym);
471 let EncoderMethod = "getPC32DBLTLSEncoding";
472 let DecoderMethod = "decodePC32DBLOperand";
475 // A PC-relative offset of a global value. The offset is sign-extended
476 // and multiplied by 2.
477 def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> {
478 let EncoderMethod = "getPC32DBLEncoding";
479 let DecoderMethod = "decodePC32DBLOperand";
482 //===----------------------------------------------------------------------===//
484 //===----------------------------------------------------------------------===//
486 // 12-bit displacement operands.
487 def disp12imm32 : Operand<i32>;
488 def disp12imm64 : Operand<i64>;
490 // 20-bit displacement operands.
491 def disp20imm32 : Operand<i32>;
492 def disp20imm64 : Operand<i64>;
494 def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">;
495 def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">;
496 def BDAddr64Disp12 : AddressAsmOperand<"BDAddr", "64", "12">;
497 def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">;
498 def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">;
499 def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">;
500 def BDLAddr64Disp12Len8 : AddressAsmOperand<"BDLAddr", "64", "12", "Len8">;
501 def BDVAddr64Disp12 : AddressAsmOperand<"BDVAddr", "64", "12">;
503 // DAG patterns and operands for addressing modes. Each mode has
504 // the form <type><range><group>[<len>] where:
507 // shift : base + displacement (32-bit)
508 // bdaddr : base + displacement
509 // mviaddr : like bdaddr, but reject cases with a natural index
510 // bdxaddr : base + displacement + index
511 // laaddr : like bdxaddr, but used for Load Address operations
512 // dynalloc : base + displacement + index + ADJDYNALLOC
513 // bdladdr : base + displacement with a length field
514 // bdvaddr : base + displacement with a vector index
516 // <range> is one of:
517 // 12 : the displacement is an unsigned 12-bit value
518 // 20 : the displacement is a signed 20-bit value
520 // <group> is one of:
521 // pair : used when there is an equivalent instruction with the opposite
522 // range value (12 or 20)
523 // only : used when there is no equivalent instruction with the opposite
528 // <empty> : there is no length field
529 // len8 : the length field is 8 bits, with a range of [1, 0x100].
530 def shift12only : BDMode <"BDAddr", "32", "12", "Only">;
531 def shift20only : BDMode <"BDAddr", "32", "20", "Only">;
532 def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">;
533 def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">;
534 def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">;
535 def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">;
536 def mviaddr12pair : BDMode <"MVIAddr", "64", "12", "Pair">;
537 def mviaddr20pair : BDMode <"MVIAddr", "64", "20", "Pair">;
538 def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">;
539 def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">;
540 def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">;
541 def bdxaddr20only128 : BDXMode<"BDXAddr", "64", "20", "Only128">;
542 def bdxaddr20pair : BDXMode<"BDXAddr", "64", "20", "Pair">;
543 def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">;
544 def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">;
545 def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">;
546 def bdladdr12onlylen8 : BDLMode<"BDLAddr", "64", "12", "Only", "8">;
547 def bdvaddr12only : BDVMode< "64", "12">;
549 //===----------------------------------------------------------------------===//
551 //===----------------------------------------------------------------------===//
553 // Access registers. At present we just use them for accessing the thread
554 // pointer, so we don't expose them as register to LLVM.
555 def AccessReg : AsmOperandClass {
556 let Name = "AccessReg";
557 let ParserMethod = "parseAccessReg";
559 def access_reg : Immediate<i32, [{ return N->getZExtValue() < 16; }],
560 NOOP_SDNodeXForm, "AccessReg"> {
561 let ParserMatchClass = AccessReg;
564 // A 4-bit condition-code mask.
565 def cond4 : PatLeaf<(i32 imm), [{ return (N->getZExtValue() < 16); }]>,
567 let PrintMethod = "printCond4Operand";