1 //===-- SystemZOperators.td - SystemZ-specific operators ------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>]>;
14 def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>,
16 def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
17 def SDT_ZCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
18 def SDT_ZBRCCMask : SDTypeProfile<0, 2,
20 SDTCisVT<1, OtherVT>]>;
21 def SDT_ZSelectCCMask : SDTypeProfile<1, 3,
25 def SDT_ZWrapPtr : SDTypeProfile<1, 1,
28 def SDT_ZAdjDynAlloc : SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
29 def SDT_ZExtractAccess : SDTypeProfile<1, 1,
32 def SDT_ZGR128Binary32 : SDTypeProfile<1, 2,
33 [SDTCisVT<0, untyped>,
36 def SDT_ZGR128Binary64 : SDTypeProfile<1, 2,
37 [SDTCisVT<0, untyped>,
40 def SDT_ZAtomicLoadBinaryW : SDTypeProfile<1, 5,
47 def SDT_ZAtomicCmpSwapW : SDTypeProfile<1, 6,
56 //===----------------------------------------------------------------------===//
58 //===----------------------------------------------------------------------===//
60 // These are target-independent nodes, but have target-specific formats.
61 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
62 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
63 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
64 [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue,
67 // Nodes for SystemZISD::*. See SystemZISelLowering.h for more details.
68 def z_retflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
69 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
70 def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall,
71 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
73 def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>;
74 def z_cmp : SDNode<"SystemZISD::CMP", SDT_ZCmp, [SDNPOutGlue]>;
75 def z_ucmp : SDNode<"SystemZISD::UCMP", SDT_ZCmp, [SDNPOutGlue]>;
76 def z_br_ccmask : SDNode<"SystemZISD::BR_CCMASK", SDT_ZBRCCMask,
77 [SDNPHasChain, SDNPInGlue]>;
78 def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask,
80 def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>;
81 def z_extract_access : SDNode<"SystemZISD::EXTRACT_ACCESS",
83 def z_umul_lohi64 : SDNode<"SystemZISD::UMUL_LOHI64", SDT_ZGR128Binary64>;
84 def z_sdivrem64 : SDNode<"SystemZISD::SDIVREM64", SDT_ZGR128Binary64>;
85 def z_udivrem32 : SDNode<"SystemZISD::UDIVREM32", SDT_ZGR128Binary32>;
86 def z_udivrem64 : SDNode<"SystemZISD::UDIVREM64", SDT_ZGR128Binary64>;
88 class AtomicWOp<string name, SDTypeProfile profile = SDT_ZAtomicLoadBinaryW>
89 : SDNode<"SystemZISD::"##name, profile,
90 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
92 def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">;
93 def z_atomic_loadw_add : AtomicWOp<"ATOMIC_LOADW_ADD">;
94 def z_atomic_loadw_sub : AtomicWOp<"ATOMIC_LOADW_SUB">;
95 def z_atomic_loadw_and : AtomicWOp<"ATOMIC_LOADW_AND">;
96 def z_atomic_loadw_or : AtomicWOp<"ATOMIC_LOADW_OR">;
97 def z_atomic_loadw_xor : AtomicWOp<"ATOMIC_LOADW_XOR">;
98 def z_atomic_loadw_nand : AtomicWOp<"ATOMIC_LOADW_NAND">;
99 def z_atomic_loadw_min : AtomicWOp<"ATOMIC_LOADW_MIN">;
100 def z_atomic_loadw_max : AtomicWOp<"ATOMIC_LOADW_MAX">;
101 def z_atomic_loadw_umin : AtomicWOp<"ATOMIC_LOADW_UMIN">;
102 def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">;
103 def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>;
105 //===----------------------------------------------------------------------===//
107 //===----------------------------------------------------------------------===//
109 // Register sign-extend operations. Sub-32-bit values are represented as i32s.
110 def sext8 : PatFrag<(ops node:$src), (sext_inreg node:$src, i8)>;
111 def sext16 : PatFrag<(ops node:$src), (sext_inreg node:$src, i16)>;
112 def sext32 : PatFrag<(ops node:$src), (sext (i32 node:$src))>;
114 // Register zero-extend operations. Sub-32-bit values are represented as i32s.
115 def zext8 : PatFrag<(ops node:$src), (and node:$src, 0xff)>;
116 def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>;
117 def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>;
119 // Typed floating-point loads.
120 def loadf32 : PatFrag<(ops node:$src), (f32 (load node:$src))>;
121 def loadf64 : PatFrag<(ops node:$src), (f64 (load node:$src))>;
124 class AlignedLoad<SDPatternOperator load>
125 : PatFrag<(ops node:$addr), (load node:$addr), [{
126 LoadSDNode *Load = cast<LoadSDNode>(N);
127 return Load->getAlignment() >= Load->getMemoryVT().getStoreSize();
129 def aligned_load : AlignedLoad<load>;
130 def aligned_sextloadi16 : AlignedLoad<sextloadi16>;
131 def aligned_sextloadi32 : AlignedLoad<sextloadi32>;
132 def aligned_zextloadi16 : AlignedLoad<zextloadi16>;
133 def aligned_zextloadi32 : AlignedLoad<zextloadi32>;
136 class AlignedStore<SDPatternOperator store>
137 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
138 StoreSDNode *Store = cast<StoreSDNode>(N);
139 return Store->getAlignment() >= Store->getMemoryVT().getStoreSize();
141 def aligned_store : AlignedStore<store>;
142 def aligned_truncstorei16 : AlignedStore<truncstorei16>;
143 def aligned_truncstorei32 : AlignedStore<truncstorei32>;
145 // Non-volatile loads. Used for instructions that might access the storage
146 // location multiple times.
147 class NonvolatileLoad<SDPatternOperator load>
148 : PatFrag<(ops node:$addr), (load node:$addr), [{
149 LoadSDNode *Load = cast<LoadSDNode>(N);
150 return !Load->isVolatile();
152 def nonvolatile_load : NonvolatileLoad<load>;
154 // Non-volatile stores.
155 class NonvolatileStore<SDPatternOperator store>
156 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
157 StoreSDNode *Store = cast<StoreSDNode>(N);
158 return !Store->isVolatile();
160 def nonvolatile_store : NonvolatileStore<store>;
163 def inserti8 : PatFrag<(ops node:$src1, node:$src2),
164 (or (and node:$src1, -256), node:$src2)>;
165 def insertll : PatFrag<(ops node:$src1, node:$src2),
166 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>;
167 def insertlh : PatFrag<(ops node:$src1, node:$src2),
168 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>;
169 def inserthl : PatFrag<(ops node:$src1, node:$src2),
170 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>;
171 def inserthh : PatFrag<(ops node:$src1, node:$src2),
172 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>;
173 def insertlf : PatFrag<(ops node:$src1, node:$src2),
174 (or (and node:$src1, 0xffffffff00000000), node:$src2)>;
175 def inserthf : PatFrag<(ops node:$src1, node:$src2),
176 (or (and node:$src1, 0x00000000ffffffff), node:$src2)>;
178 // ORs that can be treated as insertions.
179 def or_as_inserti8 : PatFrag<(ops node:$src1, node:$src2),
180 (or node:$src1, node:$src2), [{
181 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
182 return CurDAG->MaskedValueIsZero(N->getOperand(0),
183 APInt::getLowBitsSet(BitWidth, 8));
186 // ORs that can be treated as reversed insertions.
187 def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2),
188 (or node:$src1, node:$src2), [{
189 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
190 return CurDAG->MaskedValueIsZero(N->getOperand(1),
191 APInt::getLowBitsSet(BitWidth, 8));
194 // Fused multiply-add and multiply-subtract, but with the order of the
195 // operands matching SystemZ's MA and MS instructions.
196 def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
197 (fma node:$src2, node:$src3, node:$src1)>;
198 def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
199 (fma node:$src2, node:$src3, (fneg node:$src1))>;
201 // Floating-point negative absolute.
202 def fnabs : PatFrag<(ops node:$ptr), (fneg (fabs node:$ptr))>;
204 // Create a unary operator that loads from memory and then performs
205 // the given operation on it.
206 class loadu<SDPatternOperator operator, SDPatternOperator load = load>
207 : PatFrag<(ops node:$addr), (operator (load node:$addr))>;
209 // Create a store operator that performs the given unary operation
210 // on the value before storing it.
211 class storeu<SDPatternOperator operator, SDPatternOperator store = store>
212 : PatFrag<(ops node:$value, node:$addr),
213 (store (operator node:$value), node:$addr)>;