1 //===-- SystemZOperators.td - SystemZ-specific operators ------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
13 def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i64>]>;
14 def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i64>,
16 def SDT_ZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
17 def SDT_ZCmp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
18 def SDT_ZBRCCMask : SDTypeProfile<0, 3,
21 SDTCisVT<2, OtherVT>]>;
22 def SDT_ZSelectCCMask : SDTypeProfile<1, 4,
27 def SDT_ZWrapPtr : SDTypeProfile<1, 1,
30 def SDT_ZAdjDynAlloc : SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
31 def SDT_ZExtractAccess : SDTypeProfile<1, 1,
34 def SDT_ZGR128Binary32 : SDTypeProfile<1, 2,
35 [SDTCisVT<0, untyped>,
38 def SDT_ZGR128Binary64 : SDTypeProfile<1, 2,
39 [SDTCisVT<0, untyped>,
42 def SDT_ZAtomicLoadBinaryW : SDTypeProfile<1, 5,
49 def SDT_ZAtomicCmpSwapW : SDTypeProfile<1, 6,
57 def SDT_ZMemMemLength : SDTypeProfile<0, 3,
61 def SDT_ZMemMemLoop : SDTypeProfile<0, 4,
66 def SDT_ZString : SDTypeProfile<1, 3,
71 def SDT_ZI32Intrinsic : SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>;
72 def SDT_ZPrefetch : SDTypeProfile<0, 2,
76 //===----------------------------------------------------------------------===//
78 //===----------------------------------------------------------------------===//
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue,
87 // Nodes for SystemZISD::*. See SystemZISelLowering.h for more details.
88 def z_retflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
89 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
90 def z_call : SDNode<"SystemZISD::CALL", SDT_ZCall,
91 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
93 def z_sibcall : SDNode<"SystemZISD::SIBCALL", SDT_ZCall,
94 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
96 def z_pcrel_wrapper : SDNode<"SystemZISD::PCREL_WRAPPER", SDT_ZWrapPtr, []>;
97 def z_cmp : SDNode<"SystemZISD::CMP", SDT_ZCmp, [SDNPOutGlue]>;
98 def z_ucmp : SDNode<"SystemZISD::UCMP", SDT_ZCmp, [SDNPOutGlue]>;
99 def z_tm : SDNode<"SystemZISD::TM", SDT_ZCmp, [SDNPOutGlue]>;
100 def z_br_ccmask : SDNode<"SystemZISD::BR_CCMASK", SDT_ZBRCCMask,
101 [SDNPHasChain, SDNPInGlue]>;
102 def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask,
104 def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>;
105 def z_extract_access : SDNode<"SystemZISD::EXTRACT_ACCESS",
107 def z_umul_lohi64 : SDNode<"SystemZISD::UMUL_LOHI64", SDT_ZGR128Binary64>;
108 def z_sdivrem32 : SDNode<"SystemZISD::SDIVREM32", SDT_ZGR128Binary32>;
109 def z_sdivrem64 : SDNode<"SystemZISD::SDIVREM64", SDT_ZGR128Binary64>;
110 def z_udivrem32 : SDNode<"SystemZISD::UDIVREM32", SDT_ZGR128Binary32>;
111 def z_udivrem64 : SDNode<"SystemZISD::UDIVREM64", SDT_ZGR128Binary64>;
113 class AtomicWOp<string name, SDTypeProfile profile = SDT_ZAtomicLoadBinaryW>
114 : SDNode<"SystemZISD::"##name, profile,
115 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
117 def z_atomic_swapw : AtomicWOp<"ATOMIC_SWAPW">;
118 def z_atomic_loadw_add : AtomicWOp<"ATOMIC_LOADW_ADD">;
119 def z_atomic_loadw_sub : AtomicWOp<"ATOMIC_LOADW_SUB">;
120 def z_atomic_loadw_and : AtomicWOp<"ATOMIC_LOADW_AND">;
121 def z_atomic_loadw_or : AtomicWOp<"ATOMIC_LOADW_OR">;
122 def z_atomic_loadw_xor : AtomicWOp<"ATOMIC_LOADW_XOR">;
123 def z_atomic_loadw_nand : AtomicWOp<"ATOMIC_LOADW_NAND">;
124 def z_atomic_loadw_min : AtomicWOp<"ATOMIC_LOADW_MIN">;
125 def z_atomic_loadw_max : AtomicWOp<"ATOMIC_LOADW_MAX">;
126 def z_atomic_loadw_umin : AtomicWOp<"ATOMIC_LOADW_UMIN">;
127 def z_atomic_loadw_umax : AtomicWOp<"ATOMIC_LOADW_UMAX">;
128 def z_atomic_cmp_swapw : AtomicWOp<"ATOMIC_CMP_SWAPW", SDT_ZAtomicCmpSwapW>;
130 def z_mvc : SDNode<"SystemZISD::MVC", SDT_ZMemMemLength,
131 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
132 def z_mvc_loop : SDNode<"SystemZISD::MVC_LOOP", SDT_ZMemMemLoop,
133 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
134 def z_nc : SDNode<"SystemZISD::NC", SDT_ZMemMemLength,
135 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
136 def z_nc_loop : SDNode<"SystemZISD::NC_LOOP", SDT_ZMemMemLoop,
137 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
138 def z_oc : SDNode<"SystemZISD::OC", SDT_ZMemMemLength,
139 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
140 def z_oc_loop : SDNode<"SystemZISD::OC_LOOP", SDT_ZMemMemLoop,
141 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
142 def z_xc : SDNode<"SystemZISD::XC", SDT_ZMemMemLength,
143 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
144 def z_xc_loop : SDNode<"SystemZISD::XC_LOOP", SDT_ZMemMemLoop,
145 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
146 def z_clc : SDNode<"SystemZISD::CLC", SDT_ZMemMemLength,
147 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
148 def z_clc_loop : SDNode<"SystemZISD::CLC_LOOP", SDT_ZMemMemLoop,
149 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
150 def z_strcmp : SDNode<"SystemZISD::STRCMP", SDT_ZString,
151 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
152 def z_stpcpy : SDNode<"SystemZISD::STPCPY", SDT_ZString,
153 [SDNPHasChain, SDNPMayStore, SDNPMayLoad]>;
154 def z_search_string : SDNode<"SystemZISD::SEARCH_STRING", SDT_ZString,
155 [SDNPHasChain, SDNPOutGlue, SDNPMayLoad]>;
156 def z_ipm : SDNode<"SystemZISD::IPM", SDT_ZI32Intrinsic,
158 def z_prefetch : SDNode<"SystemZISD::PREFETCH", SDT_ZPrefetch,
159 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
162 //===----------------------------------------------------------------------===//
164 //===----------------------------------------------------------------------===//
166 // Register sign-extend operations. Sub-32-bit values are represented as i32s.
167 def sext8 : PatFrag<(ops node:$src), (sext_inreg node:$src, i8)>;
168 def sext16 : PatFrag<(ops node:$src), (sext_inreg node:$src, i16)>;
169 def sext32 : PatFrag<(ops node:$src), (sext (i32 node:$src))>;
171 // Register zero-extend operations. Sub-32-bit values are represented as i32s.
172 def zext8 : PatFrag<(ops node:$src), (and node:$src, 0xff)>;
173 def zext16 : PatFrag<(ops node:$src), (and node:$src, 0xffff)>;
174 def zext32 : PatFrag<(ops node:$src), (zext (i32 node:$src))>;
176 // Typed floating-point loads.
177 def loadf32 : PatFrag<(ops node:$src), (f32 (load node:$src))>;
178 def loadf64 : PatFrag<(ops node:$src), (f64 (load node:$src))>;
180 // Extending loads in which the extension type doesn't matter.
181 def anyextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
182 return cast<LoadSDNode>(N)->getExtensionType() != ISD::NON_EXTLOAD;
184 def anyextloadi8 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
185 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
187 def anyextloadi16 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
188 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
190 def anyextloadi32 : PatFrag<(ops node:$ptr), (anyextload node:$ptr), [{
191 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
195 class AlignedLoad<SDPatternOperator load>
196 : PatFrag<(ops node:$addr), (load node:$addr), [{
197 LoadSDNode *Load = cast<LoadSDNode>(N);
198 return Load->getAlignment() >= Load->getMemoryVT().getStoreSize();
200 def aligned_load : AlignedLoad<load>;
201 def aligned_sextloadi16 : AlignedLoad<sextloadi16>;
202 def aligned_sextloadi32 : AlignedLoad<sextloadi32>;
203 def aligned_zextloadi16 : AlignedLoad<zextloadi16>;
204 def aligned_zextloadi32 : AlignedLoad<zextloadi32>;
207 class AlignedStore<SDPatternOperator store>
208 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
209 StoreSDNode *Store = cast<StoreSDNode>(N);
210 return Store->getAlignment() >= Store->getMemoryVT().getStoreSize();
212 def aligned_store : AlignedStore<store>;
213 def aligned_truncstorei16 : AlignedStore<truncstorei16>;
214 def aligned_truncstorei32 : AlignedStore<truncstorei32>;
216 // Non-volatile loads. Used for instructions that might access the storage
217 // location multiple times.
218 class NonvolatileLoad<SDPatternOperator load>
219 : PatFrag<(ops node:$addr), (load node:$addr), [{
220 LoadSDNode *Load = cast<LoadSDNode>(N);
221 return !Load->isVolatile();
223 def nonvolatile_load : NonvolatileLoad<load>;
224 def nonvolatile_anyextloadi8 : NonvolatileLoad<anyextloadi8>;
225 def nonvolatile_anyextloadi16 : NonvolatileLoad<anyextloadi16>;
226 def nonvolatile_anyextloadi32 : NonvolatileLoad<anyextloadi32>;
228 // Non-volatile stores.
229 class NonvolatileStore<SDPatternOperator store>
230 : PatFrag<(ops node:$src, node:$addr), (store node:$src, node:$addr), [{
231 StoreSDNode *Store = cast<StoreSDNode>(N);
232 return !Store->isVolatile();
234 def nonvolatile_store : NonvolatileStore<store>;
235 def nonvolatile_truncstorei8 : NonvolatileStore<truncstorei8>;
236 def nonvolatile_truncstorei16 : NonvolatileStore<truncstorei16>;
237 def nonvolatile_truncstorei32 : NonvolatileStore<truncstorei32>;
239 // A store of a load that can be implemented using MVC.
240 def mvc_store : PatFrag<(ops node:$value, node:$addr),
241 (unindexedstore node:$value, node:$addr),
242 [{ return storeLoadCanUseMVC(N); }]>;
244 // Binary read-modify-write operations on memory in which the other
245 // operand is also memory and for which block operations like NC can
246 // be used. There are two patterns for each operator, depending on
247 // which operand contains the "other" load.
248 multiclass block_op<SDPatternOperator operator> {
249 def "1" : PatFrag<(ops node:$value, node:$addr),
250 (unindexedstore (operator node:$value,
251 (unindexedload node:$addr)),
253 [{ return storeLoadCanUseBlockBinary(N, 0); }]>;
254 def "2" : PatFrag<(ops node:$value, node:$addr),
255 (unindexedstore (operator (unindexedload node:$addr),
258 [{ return storeLoadCanUseBlockBinary(N, 1); }]>;
260 defm block_and : block_op<and>;
261 defm block_or : block_op<or>;
262 defm block_xor : block_op<xor>;
265 def inserti8 : PatFrag<(ops node:$src1, node:$src2),
266 (or (and node:$src1, -256), node:$src2)>;
267 def insertll : PatFrag<(ops node:$src1, node:$src2),
268 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>;
269 def insertlh : PatFrag<(ops node:$src1, node:$src2),
270 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>;
271 def inserthl : PatFrag<(ops node:$src1, node:$src2),
272 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>;
273 def inserthh : PatFrag<(ops node:$src1, node:$src2),
274 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>;
275 def insertlf : PatFrag<(ops node:$src1, node:$src2),
276 (or (and node:$src1, 0xffffffff00000000), node:$src2)>;
277 def inserthf : PatFrag<(ops node:$src1, node:$src2),
278 (or (and node:$src1, 0x00000000ffffffff), node:$src2)>;
280 // ORs that can be treated as insertions.
281 def or_as_inserti8 : PatFrag<(ops node:$src1, node:$src2),
282 (or node:$src1, node:$src2), [{
283 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
284 return CurDAG->MaskedValueIsZero(N->getOperand(0),
285 APInt::getLowBitsSet(BitWidth, 8));
288 // ORs that can be treated as reversed insertions.
289 def or_as_revinserti8 : PatFrag<(ops node:$src1, node:$src2),
290 (or node:$src1, node:$src2), [{
291 unsigned BitWidth = N->getValueType(0).getScalarType().getSizeInBits();
292 return CurDAG->MaskedValueIsZero(N->getOperand(1),
293 APInt::getLowBitsSet(BitWidth, 8));
296 // Integer absolute, matching the canonical form generated by DAGCombiner.
297 def z_iabs32 : PatFrag<(ops node:$src),
298 (xor (add node:$src, (sra node:$src, (i32 31))),
299 (sra node:$src, (i32 31)))>;
300 def z_iabs64 : PatFrag<(ops node:$src),
301 (xor (add node:$src, (sra node:$src, (i32 63))),
302 (sra node:$src, (i32 63)))>;
303 def z_inegabs32 : PatFrag<(ops node:$src), (ineg (z_iabs32 node:$src))>;
304 def z_inegabs64 : PatFrag<(ops node:$src), (ineg (z_iabs64 node:$src))>;
306 // Fused multiply-add and multiply-subtract, but with the order of the
307 // operands matching SystemZ's MA and MS instructions.
308 def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3),
309 (fma node:$src2, node:$src3, node:$src1)>;
310 def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3),
311 (fma node:$src2, node:$src3, (fneg node:$src1))>;
313 // Floating-point negative absolute.
314 def fnabs : PatFrag<(ops node:$ptr), (fneg (fabs node:$ptr))>;
316 // Create a unary operator that loads from memory and then performs
317 // the given operation on it.
318 class loadu<SDPatternOperator operator, SDPatternOperator load = load>
319 : PatFrag<(ops node:$addr), (operator (load node:$addr))>;
321 // Create a store operator that performs the given unary operation
322 // on the value before storing it.
323 class storeu<SDPatternOperator operator, SDPatternOperator store = store>
324 : PatFrag<(ops node:$value, node:$addr),
325 (store (operator node:$value), node:$addr)>;