1 //===-- SystemZPatterns.td - SystemZ-specific pattern rules ---*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Record that INSN performs a 64-bit version of unary operator OPERATOR
11 // in which the operand is sign-extended from 32 to 64 bits.
12 multiclass SXU<SDPatternOperator operator, Instruction insn> {
13 def : Pat<(operator (sext (i32 GR32:$src))),
15 def : Pat<(operator (sext_inreg GR64:$src, i32)),
16 (insn (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
19 // Record that INSN performs a 64-bit version of binary operator OPERATOR
20 // in which the first operand has class CLS and which the second operand
21 // is sign-extended from a 32-bit register.
22 multiclass SXB<SDPatternOperator operator, RegisterOperand cls,
24 def : Pat<(operator cls:$src1, (sext GR32:$src2)),
25 (insn cls:$src1, GR32:$src2)>;
26 def : Pat<(operator cls:$src1, (sext_inreg GR64:$src2, i32)),
27 (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_32bit))>;
30 // Like SXB, but for zero extension.
31 multiclass ZXB<SDPatternOperator operator, RegisterOperand cls,
33 def : Pat<(operator cls:$src1, (zext GR32:$src2)),
34 (insn cls:$src1, GR32:$src2)>;
35 def : Pat<(operator cls:$src1, (and GR64:$src2, 0xffffffff)),
36 (insn cls:$src1, (EXTRACT_SUBREG GR64:$src2, subreg_32bit))>;
39 // Record that INSN performs a binary read-modify-write operation,
40 // with LOAD, OPERATOR and STORE being the read, modify and write
41 // respectively. MODE is the addressing mode and IMM is the type
42 // of the second operand.
43 class RMWI<SDPatternOperator load, SDPatternOperator operator,
44 SDPatternOperator store, AddressingMode mode,
45 PatFrag imm, Instruction insn>
46 : Pat<(store (operator (load mode:$addr), imm:$src), mode:$addr),
47 (insn mode:$addr, (UIMM8 imm:$src))>;
49 // Record that INSN performs binary operation OPERATION on a byte
50 // memory location. IMM is the type of the second operand.
51 multiclass RMWIByte<SDPatternOperator operator, AddressingMode mode,
53 def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm32, insn>;
54 def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm64, insn>;
57 // Record that INSN performs insertion TYPE into a register of class CLS.
58 // The inserted operand is loaded using LOAD from an address of mode MODE.
59 multiclass InsertMem<string type, Instruction insn, RegisterOperand cls,
60 SDPatternOperator load, AddressingMode mode> {
61 def : Pat<(!cast<SDPatternOperator>("or_as_"##type)
62 cls:$src1, (load mode:$src2)),
63 (insn cls:$src1, mode:$src2)>;
64 def : Pat<(!cast<SDPatternOperator>("or_as_rev"##type)
65 (load mode:$src2), cls:$src1),
66 (insn cls:$src1, mode:$src2)>;
69 // Use MVC instruction INSN for a load of type LOAD followed by a store
70 // of type STORE. VT is the type of the intermediate register and LENGTH
71 // is the number of bytes to copy (which may be smaller than VT).
72 multiclass MVCLoadStore<SDPatternOperator load, SDPatternOperator store,
73 ValueType vt, Instruction insn, bits<5> length> {
74 def Pat : PatFrag<(ops node:$dest, node:$src),
75 (store (vt (load node:$src)), node:$dest),
76 [{ return storeLoadCanUseMVC(N); }]>;
78 def : Pat<(!cast<SDPatternOperator>(NAME##"Pat") bdaddr12only:$dest,
80 (insn bdaddr12only:$dest, bdaddr12only:$src, length)>;