1 //===- SystemZRegisterInfo.cpp - SystemZ Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SystemZInstrInfo.h"
16 #include "SystemZMachineFunctionInfo.h"
17 #include "SystemZRegisterInfo.h"
18 #include "SystemZSubtarget.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetFrameInfo.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/ADT/BitVector.h"
30 SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
31 const SystemZInstrInfo &tii)
32 : SystemZGenRegisterInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
37 SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
38 static const unsigned CalleeSavedRegs[] = {
39 SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D,
40 SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D,
41 SystemZ::R14D, SystemZ::R15D,
42 SystemZ::F1, SystemZ::F3, SystemZ::F5, SystemZ::F7,
46 return CalleeSavedRegs;
49 const TargetRegisterClass* const*
50 SystemZRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
51 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
52 &SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
53 &SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
54 &SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
55 &SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
56 &SystemZ::GR64RegClass, &SystemZ::GR64RegClass,
57 &SystemZ::FP64RegClass, &SystemZ::FP64RegClass,
58 &SystemZ::FP64RegClass, &SystemZ::FP64RegClass, 0
60 return CalleeSavedRegClasses;
63 BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
64 BitVector Reserved(getNumRegs());
66 Reserved.set(SystemZ::R11D);
67 Reserved.set(SystemZ::R14D);
68 Reserved.set(SystemZ::R15D);
72 /// needsFP - Return true if the specified function should have a dedicated
73 /// frame pointer register. This is true if the function has variable sized
74 /// allocas or if frame pointer elimination is disabled.
75 bool SystemZRegisterInfo::hasFP(const MachineFunction &MF) const {
76 const MachineFrameInfo *MFI = MF.getFrameInfo();
77 return NoFramePointerElim || MFI->hasVarSizedObjects();
80 void SystemZRegisterInfo::
81 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
82 MachineBasicBlock::iterator I) const {
86 int SystemZRegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const {
87 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
88 MachineFrameInfo *MFI = MF.getFrameInfo();
89 SystemZMachineFunctionInfo *SystemZMFI =
90 MF.getInfo<SystemZMachineFunctionInfo>();
91 int Offset = MFI->getObjectOffset(FI) + MFI->getOffsetAdjustment();
92 uint64_t StackSize = MFI->getStackSize();
94 // Fixed objects are really located in the "previous" frame.
96 StackSize -= SystemZMFI->getCalleeSavedFrameSize();
98 Offset += StackSize - TFI.getOffsetOfLocalArea();
100 // Skip the register save area if we generated the stack frame.
102 Offset -= TFI.getOffsetOfLocalArea();
107 void SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
108 int SPAdj, RegScavenger *RS) const {
109 assert(SPAdj == 0 && "Unxpected");
112 MachineInstr &MI = *II;
113 MachineFunction &MF = *MI.getParent()->getParent();
114 while (!MI.getOperand(i).isFI()) {
116 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
119 int FrameIndex = MI.getOperand(i).getIndex();
121 unsigned BasePtr = (hasFP(MF) ? SystemZ::R11D : SystemZ::R15D);
123 // This must be part of a rri or ri operand memory reference. Replace the
124 // FrameIndex with base register with BasePtr. Add an offset to the
125 // displacement field.
126 MI.getOperand(i).ChangeToRegister(BasePtr, false);
128 // Offset is a either 12-bit unsigned or 20-bit signed integer.
129 // FIXME: handle "too long" displacements.
130 int Offset = getFrameIndexOffset(MF, FrameIndex) + MI.getOperand(i+1).getImm();
132 // Check whether displacement is too long to fit into 12 bit zext field.
133 if (Offset < 0 || Offset >= 4096)
134 MI.setDesc(TII.getLongDispOpc(MI.getOpcode()));
136 MI.getOperand(i+1).ChangeToImmediate(Offset);
140 SystemZRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
141 RegScavenger *RS) const {
142 // Determine whether R15/R14 will ever be clobbered inside the function. And
143 // if yes - mark it as 'callee' saved.
144 MachineFrameInfo *FFI = MF.getFrameInfo();
147 /* FIXME: function is varargs */
148 /* FIXME: function grabs RA */
149 /* FIXME: function calls eh_return */
150 MF.getRegInfo().setPhysRegUsed(SystemZ::R14D);
152 if (FFI->hasCalls() ||
153 FFI->getObjectIndexEnd() != 0 || // Contains automatic variables
154 FFI->hasVarSizedObjects() // Function calls dynamic alloca's
155 /* FIXME: function is varargs */)
156 MF.getRegInfo().setPhysRegUsed(SystemZ::R15D);
159 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
160 /// stack pointer by a constant value.
162 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
163 int64_t NumBytes, const TargetInstrInfo &TII) {
164 // FIXME: Handle different stack sizes here.
165 bool isSub = NumBytes < 0;
166 uint64_t Offset = isSub ? -NumBytes : NumBytes;
167 unsigned Opc = SystemZ::ADD64ri16;
168 uint64_t Chunk = (1LL << 15) - 1;
169 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
170 DebugLoc::getUnknownLoc());
173 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
175 BuildMI(MBB, MBBI, DL, TII.get(Opc), SystemZ::R15D)
176 .addReg(SystemZ::R15D).addImm((isSub ? -(int64_t)ThisVal : ThisVal));
177 // The PSW implicit def is dead.
178 MI->getOperand(3).setIsDead();
183 void SystemZRegisterInfo::emitPrologue(MachineFunction &MF) const {
184 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
185 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
186 MachineFrameInfo *MFI = MF.getFrameInfo();
187 SystemZMachineFunctionInfo *SystemZMFI =
188 MF.getInfo<SystemZMachineFunctionInfo>();
189 MachineBasicBlock::iterator MBBI = MBB.begin();
190 DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() :
191 DebugLoc::getUnknownLoc());
193 // Get the number of bytes to allocate from the FrameInfo.
194 // Note that area for callee-saved stuff is already allocated, thus we need to
195 // 'undo' the stack movement.
196 uint64_t StackSize = MFI->getStackSize();
197 StackSize -= SystemZMFI->getCalleeSavedFrameSize();
199 uint64_t NumBytes = StackSize - TFI.getOffsetOfLocalArea();
201 // Skip the callee-saved push instructions.
202 while (MBBI != MBB.end() &&
203 (MBBI->getOpcode() == SystemZ::MOV64mr ||
204 MBBI->getOpcode() == SystemZ::MOV64mrm))
207 if (MBBI != MBB.end())
208 DL = MBBI->getDebugLoc();
210 // adjust stack pointer: R15 -= numbytes
211 if (StackSize || MFI->hasCalls()) {
212 assert(MF.getRegInfo().isPhysRegUsed(SystemZ::R15D) &&
213 "Invalid stack frame calculation!");
214 emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, TII);
218 // Update R11 with the new base value...
219 BuildMI(MBB, MBBI, DL, TII.get(SystemZ::MOV64rr), SystemZ::R11D)
220 .addReg(SystemZ::R15D);
222 // Mark the FramePtr as live-in in every block except the entry.
223 for (MachineFunction::iterator I = next(MF.begin()), E = MF.end();
225 I->addLiveIn(SystemZ::R11D);
230 void SystemZRegisterInfo::emitEpilogue(MachineFunction &MF,
231 MachineBasicBlock &MBB) const {
232 const MachineFrameInfo *MFI = MF.getFrameInfo();
233 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
234 MachineBasicBlock::iterator MBBI = prior(MBB.end());
235 SystemZMachineFunctionInfo *SystemZMFI =
236 MF.getInfo<SystemZMachineFunctionInfo>();
237 unsigned RetOpcode = MBBI->getOpcode();
238 DebugLoc DL = MBBI->getDebugLoc();
241 case SystemZ::RET: break; // These are ok
243 assert(0 && "Can only insert epilog into returning blocks");
246 // Get the number of bytes to allocate from the FrameInfo
247 // Note that area for callee-saved stuff is already allocated, thus we need to
248 // 'undo' the stack movement.
250 MFI->getStackSize() - SystemZMFI->getCalleeSavedFrameSize();
251 uint64_t NumBytes = StackSize - TFI.getOffsetOfLocalArea();
253 // Skip the final terminator instruction.
254 while (MBBI != MBB.begin()) {
255 MachineBasicBlock::iterator PI = prior(MBBI);
257 if (!PI->getDesc().isTerminator())
261 // During callee-saved restores emission stack frame was not yet finialized
262 // (and thus - the stack size was unknown). Tune the offset having full stack
264 if (StackSize || MFI->hasCalls()) {
265 assert((MBBI->getOpcode() == SystemZ::MOV64rmm ||
266 MBBI->getOpcode() == SystemZ::MOV64rm) &&
267 "Expected to see callee-save register restore code");
268 assert(MF.getRegInfo().isPhysRegUsed(SystemZ::R15D) &&
269 "Invalid stack frame calculation!");
272 MachineInstr &MI = *MBBI;
273 while (!MI.getOperand(i).isImm()) {
275 assert(i < MI.getNumOperands() && "Unexpected restore code!");
278 MI.getOperand(i).ChangeToImmediate(NumBytes + MI.getOperand(i).getImm());
282 unsigned SystemZRegisterInfo::getRARegister() const {
283 assert(0 && "What is the return address register");
287 unsigned SystemZRegisterInfo::getFrameRegister(MachineFunction &MF) const {
288 assert(0 && "What is the frame register");
292 unsigned SystemZRegisterInfo::getEHExceptionRegister() const {
293 assert(0 && "What is the exception register");
297 unsigned SystemZRegisterInfo::getEHHandlerRegister() const {
298 assert(0 && "What is the exception handler register");
302 int SystemZRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
303 assert(0 && "What is the dwarf register number");
307 #include "SystemZGenRegisterInfo.inc"