1 //==- SystemZRegisterInfo.td - SystemZ register definitions -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class SystemZReg<string n> : Register<n> {
15 let Namespace = "SystemZ";
18 class SystemZRegWithSubregs<string n, list<Register> subregs>
19 : RegisterWithSubRegs<n, subregs> {
20 let Namespace = "SystemZ";
23 let Namespace = "SystemZ" in {
24 def subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_ll32.
25 def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32.
26 def subreg_l64 : SubRegIndex<64, 0>;
27 def subreg_h64 : SubRegIndex<64, 64>;
28 def subreg_r32 : SubRegIndex<32, 32>; // Reinterpret a wider reg as 32 bits.
29 def subreg_r64 : SubRegIndex<64, 64>; // Reinterpret a wider reg as 64 bits.
30 def subreg_hh32 : ComposedSubRegIndex<subreg_h64, subreg_h32>;
31 def subreg_hl32 : ComposedSubRegIndex<subreg_h64, subreg_l32>;
32 def subreg_hr32 : ComposedSubRegIndex<subreg_h64, subreg_r32>;
35 // Define a register class that contains values of types TYPES and an
36 // associated operand called NAME. SIZE is the size and alignment
37 // of the registers and REGLIST is the list of individual registers.
38 multiclass SystemZRegClass<string name, list<ValueType> types, int size,
40 def AsmOperand : AsmOperandClass {
42 let ParserMethod = "parse"##name;
43 let RenderMethod = "addRegOperands";
45 def Bit : RegisterClass<"SystemZ", types, size, regList> {
48 def "" : RegisterOperand<!cast<RegisterClass>(name##"Bit")> {
49 let ParserMatchClass = !cast<AsmOperandClass>(name##"AsmOperand");
53 //===----------------------------------------------------------------------===//
54 // General-purpose registers
55 //===----------------------------------------------------------------------===//
57 // Lower 32 bits of one of the 16 64-bit general-purpose registers
58 class GPR32<bits<16> num, string n> : SystemZReg<n> {
62 // One of the 16 64-bit general-purpose registers.
63 class GPR64<bits<16> num, string n, GPR32 low, GPR32 high>
64 : SystemZRegWithSubregs<n, [low, high]> {
66 let SubRegIndices = [subreg_l32, subreg_h32];
69 // 8 even-odd pairs of GPR64s.
70 class GPR128<bits<16> num, string n, GPR64 low, GPR64 high>
71 : SystemZRegWithSubregs<n, [low, high]> {
73 let SubRegIndices = [subreg_l64, subreg_h64];
76 // General-purpose registers
78 def R#I#L : GPR32<I, "r"#I>;
79 def R#I#H : GPR32<I, "r"#I>;
80 def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L"), !cast<GPR32>("R"#I#"H")>,
84 foreach I = [0, 2, 4, 6, 8, 10, 12, 14] in {
85 def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#!add(I, 1)#"D"),
86 !cast<GPR64>("R"#I#"D")>;
89 /// Allocate the callee-saved R6-R13 backwards. That way they can be saved
90 /// together with R14 and R15 in one prolog instruction.
91 defm GR32 : SystemZRegClass<"GR32", [i32], 32,
92 (add (sequence "R%uL", 0, 5),
93 (sequence "R%uL", 15, 6))>;
94 defm GRH32 : SystemZRegClass<"GRH32", [i32], 32,
95 (add (sequence "R%uH", 0, 5),
96 (sequence "R%uH", 15, 6))>;
97 defm GR64 : SystemZRegClass<"GR64", [i64], 64,
98 (add (sequence "R%uD", 0, 5),
99 (sequence "R%uD", 15, 6))>;
101 // Combine the low and high GR32s into a single class. This can only be
102 // used for virtual registers if the high-word facility is available.
103 defm GRX32 : SystemZRegClass<"GRX32", [i32], 32,
104 (add (sequence "R%uL", 0, 5),
105 (sequence "R%uH", 0, 5),
106 R15L, R15H, R14L, R14H, R13L, R13H,
107 R12L, R12H, R11L, R11H, R10L, R10H,
108 R9L, R9H, R8L, R8H, R7L, R7H, R6L, R6H)>;
110 // The architecture doesn't really have any i128 support, so model the
111 // register pairs as untyped instead.
112 defm GR128 : SystemZRegClass<"GR128", [untyped], 128,
113 (add R0Q, R2Q, R4Q, R12Q, R10Q, R8Q, R6Q, R14Q)>;
115 // Base and index registers. Everything except R0, which in an address
116 // context evaluates as 0.
117 defm ADDR32 : SystemZRegClass<"ADDR32", [i32], 32, (sub GR32Bit, R0L)>;
118 defm ADDR64 : SystemZRegClass<"ADDR64", [i64], 64, (sub GR64Bit, R0D)>;
120 // Not used directly, but needs to exist for ADDR32 and ADDR64 subregs
122 defm ADDR128 : SystemZRegClass<"ADDR128", [untyped], 128, (sub GR128Bit, R0Q)>;
124 //===----------------------------------------------------------------------===//
125 // Floating-point registers
126 //===----------------------------------------------------------------------===//
128 // Maps FPR register numbers to their DWARF encoding.
129 class DwarfMapping<int id> { int Id = id; }
131 def F0Dwarf : DwarfMapping<16>;
132 def F2Dwarf : DwarfMapping<17>;
133 def F4Dwarf : DwarfMapping<18>;
134 def F6Dwarf : DwarfMapping<19>;
136 def F1Dwarf : DwarfMapping<20>;
137 def F3Dwarf : DwarfMapping<21>;
138 def F5Dwarf : DwarfMapping<22>;
139 def F7Dwarf : DwarfMapping<23>;
141 def F8Dwarf : DwarfMapping<24>;
142 def F10Dwarf : DwarfMapping<25>;
143 def F12Dwarf : DwarfMapping<26>;
144 def F14Dwarf : DwarfMapping<27>;
146 def F9Dwarf : DwarfMapping<28>;
147 def F11Dwarf : DwarfMapping<29>;
148 def F13Dwarf : DwarfMapping<30>;
149 def F15Dwarf : DwarfMapping<31>;
151 def F16Dwarf : DwarfMapping<68>;
152 def F18Dwarf : DwarfMapping<69>;
153 def F20Dwarf : DwarfMapping<70>;
154 def F22Dwarf : DwarfMapping<71>;
156 def F17Dwarf : DwarfMapping<72>;
157 def F19Dwarf : DwarfMapping<73>;
158 def F21Dwarf : DwarfMapping<74>;
159 def F23Dwarf : DwarfMapping<75>;
161 def F24Dwarf : DwarfMapping<76>;
162 def F26Dwarf : DwarfMapping<77>;
163 def F28Dwarf : DwarfMapping<78>;
164 def F30Dwarf : DwarfMapping<79>;
166 def F25Dwarf : DwarfMapping<80>;
167 def F27Dwarf : DwarfMapping<81>;
168 def F29Dwarf : DwarfMapping<82>;
169 def F31Dwarf : DwarfMapping<83>;
171 // Upper 32 bits of one of the floating-point registers
172 class FPR32<bits<16> num, string n> : SystemZReg<n> {
173 let HWEncoding = num;
176 // One of the floating-point registers.
177 class FPR64<bits<16> num, string n, FPR32 high>
178 : SystemZRegWithSubregs<n, [high]> {
179 let HWEncoding = num;
180 let SubRegIndices = [subreg_r32];
183 // 8 pairs of FPR64s, with a one-register gap inbetween.
184 class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>
185 : SystemZRegWithSubregs<n, [low, high]> {
186 let HWEncoding = num;
187 let SubRegIndices = [subreg_l64, subreg_h64];
190 // Floating-point registers. Registers 16-31 require the vector facility.
191 foreach I = 0-15 in {
192 def F#I#S : FPR32<I, "f"#I>;
193 def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>,
194 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
196 foreach I = 16-31 in {
197 def F#I#S : FPR32<I, "v"#I>;
198 def F#I#D : FPR64<I, "v"#I, !cast<FPR32>("F"#I#"S")>,
199 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
202 foreach I = [0, 1, 4, 5, 8, 9, 12, 13] in {
203 def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"),
204 !cast<FPR64>("F"#I#"D")>;
207 // There's no store-multiple instruction for FPRs, so we're not fussy
208 // about the order in which call-saved registers are allocated.
209 defm FP32 : SystemZRegClass<"FP32", [f32], 32, (sequence "F%uS", 0, 15)>;
210 defm FP64 : SystemZRegClass<"FP64", [f64], 64, (sequence "F%uD", 0, 15)>;
211 defm FP128 : SystemZRegClass<"FP128", [f128], 128,
212 (add F0Q, F1Q, F4Q, F5Q, F8Q, F9Q, F12Q, F13Q)>;
214 //===----------------------------------------------------------------------===//
216 //===----------------------------------------------------------------------===//
218 // A full 128-bit vector register, with an FPR64 as its high part.
219 class VR128<bits<16> num, string n, FPR64 high>
220 : SystemZRegWithSubregs<n, [high]> {
221 let HWEncoding = num;
222 let SubRegIndices = [subreg_r64];
225 // Full vector registers.
226 foreach I = 0-31 in {
227 def V#I : VR128<I, "v"#I, !cast<FPR64>("F"#I#"D")>,
228 DwarfRegNum<[!cast<DwarfMapping>("F"#I#"Dwarf").Id]>;
231 // Class used to store 32-bit values in the first element of a vector
232 // register. f32 scalars are used for the WLEDB and WLDEB instructions.
233 defm VR32 : SystemZRegClass<"VR32", [f32, v4i8, v2i16], 32,
234 (add (sequence "F%uS", 0, 7),
235 (sequence "F%uS", 16, 31),
236 (sequence "F%uS", 8, 15))>;
238 // Class used to store 64-bit values in the upper half of a vector register.
239 // The vector facility also includes scalar f64 instructions that operate
240 // on the full vector register set.
241 defm VR64 : SystemZRegClass<"VR64", [f64, v8i8, v4i16, v2i32, v2f32], 64,
242 (add (sequence "F%uD", 0, 7),
243 (sequence "F%uD", 16, 31),
244 (sequence "F%uD", 8, 15))>;
246 // The subset of vector registers that can be used for floating-point
248 defm VF128 : SystemZRegClass<"VF128",
249 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
250 (sequence "V%u", 0, 15)>;
252 // All vector registers.
253 defm VR128 : SystemZRegClass<"VR128",
254 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
255 (add (sequence "V%u", 0, 7),
256 (sequence "V%u", 16, 31),
257 (sequence "V%u", 8, 15))>;
259 // Attaches a ValueType to a register operand, to make the instruction
260 // definitions easier.
261 class TypedReg<ValueType vtin, RegisterOperand opin> {
263 RegisterOperand op = opin;
266 def v32eb : TypedReg<f32, VR32>;
267 def v64g : TypedReg<i64, VR64>;
268 def v64db : TypedReg<f64, VR64>;
269 def v128b : TypedReg<v16i8, VR128>;
270 def v128h : TypedReg<v8i16, VR128>;
271 def v128f : TypedReg<v4i32, VR128>;
272 def v128g : TypedReg<v2i64, VR128>;
273 def v128q : TypedReg<v16i8, VR128>;
274 def v128eb : TypedReg<v4f32, VR128>;
275 def v128db : TypedReg<v2f64, VR128>;
276 def v128any : TypedReg<untyped, VR128>;
278 //===----------------------------------------------------------------------===//
280 //===----------------------------------------------------------------------===//
282 // The 2-bit condition code field of the PSW. Every register named in an
283 // inline asm needs a class associated with it.
284 def CC : SystemZReg<"cc">;
285 def CCRegs : RegisterClass<"SystemZ", [i32], 32, (add CC)>;