1 //===- SystemZRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 class SystemZReg<string n> : Register<n> {
14 let Namespace = "SystemZ";
17 class SystemZRegWithSubregs<string n, list<Register> subregs>
18 : RegisterWithSubRegs<n, subregs> {
19 let Namespace = "SystemZ";
22 // We identify all our registers with a 4-bit ID, for consistency's sake.
24 // GPR32 - Lower 32 bits of one of the 16 64-bit general-purpose registers
25 class GPR32<bits<4> num, string n> : SystemZReg<n> {
26 field bits<4> Num = num;
29 // GPR64 - One of the 16 64-bit general-purpose registers
30 class GPR64<bits<4> num, string n, list<Register> subregs,
31 list<Register> aliases = []>
32 : SystemZRegWithSubregs<n, subregs> {
33 field bits<4> Num = num;
34 let Aliases = aliases;
37 // GPR128 - 8 even-odd register pairs
38 class GPR128<bits<4> num, string n, list<Register> subregs,
39 list<Register> aliases = []>
40 : SystemZRegWithSubregs<n, subregs> {
41 field bits<4> Num = num;
42 let Aliases = aliases;
45 // FPRS - Lower 32 bits of one of the 16 64-bit floating-point registers
46 class FPRS<bits<4> num, string n> : SystemZReg<n> {
47 field bits<4> Num = num;
50 // FPRL - One of the 16 64-bit floating-point registers
51 class FPRL<bits<4> num, string n, list<Register> subregs>
52 : SystemZRegWithSubregs<n, subregs> {
53 field bits<4> Num = num;
56 // General-purpose registers
57 def R0W : GPR32< 0, "r0">, DwarfRegNum<[0]>;
58 def R1W : GPR32< 1, "r1">, DwarfRegNum<[1]>;
59 def R2W : GPR32< 2, "r2">, DwarfRegNum<[2]>;
60 def R3W : GPR32< 3, "r3">, DwarfRegNum<[3]>;
61 def R4W : GPR32< 4, "r4">, DwarfRegNum<[4]>;
62 def R5W : GPR32< 5, "r5">, DwarfRegNum<[5]>;
63 def R6W : GPR32< 6, "r6">, DwarfRegNum<[6]>;
64 def R7W : GPR32< 7, "r7">, DwarfRegNum<[7]>;
65 def R8W : GPR32< 8, "r8">, DwarfRegNum<[8]>;
66 def R9W : GPR32< 9, "r9">, DwarfRegNum<[9]>;
67 def R10W : GPR32<10, "r10">, DwarfRegNum<[10]>;
68 def R11W : GPR32<11, "r11">, DwarfRegNum<[11]>;
69 def R12W : GPR32<12, "r12">, DwarfRegNum<[12]>;
70 def R13W : GPR32<13, "r13">, DwarfRegNum<[13]>;
71 def R14W : GPR32<14, "r14">, DwarfRegNum<[14]>;
72 def R15W : GPR32<15, "r15">, DwarfRegNum<[15]>;
74 def R0D : GPR64< 0, "r0", [R0W]>, DwarfRegNum<[0]>;
75 def R1D : GPR64< 1, "r1", [R1W]>, DwarfRegNum<[1]>;
76 def R2D : GPR64< 2, "r2", [R2W]>, DwarfRegNum<[2]>;
77 def R3D : GPR64< 3, "r3", [R3W]>, DwarfRegNum<[3]>;
78 def R4D : GPR64< 4, "r4", [R4W]>, DwarfRegNum<[4]>;
79 def R5D : GPR64< 5, "r5", [R5W]>, DwarfRegNum<[5]>;
80 def R6D : GPR64< 6, "r6", [R6W]>, DwarfRegNum<[6]>;
81 def R7D : GPR64< 7, "r7", [R7W]>, DwarfRegNum<[7]>;
82 def R8D : GPR64< 8, "r8", [R8W]>, DwarfRegNum<[8]>;
83 def R9D : GPR64< 9, "r9", [R9W]>, DwarfRegNum<[9]>;
84 def R10D : GPR64<10, "r10", [R10W]>, DwarfRegNum<[10]>;
85 def R11D : GPR64<11, "r11", [R11W]>, DwarfRegNum<[11]>;
86 def R12D : GPR64<12, "r12", [R12W]>, DwarfRegNum<[12]>;
87 def R13D : GPR64<13, "r13", [R13W]>, DwarfRegNum<[13]>;
88 def R14D : GPR64<14, "r14", [R14W]>, DwarfRegNum<[14]>;
89 def R15D : GPR64<15, "r15", [R15W]>, DwarfRegNum<[15]>;
92 def R0P : GPR64< 0, "r0", [R0W, R1W], [R0D, R1D]>, DwarfRegNum<[0]>;
93 def R2P : GPR64< 2, "r2", [R2W, R3W], [R2D, R3D]>, DwarfRegNum<[2]>;
94 def R4P : GPR64< 4, "r4", [R4W, R5W], [R4D, R5D]>, DwarfRegNum<[4]>;
95 def R6P : GPR64< 6, "r6", [R6W, R7W], [R6D, R7D]>, DwarfRegNum<[6]>;
96 def R8P : GPR64< 8, "r8", [R8W, R9W], [R8D, R9D]>, DwarfRegNum<[8]>;
97 def R10P : GPR64<10, "r10", [R10W, R11W], [R10D, R11D]>, DwarfRegNum<[10]>;
98 def R12P : GPR64<12, "r12", [R12W, R13W], [R12D, R13D]>, DwarfRegNum<[12]>;
99 def R14P : GPR64<14, "r14", [R14W, R15W], [R14D, R15D]>, DwarfRegNum<[14]>;
101 def R0Q : GPR128< 0, "r0", [R0D, R1D], [R0P]>, DwarfRegNum<[0]>;
102 def R2Q : GPR128< 2, "r2", [R2D, R3D], [R2P]>, DwarfRegNum<[2]>;
103 def R4Q : GPR128< 4, "r4", [R4D, R5D], [R4P]>, DwarfRegNum<[4]>;
104 def R6Q : GPR128< 6, "r6", [R6D, R7D], [R6P]>, DwarfRegNum<[6]>;
105 def R8Q : GPR128< 8, "r8", [R8D, R9D], [R8P]>, DwarfRegNum<[8]>;
106 def R10Q : GPR128<10, "r10", [R10D, R11D], [R10P]>, DwarfRegNum<[10]>;
107 def R12Q : GPR128<12, "r12", [R12D, R13D], [R12P]>, DwarfRegNum<[12]>;
108 def R14Q : GPR128<14, "r14", [R14D, R15D], [R14P]>, DwarfRegNum<[14]>;
110 // Floating-point registers
111 def F0S : FPRS< 0, "f0">, DwarfRegNum<[16]>;
112 def F1S : FPRS< 1, "f1">, DwarfRegNum<[17]>;
113 def F2S : FPRS< 2, "f2">, DwarfRegNum<[18]>;
114 def F3S : FPRS< 3, "f3">, DwarfRegNum<[19]>;
115 def F4S : FPRS< 4, "f4">, DwarfRegNum<[20]>;
116 def F5S : FPRS< 5, "f5">, DwarfRegNum<[21]>;
117 def F6S : FPRS< 6, "f6">, DwarfRegNum<[22]>;
118 def F7S : FPRS< 7, "f7">, DwarfRegNum<[23]>;
119 def F8S : FPRS< 8, "f8">, DwarfRegNum<[24]>;
120 def F9S : FPRS< 9, "f9">, DwarfRegNum<[25]>;
121 def F10S : FPRS<10, "f10">, DwarfRegNum<[26]>;
122 def F11S : FPRS<11, "f11">, DwarfRegNum<[27]>;
123 def F12S : FPRS<12, "f12">, DwarfRegNum<[28]>;
124 def F13S : FPRS<13, "f13">, DwarfRegNum<[29]>;
125 def F14S : FPRS<14, "f14">, DwarfRegNum<[30]>;
126 def F15S : FPRS<15, "f15">, DwarfRegNum<[31]>;
128 def F0L : FPRL< 0, "f0", [F0S]>, DwarfRegNum<[16]>;
129 def F1L : FPRL< 1, "f1", [F1S]>, DwarfRegNum<[17]>;
130 def F2L : FPRL< 2, "f2", [F2S]>, DwarfRegNum<[18]>;
131 def F3L : FPRL< 3, "f3", [F3S]>, DwarfRegNum<[19]>;
132 def F4L : FPRL< 4, "f4", [F4S]>, DwarfRegNum<[20]>;
133 def F5L : FPRL< 5, "f5", [F5S]>, DwarfRegNum<[21]>;
134 def F6L : FPRL< 6, "f6", [F6S]>, DwarfRegNum<[22]>;
135 def F7L : FPRL< 7, "f7", [F7S]>, DwarfRegNum<[23]>;
136 def F8L : FPRL< 8, "f8", [F8S]>, DwarfRegNum<[24]>;
137 def F9L : FPRL< 9, "f9", [F9S]>, DwarfRegNum<[25]>;
138 def F10L : FPRL<10, "f10", [F10S]>, DwarfRegNum<[26]>;
139 def F11L : FPRL<11, "f11", [F11S]>, DwarfRegNum<[27]>;
140 def F12L : FPRL<12, "f12", [F12S]>, DwarfRegNum<[28]>;
141 def F13L : FPRL<13, "f13", [F13S]>, DwarfRegNum<[29]>;
142 def F14L : FPRL<14, "f14", [F14S]>, DwarfRegNum<[30]>;
143 def F15L : FPRL<15, "f15", [F15S]>, DwarfRegNum<[31]>;
146 def PSW : SystemZReg<"psw">;
148 let Namespace = "SystemZ" in {
149 def subreg_32bit : SubRegIndex;
150 def subreg_even32 : SubRegIndex;
151 def subreg_odd32 : SubRegIndex;
152 def subreg_even : SubRegIndex;
153 def subreg_odd : SubRegIndex;
156 def : SubRegSet<subreg_32bit, [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D,
157 R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
158 [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W,
159 R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
161 def : SubRegSet<subreg_even, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
162 [R0D, R2D, R4D, R6D, R8D, R10D, R12D, R14D]>;
164 def : SubRegSet<subreg_odd, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
165 [R1D, R3D, R5D, R7D, R9D, R11D, R13D, R15D]>;
167 def : SubRegSet<subreg_even32, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
168 [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>;
170 def : SubRegSet<subreg_odd32, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
171 [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>;
173 def : SubRegSet<subreg_even32, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
174 [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>;
176 def : SubRegSet<subreg_odd32, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
177 [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>;
180 def GR32 : RegisterClass<"SystemZ", [i32], 32,
181 // Volatile registers
182 [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W,
183 // Frame pointer, sometimes allocable
185 // Volatile, but not allocable
188 let MethodProtos = [{
189 iterator allocation_order_begin(const MachineFunction &MF) const;
190 iterator allocation_order_end(const MachineFunction &MF) const;
192 let MethodBodies = [{
193 static const unsigned SystemZ_REG32[] = {
194 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
195 SystemZ::R5W, SystemZ::R0W, SystemZ::R12W, SystemZ::R11W,
196 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
197 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
199 static const unsigned SystemZ_REG32_nofp[] = {
200 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
201 SystemZ::R5W, SystemZ::R0W, SystemZ::R12W, /* No R11W */
202 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
203 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
206 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
207 const TargetMachine &TM = MF.getTarget();
208 const TargetRegisterInfo *RI = TM.getRegisterInfo();
210 return SystemZ_REG32_nofp;
212 return SystemZ_REG32;
215 GR32Class::allocation_order_end(const MachineFunction &MF) const {
216 const TargetMachine &TM = MF.getTarget();
217 const TargetRegisterInfo *RI = TM.getRegisterInfo();
219 return SystemZ_REG32_nofp + (sizeof(SystemZ_REG32_nofp) / sizeof(unsigned));
221 return SystemZ_REG32 + (sizeof(SystemZ_REG32) / sizeof(unsigned));
226 /// Registers used to generate address. Everything except R0.
227 def ADDR32 : RegisterClass<"SystemZ", [i32], 32,
228 // Volatile registers
229 [R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W,
230 // Frame pointer, sometimes allocable
232 // Volatile, but not allocable
235 let MethodProtos = [{
236 iterator allocation_order_begin(const MachineFunction &MF) const;
237 iterator allocation_order_end(const MachineFunction &MF) const;
239 let MethodBodies = [{
240 static const unsigned SystemZ_ADDR32[] = {
241 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
242 SystemZ::R5W, /* No R0W */ SystemZ::R12W, SystemZ::R11W,
243 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
244 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
246 static const unsigned SystemZ_ADDR32_nofp[] = {
247 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
248 SystemZ::R5W, /* No R0W */ SystemZ::R12W, /* No R11W */
249 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
250 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
252 ADDR32Class::iterator
253 ADDR32Class::allocation_order_begin(const MachineFunction &MF) const {
254 const TargetMachine &TM = MF.getTarget();
255 const TargetRegisterInfo *RI = TM.getRegisterInfo();
257 return SystemZ_ADDR32_nofp;
259 return SystemZ_ADDR32;
261 ADDR32Class::iterator
262 ADDR32Class::allocation_order_end(const MachineFunction &MF) const {
263 const TargetMachine &TM = MF.getTarget();
264 const TargetRegisterInfo *RI = TM.getRegisterInfo();
266 return SystemZ_ADDR32_nofp + (sizeof(SystemZ_ADDR32_nofp) / sizeof(unsigned));
268 return SystemZ_ADDR32 + (sizeof(SystemZ_ADDR32) / sizeof(unsigned));
273 def GR64 : RegisterClass<"SystemZ", [i64], 64,
274 // Volatile registers
275 [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R12D, R13D,
276 // Frame pointer, sometimes allocable
278 // Volatile, but not allocable
281 let SubRegClasses = [(GR32 subreg_32bit)];
282 let MethodProtos = [{
283 iterator allocation_order_begin(const MachineFunction &MF) const;
284 iterator allocation_order_end(const MachineFunction &MF) const;
286 let MethodBodies = [{
287 static const unsigned SystemZ_REG64[] = {
288 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
289 SystemZ::R5D, SystemZ::R0D, SystemZ::R12D, SystemZ::R11D,
290 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
291 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
293 static const unsigned SystemZ_REG64_nofp[] = {
294 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
295 SystemZ::R5D, SystemZ::R0D, SystemZ::R12D, /* No R11D */
296 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
297 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
300 GR64Class::allocation_order_begin(const MachineFunction &MF) const {
301 const TargetMachine &TM = MF.getTarget();
302 const TargetRegisterInfo *RI = TM.getRegisterInfo();
304 return SystemZ_REG64_nofp;
306 return SystemZ_REG64;
309 GR64Class::allocation_order_end(const MachineFunction &MF) const {
310 const TargetMachine &TM = MF.getTarget();
311 const TargetRegisterInfo *RI = TM.getRegisterInfo();
313 return SystemZ_REG64_nofp + (sizeof(SystemZ_REG64_nofp) / sizeof(unsigned));
315 return SystemZ_REG64 + (sizeof(SystemZ_REG64) / sizeof(unsigned));
320 def ADDR64 : RegisterClass<"SystemZ", [i64], 64,
321 // Volatile registers
322 [R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R12D, R13D,
323 // Frame pointer, sometimes allocable
325 // Volatile, but not allocable
328 let SubRegClasses = [(ADDR32 subreg_32bit)];
329 let MethodProtos = [{
330 iterator allocation_order_begin(const MachineFunction &MF) const;
331 iterator allocation_order_end(const MachineFunction &MF) const;
333 let MethodBodies = [{
334 static const unsigned SystemZ_ADDR64[] = {
335 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
336 SystemZ::R5D, /* No R0D */ SystemZ::R12D, SystemZ::R11D,
337 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
338 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
340 static const unsigned SystemZ_ADDR64_nofp[] = {
341 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
342 SystemZ::R5D, /* No R0D */ SystemZ::R12D, /* No R11D */
343 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
344 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
346 ADDR64Class::iterator
347 ADDR64Class::allocation_order_begin(const MachineFunction &MF) const {
348 const TargetMachine &TM = MF.getTarget();
349 const TargetRegisterInfo *RI = TM.getRegisterInfo();
351 return SystemZ_ADDR64_nofp;
353 return SystemZ_ADDR64;
355 ADDR64Class::iterator
356 ADDR64Class::allocation_order_end(const MachineFunction &MF) const {
357 const TargetMachine &TM = MF.getTarget();
358 const TargetRegisterInfo *RI = TM.getRegisterInfo();
360 return SystemZ_ADDR64_nofp + (sizeof(SystemZ_ADDR64_nofp) / sizeof(unsigned));
362 return SystemZ_ADDR64 + (sizeof(SystemZ_ADDR64) / sizeof(unsigned));
367 // Even-odd register pairs
368 def GR64P : RegisterClass<"SystemZ", [v2i32], 64,
369 [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P]>
371 let SubRegClasses = [(GR32 subreg_even32, subreg_odd32)];
372 let MethodProtos = [{
373 iterator allocation_order_begin(const MachineFunction &MF) const;
374 iterator allocation_order_end(const MachineFunction &MF) const;
376 let MethodBodies = [{
377 static const unsigned SystemZ_REG64P[] = {
378 SystemZ::R0P, SystemZ::R2P, SystemZ::R4P, SystemZ::R10P,
379 SystemZ::R8P, SystemZ::R6P };
380 static const unsigned SystemZ_REG64P_nofp[] = {
381 SystemZ::R0P, SystemZ::R2P, SystemZ::R4P, /* NO R10P */
382 SystemZ::R8P, SystemZ::R6P };
384 GR64PClass::allocation_order_begin(const MachineFunction &MF) const {
385 const TargetMachine &TM = MF.getTarget();
386 const TargetRegisterInfo *RI = TM.getRegisterInfo();
388 return SystemZ_REG64P_nofp;
390 return SystemZ_REG64P;
393 GR64PClass::allocation_order_end(const MachineFunction &MF) const {
394 const TargetMachine &TM = MF.getTarget();
395 const TargetRegisterInfo *RI = TM.getRegisterInfo();
397 return SystemZ_REG64P_nofp + (sizeof(SystemZ_REG64P_nofp) / sizeof(unsigned));
399 return SystemZ_REG64P + (sizeof(SystemZ_REG64P) / sizeof(unsigned));
404 def GR128 : RegisterClass<"SystemZ", [v2i64], 128,
405 [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q]>
407 let SubRegClasses = [(GR32 subreg_even32, subreg_odd32),
408 (GR64 subreg_even, subreg_odd)];
409 let MethodProtos = [{
410 iterator allocation_order_begin(const MachineFunction &MF) const;
411 iterator allocation_order_end(const MachineFunction &MF) const;
413 let MethodBodies = [{
414 static const unsigned SystemZ_REG128[] = {
415 SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R10Q,
416 SystemZ::R8Q, SystemZ::R6Q };
417 static const unsigned SystemZ_REG128_nofp[] = {
418 SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, /* NO R10Q */
419 SystemZ::R8Q, SystemZ::R6Q };
421 GR128Class::allocation_order_begin(const MachineFunction &MF) const {
422 const TargetMachine &TM = MF.getTarget();
423 const TargetRegisterInfo *RI = TM.getRegisterInfo();
425 return SystemZ_REG128_nofp;
427 return SystemZ_REG128;
430 GR128Class::allocation_order_end(const MachineFunction &MF) const {
431 const TargetMachine &TM = MF.getTarget();
432 const TargetRegisterInfo *RI = TM.getRegisterInfo();
434 return SystemZ_REG128_nofp + (sizeof(SystemZ_REG128_nofp) / sizeof(unsigned));
436 return SystemZ_REG128 + (sizeof(SystemZ_REG128) / sizeof(unsigned));
441 def FP32 : RegisterClass<"SystemZ", [f32], 32,
442 [F0S, F1S, F2S, F3S, F4S, F5S, F6S, F7S,
443 F8S, F9S, F10S, F11S, F12S, F13S, F14S, F15S]> {
444 let MethodProtos = [{
445 iterator allocation_order_begin(const MachineFunction &MF) const;
446 iterator allocation_order_end(const MachineFunction &MF) const;
448 let MethodBodies = [{
449 static const unsigned SystemZ_REGFP32[] = {
450 SystemZ::F0S, SystemZ::F2S, SystemZ::F4S, SystemZ::F6S,
451 SystemZ::F1S, SystemZ::F3S, SystemZ::F5S, SystemZ::F7S,
452 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
453 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
455 FP32Class::allocation_order_begin(const MachineFunction &MF) const {
456 return SystemZ_REGFP32;
459 FP32Class::allocation_order_end(const MachineFunction &MF) const {
460 return SystemZ_REGFP32 + (sizeof(SystemZ_REGFP32) / sizeof(unsigned));
465 def FP64 : RegisterClass<"SystemZ", [f64], 64,
466 [F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L,
467 F8L, F9L, F10L, F11L, F12L, F13L, F14L, F15L]> {
468 let SubRegClasses = [(FP32 subreg_32bit)];
469 let MethodProtos = [{
470 iterator allocation_order_begin(const MachineFunction &MF) const;
471 iterator allocation_order_end(const MachineFunction &MF) const;
473 let MethodBodies = [{
474 static const unsigned SystemZ_REGFP64[] = {
475 SystemZ::F0L, SystemZ::F2L, SystemZ::F4L, SystemZ::F6L,
476 SystemZ::F1L, SystemZ::F3L, SystemZ::F5L, SystemZ::F7L,
477 SystemZ::F8L, SystemZ::F9L, SystemZ::F10L, SystemZ::F11L,
478 SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L };
480 FP64Class::allocation_order_begin(const MachineFunction &MF) const {
481 return SystemZ_REGFP64;
484 FP64Class::allocation_order_end(const MachineFunction &MF) const {
485 return SystemZ_REGFP64 + (sizeof(SystemZ_REGFP64) / sizeof(unsigned));
490 // Status flags registers.
491 def CCR : RegisterClass<"SystemZ", [i64], 64, [PSW]> {
492 let CopyCost = -1; // Don't allow copying of status registers.