1 //===- SystemZRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 class SystemZReg<string n> : Register<n> {
14 let Namespace = "SystemZ";
17 class SystemZRegWithSubregs<string n, list<Register> subregs>
18 : RegisterWithSubRegs<n, subregs> {
19 let Namespace = "SystemZ";
22 // We identify all our registers with a 4-bit ID, for consistency's sake.
24 // GPR32 - Lower 32 bits of one of the 16 64-bit general-purpose registers
25 class GPR32<bits<4> num, string n> : SystemZReg<n> {
26 field bits<4> Num = num;
29 // GPR64 - One of the 16 64-bit general-purpose registers
30 class GPR64<bits<4> num, string n, list<Register> subregs,
31 list<Register> aliases = []>
32 : SystemZRegWithSubregs<n, subregs> {
33 field bits<4> Num = num;
34 let Aliases = aliases;
37 // GPR128 - 8 even-odd register pairs
38 class GPR128<bits<4> num, string n, list<Register> subregs,
39 list<Register> aliases = []>
40 : SystemZRegWithSubregs<n, subregs> {
41 field bits<4> Num = num;
42 let Aliases = aliases;
45 // FPRS - Lower 32 bits of one of the 16 64-bit floating-point registers
46 class FPRS<bits<4> num, string n> : SystemZReg<n> {
47 field bits<4> Num = num;
50 // FPRL - One of the 16 64-bit floating-point registers
51 class FPRL<bits<4> num, string n, list<Register> subregs>
52 : SystemZRegWithSubregs<n, subregs> {
53 field bits<4> Num = num;
56 let Namespace = "SystemZ" in {
57 def subreg_32bit : SubRegIndex;
58 def subreg_even32 : SubRegIndex;
59 def subreg_odd32 : SubRegIndex;
60 def subreg_even : SubRegIndex;
61 def subreg_odd : SubRegIndex;
64 // General-purpose registers
65 def R0W : GPR32< 0, "r0">, DwarfRegNum<[0]>;
66 def R1W : GPR32< 1, "r1">, DwarfRegNum<[1]>;
67 def R2W : GPR32< 2, "r2">, DwarfRegNum<[2]>;
68 def R3W : GPR32< 3, "r3">, DwarfRegNum<[3]>;
69 def R4W : GPR32< 4, "r4">, DwarfRegNum<[4]>;
70 def R5W : GPR32< 5, "r5">, DwarfRegNum<[5]>;
71 def R6W : GPR32< 6, "r6">, DwarfRegNum<[6]>;
72 def R7W : GPR32< 7, "r7">, DwarfRegNum<[7]>;
73 def R8W : GPR32< 8, "r8">, DwarfRegNum<[8]>;
74 def R9W : GPR32< 9, "r9">, DwarfRegNum<[9]>;
75 def R10W : GPR32<10, "r10">, DwarfRegNum<[10]>;
76 def R11W : GPR32<11, "r11">, DwarfRegNum<[11]>;
77 def R12W : GPR32<12, "r12">, DwarfRegNum<[12]>;
78 def R13W : GPR32<13, "r13">, DwarfRegNum<[13]>;
79 def R14W : GPR32<14, "r14">, DwarfRegNum<[14]>;
80 def R15W : GPR32<15, "r15">, DwarfRegNum<[15]>;
82 let SubRegIndices = [subreg_32bit] in {
83 def R0D : GPR64< 0, "r0", [R0W]>, DwarfRegNum<[0]>;
84 def R1D : GPR64< 1, "r1", [R1W]>, DwarfRegNum<[1]>;
85 def R2D : GPR64< 2, "r2", [R2W]>, DwarfRegNum<[2]>;
86 def R3D : GPR64< 3, "r3", [R3W]>, DwarfRegNum<[3]>;
87 def R4D : GPR64< 4, "r4", [R4W]>, DwarfRegNum<[4]>;
88 def R5D : GPR64< 5, "r5", [R5W]>, DwarfRegNum<[5]>;
89 def R6D : GPR64< 6, "r6", [R6W]>, DwarfRegNum<[6]>;
90 def R7D : GPR64< 7, "r7", [R7W]>, DwarfRegNum<[7]>;
91 def R8D : GPR64< 8, "r8", [R8W]>, DwarfRegNum<[8]>;
92 def R9D : GPR64< 9, "r9", [R9W]>, DwarfRegNum<[9]>;
93 def R10D : GPR64<10, "r10", [R10W]>, DwarfRegNum<[10]>;
94 def R11D : GPR64<11, "r11", [R11W]>, DwarfRegNum<[11]>;
95 def R12D : GPR64<12, "r12", [R12W]>, DwarfRegNum<[12]>;
96 def R13D : GPR64<13, "r13", [R13W]>, DwarfRegNum<[13]>;
97 def R14D : GPR64<14, "r14", [R14W]>, DwarfRegNum<[14]>;
98 def R15D : GPR64<15, "r15", [R15W]>, DwarfRegNum<[15]>;
102 let SubRegIndices = [subreg_even32, subreg_odd32] in {
103 def R0P : GPR64< 0, "r0", [R0W, R1W], [R0D, R1D]>, DwarfRegNum<[0]>;
104 def R2P : GPR64< 2, "r2", [R2W, R3W], [R2D, R3D]>, DwarfRegNum<[2]>;
105 def R4P : GPR64< 4, "r4", [R4W, R5W], [R4D, R5D]>, DwarfRegNum<[4]>;
106 def R6P : GPR64< 6, "r6", [R6W, R7W], [R6D, R7D]>, DwarfRegNum<[6]>;
107 def R8P : GPR64< 8, "r8", [R8W, R9W], [R8D, R9D]>, DwarfRegNum<[8]>;
108 def R10P : GPR64<10, "r10", [R10W, R11W], [R10D, R11D]>, DwarfRegNum<[10]>;
109 def R12P : GPR64<12, "r12", [R12W, R13W], [R12D, R13D]>, DwarfRegNum<[12]>;
110 def R14P : GPR64<14, "r14", [R14W, R15W], [R14D, R15D]>, DwarfRegNum<[14]>;
113 let SubRegIndices = [subreg_even, subreg_odd],
114 CompositeIndices = [(subreg_even32 subreg_even, subreg_32bit),
115 (subreg_odd32 subreg_odd, subreg_32bit)] in {
116 def R0Q : GPR128< 0, "r0", [R0D, R1D], [R0P]>, DwarfRegNum<[0]>;
117 def R2Q : GPR128< 2, "r2", [R2D, R3D], [R2P]>, DwarfRegNum<[2]>;
118 def R4Q : GPR128< 4, "r4", [R4D, R5D], [R4P]>, DwarfRegNum<[4]>;
119 def R6Q : GPR128< 6, "r6", [R6D, R7D], [R6P]>, DwarfRegNum<[6]>;
120 def R8Q : GPR128< 8, "r8", [R8D, R9D], [R8P]>, DwarfRegNum<[8]>;
121 def R10Q : GPR128<10, "r10", [R10D, R11D], [R10P]>, DwarfRegNum<[10]>;
122 def R12Q : GPR128<12, "r12", [R12D, R13D], [R12P]>, DwarfRegNum<[12]>;
123 def R14Q : GPR128<14, "r14", [R14D, R15D], [R14P]>, DwarfRegNum<[14]>;
126 // Floating-point registers
127 def F0S : FPRS< 0, "f0">, DwarfRegNum<[16]>;
128 def F1S : FPRS< 1, "f1">, DwarfRegNum<[17]>;
129 def F2S : FPRS< 2, "f2">, DwarfRegNum<[18]>;
130 def F3S : FPRS< 3, "f3">, DwarfRegNum<[19]>;
131 def F4S : FPRS< 4, "f4">, DwarfRegNum<[20]>;
132 def F5S : FPRS< 5, "f5">, DwarfRegNum<[21]>;
133 def F6S : FPRS< 6, "f6">, DwarfRegNum<[22]>;
134 def F7S : FPRS< 7, "f7">, DwarfRegNum<[23]>;
135 def F8S : FPRS< 8, "f8">, DwarfRegNum<[24]>;
136 def F9S : FPRS< 9, "f9">, DwarfRegNum<[25]>;
137 def F10S : FPRS<10, "f10">, DwarfRegNum<[26]>;
138 def F11S : FPRS<11, "f11">, DwarfRegNum<[27]>;
139 def F12S : FPRS<12, "f12">, DwarfRegNum<[28]>;
140 def F13S : FPRS<13, "f13">, DwarfRegNum<[29]>;
141 def F14S : FPRS<14, "f14">, DwarfRegNum<[30]>;
142 def F15S : FPRS<15, "f15">, DwarfRegNum<[31]>;
144 let SubRegIndices = [subreg_32bit] in {
145 def F0L : FPRL< 0, "f0", [F0S]>, DwarfRegNum<[16]>;
146 def F1L : FPRL< 1, "f1", [F1S]>, DwarfRegNum<[17]>;
147 def F2L : FPRL< 2, "f2", [F2S]>, DwarfRegNum<[18]>;
148 def F3L : FPRL< 3, "f3", [F3S]>, DwarfRegNum<[19]>;
149 def F4L : FPRL< 4, "f4", [F4S]>, DwarfRegNum<[20]>;
150 def F5L : FPRL< 5, "f5", [F5S]>, DwarfRegNum<[21]>;
151 def F6L : FPRL< 6, "f6", [F6S]>, DwarfRegNum<[22]>;
152 def F7L : FPRL< 7, "f7", [F7S]>, DwarfRegNum<[23]>;
153 def F8L : FPRL< 8, "f8", [F8S]>, DwarfRegNum<[24]>;
154 def F9L : FPRL< 9, "f9", [F9S]>, DwarfRegNum<[25]>;
155 def F10L : FPRL<10, "f10", [F10S]>, DwarfRegNum<[26]>;
156 def F11L : FPRL<11, "f11", [F11S]>, DwarfRegNum<[27]>;
157 def F12L : FPRL<12, "f12", [F12S]>, DwarfRegNum<[28]>;
158 def F13L : FPRL<13, "f13", [F13S]>, DwarfRegNum<[29]>;
159 def F14L : FPRL<14, "f14", [F14S]>, DwarfRegNum<[30]>;
160 def F15L : FPRL<15, "f15", [F15S]>, DwarfRegNum<[31]>;
164 def PSW : SystemZReg<"psw">;
167 def GR32 : RegisterClass<"SystemZ", [i32], 32,
168 // Volatile registers
169 [R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W,
170 // Frame pointer, sometimes allocable
172 // Volatile, but not allocable
175 let MethodProtos = [{
176 iterator allocation_order_begin(const MachineFunction &MF) const;
177 iterator allocation_order_end(const MachineFunction &MF) const;
179 let MethodBodies = [{
180 static const unsigned SystemZ_REG32[] = {
181 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
182 SystemZ::R5W, SystemZ::R0W, SystemZ::R12W, SystemZ::R11W,
183 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
184 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
186 static const unsigned SystemZ_REG32_nofp[] = {
187 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
188 SystemZ::R5W, SystemZ::R0W, SystemZ::R12W, /* No R11W */
189 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
190 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
193 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
194 const TargetMachine &TM = MF.getTarget();
195 const TargetRegisterInfo *RI = TM.getRegisterInfo();
197 return SystemZ_REG32_nofp;
199 return SystemZ_REG32;
202 GR32Class::allocation_order_end(const MachineFunction &MF) const {
203 const TargetMachine &TM = MF.getTarget();
204 const TargetRegisterInfo *RI = TM.getRegisterInfo();
206 return SystemZ_REG32_nofp + (sizeof(SystemZ_REG32_nofp) / sizeof(unsigned));
208 return SystemZ_REG32 + (sizeof(SystemZ_REG32) / sizeof(unsigned));
213 /// Registers used to generate address. Everything except R0.
214 def ADDR32 : RegisterClass<"SystemZ", [i32], 32,
215 // Volatile registers
216 [R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W,
217 // Frame pointer, sometimes allocable
219 // Volatile, but not allocable
222 let MethodProtos = [{
223 iterator allocation_order_begin(const MachineFunction &MF) const;
224 iterator allocation_order_end(const MachineFunction &MF) const;
226 let MethodBodies = [{
227 static const unsigned SystemZ_ADDR32[] = {
228 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
229 SystemZ::R5W, /* No R0W */ SystemZ::R12W, SystemZ::R11W,
230 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
231 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
233 static const unsigned SystemZ_ADDR32_nofp[] = {
234 SystemZ::R1W, SystemZ::R2W, SystemZ::R3W, SystemZ::R4W,
235 SystemZ::R5W, /* No R0W */ SystemZ::R12W, /* No R11W */
236 SystemZ::R10W, SystemZ::R9W, SystemZ::R8W, SystemZ::R7W,
237 SystemZ::R6W, SystemZ::R14W, SystemZ::R13W
239 ADDR32Class::iterator
240 ADDR32Class::allocation_order_begin(const MachineFunction &MF) const {
241 const TargetMachine &TM = MF.getTarget();
242 const TargetRegisterInfo *RI = TM.getRegisterInfo();
244 return SystemZ_ADDR32_nofp;
246 return SystemZ_ADDR32;
248 ADDR32Class::iterator
249 ADDR32Class::allocation_order_end(const MachineFunction &MF) const {
250 const TargetMachine &TM = MF.getTarget();
251 const TargetRegisterInfo *RI = TM.getRegisterInfo();
253 return SystemZ_ADDR32_nofp + (sizeof(SystemZ_ADDR32_nofp) / sizeof(unsigned));
255 return SystemZ_ADDR32 + (sizeof(SystemZ_ADDR32) / sizeof(unsigned));
260 def GR64 : RegisterClass<"SystemZ", [i64], 64,
261 // Volatile registers
262 [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R12D, R13D,
263 // Frame pointer, sometimes allocable
265 // Volatile, but not allocable
268 let SubRegClasses = [(GR32 subreg_32bit)];
269 let MethodProtos = [{
270 iterator allocation_order_begin(const MachineFunction &MF) const;
271 iterator allocation_order_end(const MachineFunction &MF) const;
273 let MethodBodies = [{
274 static const unsigned SystemZ_REG64[] = {
275 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
276 SystemZ::R5D, SystemZ::R0D, SystemZ::R12D, SystemZ::R11D,
277 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
278 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
280 static const unsigned SystemZ_REG64_nofp[] = {
281 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
282 SystemZ::R5D, SystemZ::R0D, SystemZ::R12D, /* No R11D */
283 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
284 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
287 GR64Class::allocation_order_begin(const MachineFunction &MF) const {
288 const TargetMachine &TM = MF.getTarget();
289 const TargetRegisterInfo *RI = TM.getRegisterInfo();
291 return SystemZ_REG64_nofp;
293 return SystemZ_REG64;
296 GR64Class::allocation_order_end(const MachineFunction &MF) const {
297 const TargetMachine &TM = MF.getTarget();
298 const TargetRegisterInfo *RI = TM.getRegisterInfo();
300 return SystemZ_REG64_nofp + (sizeof(SystemZ_REG64_nofp) / sizeof(unsigned));
302 return SystemZ_REG64 + (sizeof(SystemZ_REG64) / sizeof(unsigned));
307 def ADDR64 : RegisterClass<"SystemZ", [i64], 64,
308 // Volatile registers
309 [R1D, R2D, R3D, R4D, R5D, R6D, R7D, R8D, R9D, R10D, R12D, R13D,
310 // Frame pointer, sometimes allocable
312 // Volatile, but not allocable
315 let SubRegClasses = [(ADDR32 subreg_32bit)];
316 let MethodProtos = [{
317 iterator allocation_order_begin(const MachineFunction &MF) const;
318 iterator allocation_order_end(const MachineFunction &MF) const;
320 let MethodBodies = [{
321 static const unsigned SystemZ_ADDR64[] = {
322 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
323 SystemZ::R5D, /* No R0D */ SystemZ::R12D, SystemZ::R11D,
324 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
325 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
327 static const unsigned SystemZ_ADDR64_nofp[] = {
328 SystemZ::R1D, SystemZ::R2D, SystemZ::R3D, SystemZ::R4D,
329 SystemZ::R5D, /* No R0D */ SystemZ::R12D, /* No R11D */
330 SystemZ::R10D, SystemZ::R9D, SystemZ::R8D, SystemZ::R7D,
331 SystemZ::R6D, SystemZ::R14D, SystemZ::R13D
333 ADDR64Class::iterator
334 ADDR64Class::allocation_order_begin(const MachineFunction &MF) const {
335 const TargetMachine &TM = MF.getTarget();
336 const TargetRegisterInfo *RI = TM.getRegisterInfo();
338 return SystemZ_ADDR64_nofp;
340 return SystemZ_ADDR64;
342 ADDR64Class::iterator
343 ADDR64Class::allocation_order_end(const MachineFunction &MF) const {
344 const TargetMachine &TM = MF.getTarget();
345 const TargetRegisterInfo *RI = TM.getRegisterInfo();
347 return SystemZ_ADDR64_nofp + (sizeof(SystemZ_ADDR64_nofp) / sizeof(unsigned));
349 return SystemZ_ADDR64 + (sizeof(SystemZ_ADDR64) / sizeof(unsigned));
354 // Even-odd register pairs
355 def GR64P : RegisterClass<"SystemZ", [v2i32], 64,
356 [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P]>
358 let SubRegClasses = [(GR32 subreg_even32, subreg_odd32)];
359 let MethodProtos = [{
360 iterator allocation_order_begin(const MachineFunction &MF) const;
361 iterator allocation_order_end(const MachineFunction &MF) const;
363 let MethodBodies = [{
364 static const unsigned SystemZ_REG64P[] = {
365 SystemZ::R0P, SystemZ::R2P, SystemZ::R4P, SystemZ::R10P,
366 SystemZ::R8P, SystemZ::R6P };
367 static const unsigned SystemZ_REG64P_nofp[] = {
368 SystemZ::R0P, SystemZ::R2P, SystemZ::R4P, /* NO R10P */
369 SystemZ::R8P, SystemZ::R6P };
371 GR64PClass::allocation_order_begin(const MachineFunction &MF) const {
372 const TargetMachine &TM = MF.getTarget();
373 const TargetRegisterInfo *RI = TM.getRegisterInfo();
375 return SystemZ_REG64P_nofp;
377 return SystemZ_REG64P;
380 GR64PClass::allocation_order_end(const MachineFunction &MF) const {
381 const TargetMachine &TM = MF.getTarget();
382 const TargetRegisterInfo *RI = TM.getRegisterInfo();
384 return SystemZ_REG64P_nofp + (sizeof(SystemZ_REG64P_nofp) / sizeof(unsigned));
386 return SystemZ_REG64P + (sizeof(SystemZ_REG64P) / sizeof(unsigned));
391 def GR128 : RegisterClass<"SystemZ", [v2i64], 128,
392 [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q]>
394 let SubRegClasses = [(GR32 subreg_even32, subreg_odd32),
395 (GR64 subreg_even, subreg_odd)];
396 let MethodProtos = [{
397 iterator allocation_order_begin(const MachineFunction &MF) const;
398 iterator allocation_order_end(const MachineFunction &MF) const;
400 let MethodBodies = [{
401 static const unsigned SystemZ_REG128[] = {
402 SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, SystemZ::R10Q,
403 SystemZ::R8Q, SystemZ::R6Q };
404 static const unsigned SystemZ_REG128_nofp[] = {
405 SystemZ::R0Q, SystemZ::R2Q, SystemZ::R4Q, /* NO R10Q */
406 SystemZ::R8Q, SystemZ::R6Q };
408 GR128Class::allocation_order_begin(const MachineFunction &MF) const {
409 const TargetMachine &TM = MF.getTarget();
410 const TargetRegisterInfo *RI = TM.getRegisterInfo();
412 return SystemZ_REG128_nofp;
414 return SystemZ_REG128;
417 GR128Class::allocation_order_end(const MachineFunction &MF) const {
418 const TargetMachine &TM = MF.getTarget();
419 const TargetRegisterInfo *RI = TM.getRegisterInfo();
421 return SystemZ_REG128_nofp + (sizeof(SystemZ_REG128_nofp) / sizeof(unsigned));
423 return SystemZ_REG128 + (sizeof(SystemZ_REG128) / sizeof(unsigned));
428 def FP32 : RegisterClass<"SystemZ", [f32], 32,
429 [F0S, F1S, F2S, F3S, F4S, F5S, F6S, F7S,
430 F8S, F9S, F10S, F11S, F12S, F13S, F14S, F15S]> {
431 let MethodProtos = [{
432 iterator allocation_order_begin(const MachineFunction &MF) const;
433 iterator allocation_order_end(const MachineFunction &MF) const;
435 let MethodBodies = [{
436 static const unsigned SystemZ_REGFP32[] = {
437 SystemZ::F0S, SystemZ::F2S, SystemZ::F4S, SystemZ::F6S,
438 SystemZ::F1S, SystemZ::F3S, SystemZ::F5S, SystemZ::F7S,
439 SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
440 SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S };
442 FP32Class::allocation_order_begin(const MachineFunction &MF) const {
443 return SystemZ_REGFP32;
446 FP32Class::allocation_order_end(const MachineFunction &MF) const {
447 return SystemZ_REGFP32 + (sizeof(SystemZ_REGFP32) / sizeof(unsigned));
452 def FP64 : RegisterClass<"SystemZ", [f64], 64,
453 [F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L,
454 F8L, F9L, F10L, F11L, F12L, F13L, F14L, F15L]> {
455 let SubRegClasses = [(FP32 subreg_32bit)];
456 let MethodProtos = [{
457 iterator allocation_order_begin(const MachineFunction &MF) const;
458 iterator allocation_order_end(const MachineFunction &MF) const;
460 let MethodBodies = [{
461 static const unsigned SystemZ_REGFP64[] = {
462 SystemZ::F0L, SystemZ::F2L, SystemZ::F4L, SystemZ::F6L,
463 SystemZ::F1L, SystemZ::F3L, SystemZ::F5L, SystemZ::F7L,
464 SystemZ::F8L, SystemZ::F9L, SystemZ::F10L, SystemZ::F11L,
465 SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L };
467 FP64Class::allocation_order_begin(const MachineFunction &MF) const {
468 return SystemZ_REGFP64;
471 FP64Class::allocation_order_end(const MachineFunction &MF) const {
472 return SystemZ_REGFP64 + (sizeof(SystemZ_REGFP64) / sizeof(unsigned));
477 // Status flags registers.
478 def CCR : RegisterClass<"SystemZ", [i64], 64, [PSW]> {
479 let CopyCost = -1; // Don't allow copying of status registers.