1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // Register - You should define one instance of this class for each register
25 // in the target machine. String n will become the "name" of the register.
26 class Register<string n> {
27 string Namespace = "";
30 // SpillSize - If this value is set to a non-zero value, it is the size in
31 // bits of the spill slot required to hold this register. If this value is
32 // set to zero, the information is inferred from any register classes the
33 // register belongs to.
36 // SpillAlignment - This value is used to specify the alignment required for
37 // spilling the register. Like SpillSize, this should only be explicitly
38 // specified if the register is not in a register class.
39 int SpillAlignment = 0;
41 // Aliases - A list of registers that this register overlaps with. A read or
42 // modification of this register can potentially read or modifie the aliased
45 list<Register> Aliases = [];
47 // DwarfNumber - Number used internally by gcc/gdb to identify the register.
48 // These values can be determined by locating the <target>.h file in the
49 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
50 // order of these names correspond to the enumeration used by gcc. A value of
51 // -1 indicates that the gcc number is undefined.
55 // RegisterGroup - This can be used to define instances of Register which
56 // need to specify aliases.
57 // List "aliases" specifies which registers are aliased to this one. This
58 // allows the code generator to be careful not to put two values with
59 // overlapping live ranges into registers which alias.
60 class RegisterGroup<string n, list<Register> aliases> : Register<n> {
61 let Aliases = aliases;
64 // RegisterClass - Now that all of the registers are defined, and aliases
65 // between registers are defined, specify which registers belong to which
66 // register classes. This also defines the default allocation order of
67 // registers by register allocators.
69 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
70 list<Register> regList> {
71 string Namespace = namespace;
73 // RegType - Specify the list ValueType of the registers in this register
74 // class. Note that all registers in a register class must have the same
75 // ValueTypes. This is a list because some targets permit storing different
76 // types in same register, for example vector values with 128-bit total size,
77 // but different count/size of items, like SSE on x86.
79 list<ValueType> RegTypes = regTypes;
81 // Size - Specify the spill size in bits of the registers. A default value of
82 // zero lets tablgen pick an appropriate size.
85 // Alignment - Specify the alignment required of the registers when they are
86 // stored or loaded to memory.
88 int Alignment = alignment;
90 // MemberList - Specify which registers are in this class. If the
91 // allocation_order_* method are not specified, this also defines the order of
92 // allocation used by the register allocator.
94 list<Register> MemberList = regList;
96 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
97 // code into a generated register class. The normal usage of this is to
98 // overload virtual methods.
99 code MethodProtos = [{}];
100 code MethodBodies = [{}];
104 //===----------------------------------------------------------------------===//
105 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
106 // to the register numbering used by gcc and gdb. These values are used by a
107 // debug information writer (ex. DwarfWriter) to describe where values may be
108 // located during execution.
109 class DwarfRegNum<int N> {
110 // DwarfNumber - Number used internally by gcc/gdb to identify the register.
111 // These values can be determined by locating the <target>.h file in the
112 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
113 // order of these names correspond to the enumeration used by gcc. A value of
114 // -1 indicates that the gcc number is undefined.
118 //===----------------------------------------------------------------------===//
119 // Pull in the common support for scheduling
121 include "TargetSchedule.td"
123 class Predicate; // Forward def
125 //===----------------------------------------------------------------------===//
126 // Instruction set description - These classes correspond to the C++ classes in
127 // the Target/TargetInstrInfo.h file.
130 string Name = ""; // The opcode string for this instruction
131 string Namespace = "";
133 dag OperandList; // An dag containing the MI operand list.
134 string AsmString = ""; // The .s format to print the instruction with.
136 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
137 // otherwise, uninitialized.
140 // The follow state will eventually be inferred automatically from the
141 // instruction pattern.
143 list<Register> Uses = []; // Default to using no non-operand registers
144 list<Register> Defs = []; // Default to modifying no non-operand registers
146 // Predicates - List of predicates which will be turned into isel matching
148 list<Predicate> Predicates = [];
150 // Added complexity passed onto matching pattern.
151 int AddedComplexity = 0;
153 // These bits capture information about the high-level semantics of the
155 bit isReturn = 0; // Is this instruction a return instruction?
156 bit isBranch = 0; // Is this instruction a branch instruction?
157 bit isBarrier = 0; // Can control flow fall through this instruction?
158 bit isCall = 0; // Is this instruction a call instruction?
159 bit isLoad = 0; // Is this instruction a load instruction?
160 bit isStore = 0; // Is this instruction a store instruction?
161 bit isTwoAddress = 0; // Is this a two address instruction?
162 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
163 bit isCommutable = 0; // Is this 3 operand instruction commutable?
164 bit isTerminator = 0; // Is this part of the terminator for a basic block?
165 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
166 bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
167 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
168 bit noResults = 0; // Does this instruction produce no results?
170 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
173 /// Predicates - These are extra conditionals which are turned into instruction
174 /// selector matching code. Currently each predicate is just a string.
175 class Predicate<string cond> {
176 string CondString = cond;
179 class Requires<list<Predicate> preds> {
180 list<Predicate> Predicates = preds;
183 /// ops definition - This is just a simple marker used to identify the operands
184 /// list for an instruction. This should be used like this:
185 /// (ops R32:$dst, R32:$src) or something similar.
188 /// variable_ops definition - Mark this instruction as taking a variable number
192 /// Operand Types - These provide the built-in operand types that may be used
193 /// by a target. Targets can optionally provide their own operand types as
194 /// needed, though this should not be needed for RISC targets.
195 class Operand<ValueType ty> {
197 string PrintMethod = "printOperand";
198 int NumMIOperands = 1;
199 dag MIOperandInfo = (ops);
202 def i1imm : Operand<i1>;
203 def i8imm : Operand<i8>;
204 def i16imm : Operand<i16>;
205 def i32imm : Operand<i32>;
206 def i64imm : Operand<i64>;
208 // InstrInfo - This class should only be instantiated once to provide parameters
209 // which are global to the the target machine.
212 // If the target wants to associate some target-specific information with each
213 // instruction, it should provide these two lists to indicate how to assemble
214 // the target specific information into the 32 bits available.
216 list<string> TSFlagsFields = [];
217 list<int> TSFlagsShifts = [];
219 // Target can specify its instructions in either big or little-endian formats.
220 // For instance, while both Sparc and PowerPC are big-endian platforms, the
221 // Sparc manual specifies its instructions in the format [31..0] (big), while
222 // PowerPC specifies them using the format [0..31] (little).
223 bit isLittleEndianEncoding = 0;
226 // Standard Instructions.
227 def PHI : Instruction {
228 let OperandList = (ops variable_ops);
229 let AsmString = "PHINODE";
230 let Namespace = "TargetInstrInfo";
232 def INLINEASM : Instruction {
233 let OperandList = (ops variable_ops);
235 let Namespace = "TargetInstrInfo";
238 //===----------------------------------------------------------------------===//
239 // AsmWriter - This class can be implemented by targets that need to customize
240 // the format of the .s file writer.
242 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
243 // on X86 for example).
246 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
247 // class. Generated AsmWriter classes are always prefixed with the target
249 string AsmWriterClassName = "AsmPrinter";
251 // InstFormatName - AsmWriters can specify the name of the format string to
252 // print instructions with.
253 string InstFormatName = "AsmString";
255 // Variant - AsmWriters can be of multiple different variants. Variants are
256 // used to support targets that need to emit assembly code in ways that are
257 // mostly the same for different targets, but have minor differences in
258 // syntax. If the asmstring contains {|} characters in them, this integer
259 // will specify which alternative to use. For example "{x|y|z}" with Variant
260 // == 1, will expand to "y".
263 def DefaultAsmWriter : AsmWriter;
266 //===----------------------------------------------------------------------===//
267 // Target - This class contains the "global" target information
270 // CalleeSavedRegisters - As you might guess, this is a list of the callee
271 // saved registers for a target.
272 list<Register> CalleeSavedRegisters = [];
274 // InstructionSet - Instruction set description for this target.
275 InstrInfo InstructionSet;
277 // AssemblyWriters - The AsmWriter instances available for this target.
278 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
281 //===----------------------------------------------------------------------===//
282 // SubtargetFeature - A characteristic of the chip set.
284 class SubtargetFeature<string n, string a, string v, string d> {
285 // Name - Feature name. Used by command line (-mattr=) to determine the
286 // appropriate target chip.
290 // Attribute - Attribute to be set by feature.
292 string Attribute = a;
294 // Value - Value the attribute to be set to by feature.
298 // Desc - Feature description. Used by command line (-mattr=) to display help
304 //===----------------------------------------------------------------------===//
305 // Processor chip sets - These values represent each of the chip sets supported
306 // by the scheduler. Each Processor definition requires corresponding
307 // instruction itineraries.
309 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
310 // Name - Chip set name. Used by command line (-mcpu=) to determine the
311 // appropriate target chip.
315 // ProcItin - The scheduling information for the target processor.
317 ProcessorItineraries ProcItin = pi;
319 // Features - list of
320 list<SubtargetFeature> Features = f;
323 //===----------------------------------------------------------------------===//
324 // Pull in the common support for DAG isel generation
326 include "TargetSelectionDAG.td"