1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 // Value types - These values correspond to the register types defined in the
19 // ValueTypes.h file. If you update anything here, you must update it there as
22 class ValueType<int size, int value> {
23 string Namespace = "MVT";
28 def OtherVT: ValueType<0 , 0>; // "Other" value
29 def i1 : ValueType<1 , 1>; // One bit boolean value
30 def i8 : ValueType<8 , 2>; // 8-bit integer value
31 def i16 : ValueType<16 , 3>; // 16-bit integer value
32 def i32 : ValueType<32 , 4>; // 32-bit integer value
33 def i64 : ValueType<64 , 5>; // 64-bit integer value
34 def i128 : ValueType<128, 5>; // 128-bit integer value
35 def f32 : ValueType<32 , 7>; // 32-bit floating point value
36 def f64 : ValueType<64 , 8>; // 64-bit floating point value
37 def f80 : ValueType<80 , 9>; // 80-bit floating point value
38 def f128 : ValueType<128, 10>; // 128-bit floating point value
39 def FlagVT : ValueType<0 , 11>; // Condition code or machine flag
40 def isVoid : ValueType<0 , 12>; // Produces no value
42 //===----------------------------------------------------------------------===//
43 // Register file description - These classes are used to fill in the target
44 // description classes.
46 class RegisterClass; // Forward def
48 // Register - You should define one instance of this class for each register
49 // in the target machine. String n will become the "name" of the register.
50 class Register<string n> {
51 string Namespace = "";
54 // SpillSize - If this value is set to a non-zero value, it is the size in
55 // bits of the spill slot required to hold this register. If this value is
56 // set to zero, the information is inferred from any register classes the
57 // register belongs to.
60 // SpillAlignment - This value is used to specify the alignment required for
61 // spilling the register. Like SpillSize, this should only be explicitly
62 // specified if the register is not in a register class.
63 int SpillAlignment = 0;
65 // Aliases - A list of registers that this register overlaps with. A read or
66 // modification of this register can potentially read or modifie the aliased
69 list<Register> Aliases = [];
72 // RegisterGroup - This can be used to define instances of Register which
73 // need to specify aliases.
74 // List "aliases" specifies which registers are aliased to this one. This
75 // allows the code generator to be careful not to put two values with
76 // overlapping live ranges into registers which alias.
77 class RegisterGroup<string n, list<Register> aliases> : Register<n> {
78 let Aliases = aliases;
81 // RegisterClass - Now that all of the registers are defined, and aliases
82 // between registers are defined, specify which registers belong to which
83 // register classes. This also defines the default allocation order of
84 // registers by register allocators.
86 class RegisterClass<string namespace, ValueType regType, int alignment,
87 list<Register> regList> {
88 string Namespace = namespace;
90 // RegType - Specify the ValueType of the registers in this register class.
91 // Note that all registers in a register class must have the same ValueType.
93 ValueType RegType = regType;
95 // Alignment - Specify the alignment required of the registers when they are
96 // stored or loaded to memory.
98 int Size = RegType.Size;
99 int Alignment = alignment;
101 // MemberList - Specify which registers are in this class. If the
102 // allocation_order_* method are not specified, this also defines the order of
103 // allocation used by the register allocator.
105 list<Register> MemberList = regList;
107 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
108 // code into a generated register class. The normal usage of this is to
109 // overload virtual methods.
110 code MethodProtos = [{}];
111 code MethodBodies = [{}];
115 //===----------------------------------------------------------------------===//
116 // Pull in the common support for scheduling
118 include "../TargetSchedule.td"
121 //===----------------------------------------------------------------------===//
122 // Instruction set description - These classes correspond to the C++ classes in
123 // the Target/TargetInstrInfo.h file.
126 string Name = ""; // The opcode string for this instruction
127 string Namespace = "";
129 dag OperandList; // An dag containing the MI operand list.
130 string AsmString = ""; // The .s format to print the instruction with.
132 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
133 // otherwise, uninitialized.
136 // The follow state will eventually be inferred automatically from the
137 // instruction pattern.
139 list<Register> Uses = []; // Default to using no non-operand registers
140 list<Register> Defs = []; // Default to modifying no non-operand registers
142 // These bits capture information about the high-level semantics of the
144 bit isReturn = 0; // Is this instruction a return instruction?
145 bit isBranch = 0; // Is this instruction a branch instruction?
146 bit isBarrier = 0; // Can control flow fall through this instruction?
147 bit isCall = 0; // Is this instruction a call instruction?
148 bit isLoad = 0; // Is this instruction a load instruction?
149 bit isStore = 0; // Is this instruction a store instruction?
150 bit isTwoAddress = 0; // Is this a two address instruction?
151 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
152 bit isCommutable = 0; // Is this 3 operand instruction commutable?
153 bit isTerminator = 0; // Is this part of the terminator for a basic block?
154 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
155 bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
157 InstrItinClass Itinerary; // Execution steps used for scheduling.
161 /// ops definition - This is just a simple marker used to identify the operands
162 /// list for an instruction. This should be used like this:
163 /// (ops R32:$dst, R32:$src) or something similar.
166 /// variable_ops definition - Mark this instruction as taking a variable number
170 /// Operand Types - These provide the built-in operand types that may be used
171 /// by a target. Targets can optionally provide their own operand types as
172 /// needed, though this should not be needed for RISC targets.
173 class Operand<ValueType ty> {
174 int NumMIOperands = 1;
176 string PrintMethod = "printOperand";
179 def i1imm : Operand<i1>;
180 def i8imm : Operand<i8>;
181 def i16imm : Operand<i16>;
182 def i32imm : Operand<i32>;
183 def i64imm : Operand<i64>;
185 // InstrInfo - This class should only be instantiated once to provide parameters
186 // which are global to the the target machine.
191 // If the target wants to associate some target-specific information with each
192 // instruction, it should provide these two lists to indicate how to assemble
193 // the target specific information into the 32 bits available.
195 list<string> TSFlagsFields = [];
196 list<int> TSFlagsShifts = [];
198 // Target can specify its instructions in either big or little-endian formats.
199 // For instance, while both Sparc and PowerPC are big-endian platforms, the
200 // Sparc manual specifies its instructions in the format [31..0] (big), while
201 // PowerPC specifies them using the format [0..31] (little).
202 bit isLittleEndianEncoding = 0;
205 //===----------------------------------------------------------------------===//
206 // AsmWriter - This class can be implemented by targets that need to customize
207 // the format of the .s file writer.
209 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
210 // on X86 for example).
213 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
214 // class. Generated AsmWriter classes are always prefixed with the target
216 string AsmWriterClassName = "AsmPrinter";
218 // InstFormatName - AsmWriters can specify the name of the format string to
219 // print instructions with.
220 string InstFormatName = "AsmString";
222 // Variant - AsmWriters can be of multiple different variants. Variants are
223 // used to support targets that need to emit assembly code in ways that are
224 // mostly the same for different targets, but have minor differences in
225 // syntax. If the asmstring contains {|} characters in them, this integer
226 // will specify which alternative to use. For example "{x|y|z}" with Variant
227 // == 1, will expand to "y".
230 def DefaultAsmWriter : AsmWriter;
233 //===----------------------------------------------------------------------===//
234 // Target - This class contains the "global" target information
237 // CalleeSavedRegisters - As you might guess, this is a list of the callee
238 // saved registers for a target.
239 list<Register> CalleeSavedRegisters = [];
241 // PointerType - Specify the value type to be used to represent pointers in
242 // this target. Typically this is an i32 or i64 type.
243 ValueType PointerType;
245 // InstructionSet - Instruction set description for this target.
246 InstrInfo InstructionSet;
248 // AssemblyWriters - The AsmWriter instances available for this target.
249 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
252 //===----------------------------------------------------------------------===//
253 // SubtargetFeature - A characteristic of the chip set.
255 class SubtargetFeature<string n, string d> {
256 // Name - Feature name. Used by command line (-mattr=) to determine the
257 // appropriate target chip.
261 // Desc - Feature description. Used by command line (-mattr=) to display help
267 //===----------------------------------------------------------------------===//
268 // Processor chip sets - These values represent each of the chip sets supported
269 // by the scheduler. Each Processor definition requires corresponding
270 // instruction itineraries.
272 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
273 // Name - Chip set name. Used by command line (-mcpu=) to determine the
274 // appropriate target chip.
278 // ProcItin - The scheduling information for the target processor.
280 ProcessorItineraries ProcItin = pi;
282 // Features - list of
283 list<SubtargetFeature> Features = f;
286 //===----------------------------------------------------------------------===//
287 // Pull in the common support for DAG isel generation
289 include "../TargetSelectionDAG.td"