1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 // Value types - These values correspond to the register types defined in the
19 // ValueTypes.h file. If you update anything here, you must update it there as
22 class ValueType<int size, int value> {
23 string Namespace = "MVT";
28 def OtherVT: ValueType<0 , 0>; // "Other" value
29 def i1 : ValueType<1 , 1>; // One bit boolean value
30 def i8 : ValueType<8 , 2>; // 8-bit integer value
31 def i16 : ValueType<16 , 3>; // 16-bit integer value
32 def i32 : ValueType<32 , 4>; // 32-bit integer value
33 def i64 : ValueType<64 , 5>; // 64-bit integer value
34 def i128 : ValueType<128, 5>; // 128-bit integer value
35 def f32 : ValueType<32 , 7>; // 32-bit floating point value
36 def f64 : ValueType<64 , 8>; // 64-bit floating point value
37 def f80 : ValueType<80 , 9>; // 80-bit floating point value
38 def f128 : ValueType<128, 9>; // 128-bit floating point value
39 def isVoid : ValueType<0 , 11>; // Produces no value
41 //===----------------------------------------------------------------------===//
42 // Register file description - These classes are used to fill in the target
43 // description classes in llvm/Target/MRegisterInfo.h
46 // Register - You should define one instance of this class for each register in
47 // the target machine.
50 string Namespace = "";
54 // NamedReg - If the name for the 'def' of the register should not become the
55 // "name" of the register, you can use this to specify a custom name instead.
57 class NamedReg<string n> : Register {
61 // RegisterAliases - You should define instances of this class to indicate which
62 // registers in the register file are aliased together. This allows the code
63 // generator to be careful not to put two values with overlapping live ranges
64 // into registers which alias.
66 class RegisterAliases<Register reg, list<Register> aliases> {
68 list<Register> Aliases = aliases;
71 // RegisterClass - Now that all of the registers are defined, and aliases
72 // between registers are defined, specify which registers belong to which
73 // register classes. This also defines the default allocation order of
74 // registers by register allocators.
76 class RegisterClass<ValueType regType, int alignment, list<Register> regList> {
77 // RegType - Specify the ValueType of the registers in this register class.
78 // Note that all registers in a register class must have the same ValueType.
80 ValueType RegType = regType;
82 // Alignment - Specify the alignment required of the registers when they are
83 // stored or loaded to memory.
85 int Size = RegType.Size;
86 int Alignment = alignment;
88 // MemberList - Specify which registers are in this class. If the
89 // allocation_order_* method are not specified, this also defines the order of
90 // allocation used by the register allocator.
92 list<Register> MemberList = regList;
94 // Methods - This member can be used to insert arbitrary code into a generated
95 // register class. The normal usage of this is to overload virtual methods.
100 //===----------------------------------------------------------------------===//
101 // Instruction set description - These classes correspond to the C++ classes in
102 // the Target/TargetInstrInfo.h file.
105 string Name = ""; // The opcode string for this instruction
106 string Namespace = "";
108 dag OperandList; // An dag containing the MI operand list.
109 string AsmString = ""; // The .s format to print the instruction with.
111 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
112 // otherwise, uninitialized.
115 // The follow state will eventually be inferred automatically from the
116 // instruction pattern.
118 list<Register> Uses = []; // Default to using no non-operand registers
119 list<Register> Defs = []; // Default to modifying no non-operand registers
121 // These bits capture information about the high-level semantics of the
123 bit isReturn = 0; // Is this instruction a return instruction?
124 bit isBranch = 0; // Is this instruction a branch instruction?
125 bit isBarrier = 0; // Can control flow fall through this instruction?
126 bit isCall = 0; // Is this instruction a call instruction?
127 bit isTwoAddress = 0; // Is this a two address instruction?
128 bit isTerminator = 0; // Is this part of the terminator for a basic block?
132 /// ops definition - This is just a simple marker used to identify the operands
133 /// list for an instruction. This should be used like this:
134 /// (ops R32:$dst, R32:$src) or something similar.
137 /// Operand Types - These provide the built-in operand types that may be used
138 /// by a target. Targets can optionally provide their own operand types as
139 /// needed, though this should not be needed for RISC targets.
140 class Operand<ValueType ty> {
141 int NumMIOperands = 1;
143 string PrintMethod = "printOperand";
146 def i1imm : Operand<i1>;
147 def i8imm : Operand<i8>;
148 def i16imm : Operand<i16>;
149 def i32imm : Operand<i32>;
150 def i64imm : Operand<i64>;
152 // InstrInfo - This class should only be instantiated once to provide parameters
153 // which are global to the the target machine.
158 // If the target wants to associate some target-specific information with each
159 // instruction, it should provide these two lists to indicate how to assemble
160 // the target specific information into the 32 bits available.
162 list<string> TSFlagsFields = [];
163 list<int> TSFlagsShifts = [];
166 //===----------------------------------------------------------------------===//
167 // AsmWriter - This class can be implemented by targets that need to customize
168 // the format of the .s file writer.
170 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
171 // on X86 for example).
174 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
175 // class. Generated AsmWriter classes are always prefixed with the target
177 string AsmWriterClassName = "AsmPrinter";
179 // InstFormatName - AsmWriters can specify the name of the format string to
180 // print instructions with.
181 string InstFormatName = "AsmString";
183 def DefaultAsmWriter : AsmWriter;
186 //===----------------------------------------------------------------------===//
187 // Target - This class contains the "global" target information
190 // CalleeSavedRegisters - As you might guess, this is a list of the callee
191 // saved registers for a target.
192 list<Register> CalleeSavedRegisters = [];
194 // PointerType - Specify the value type to be used to represent pointers in
195 // this target. Typically this is an i32 or i64 type.
196 ValueType PointerType;
198 // InstructionSet - Instruction set description for this target.
199 InstrInfo InstructionSet;
201 // AssemblyWriter - The AsmWriter instance to use for this target.
202 AsmWriter AssemblyWriter = DefaultAsmWriter;
206 //===----------------------------------------------------------------------===//
207 // DAG node definitions used by the instruction selector.
209 // NOTE: all of this is a work-in-progress and should be ignored for now.
212 class Expander<dag pattern, list<dag> result> {
213 dag Pattern = pattern;
214 list<dag> Result = result;
217 class DagNodeValType;
218 def DNVT_any : DagNodeValType; // No constraint on tree node
219 def DNVT_void : DagNodeValType; // Tree node always returns void
220 def DNVT_val : DagNodeValType; // A non-void type
221 def DNVT_arg0 : DagNodeValType; // Tree node returns same type as Arg0
222 def DNVT_arg1 : DagNodeValType; // Tree node returns same type as Arg1
223 def DNVT_ptr : DagNodeValType; // The target pointer type
224 def DNVT_i8 : DagNodeValType; // Always have an i8 value
226 class DagNode<DagNodeValType ret, list<DagNodeValType> args> {
227 DagNodeValType RetType = ret;
228 list<DagNodeValType> ArgTypes = args;
232 // BuiltinDagNodes are built into the instruction selector and correspond to
234 class BuiltinDagNode<DagNodeValType Ret, list<DagNodeValType> Args,
235 string Ename> : DagNode<Ret, Args> {
236 let EnumName = Ename;
240 def Void : RegisterClass<isVoid,0,[]> { let isDummyClass = 1; }
241 def set : DagNode<DNVT_void, [DNVT_val, DNVT_arg0]>;
242 def chain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void], "ChainNode">;
243 def blockchain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void],
245 def ChainExpander : Expander<(chain Void, Void), []>;
246 def BlockChainExpander : Expander<(blockchain Void, Void), []>;
250 def imm : BuiltinDagNode<DNVT_val, [], "Constant">;
251 def frameidx : BuiltinDagNode<DNVT_ptr, [], "FrameIndex">;
252 def basicblock : BuiltinDagNode<DNVT_ptr, [], "BasicBlock">;
255 def plus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Plus">;
256 def minus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Minus">;
257 def times : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Times">;
258 def sdiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SDiv">;
259 def udiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "UDiv">;
260 def srem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SRem">;
261 def urem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "URem">;
262 def and : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "And">;
263 def or : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Or">;
264 def xor : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Xor">;
267 def seteq : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetEQ">;
268 def setne : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetNE">;
269 def setlt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLT">;
270 def setle : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLE">;
271 def setgt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGT">;
272 def setge : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGE">;
274 def load : BuiltinDagNode<DNVT_val, [DNVT_ptr], "Load">;
275 //def store : BuiltinDagNode<DNVT_Void, [DNVT_ptr, DNVT_val]>;
278 def ret : BuiltinDagNode<DNVT_void, [DNVT_val], "Ret">;
279 def retvoid : BuiltinDagNode<DNVT_void, [], "RetVoid">;
280 def br : BuiltinDagNode<DNVT_void, [DNVT_ptr], "Br">;
281 def brcond : BuiltinDagNode<DNVT_void, [DNVT_i8, DNVT_ptr, DNVT_ptr],
284 def unspec1 : BuiltinDagNode<DNVT_any , [DNVT_val], "Unspec1">;
285 def unspec2 : BuiltinDagNode<DNVT_any , [DNVT_val, DNVT_val], "Unspec2">;
287 //===----------------------------------------------------------------------===//
288 // DAG nonterminals definitions used by the instruction selector...
290 class Nonterminal<dag pattern> {
291 dag Pattern = pattern;