1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // Register - You should define one instance of this class for each register
25 // in the target machine. String n will become the "name" of the register.
26 class Register<string n> {
27 string Namespace = "";
29 string PrintableName = n;
31 // SpillSize - If this value is set to a non-zero value, it is the size in
32 // bits of the spill slot required to hold this register. If this value is
33 // set to zero, the information is inferred from any register classes the
34 // register belongs to.
37 // SpillAlignment - This value is used to specify the alignment required for
38 // spilling the register. Like SpillSize, this should only be explicitly
39 // specified if the register is not in a register class.
40 int SpillAlignment = 0;
42 // Aliases - A list of registers that this register overlaps with. A read or
43 // modification of this register can potentially read or modify the aliased
45 list<Register> Aliases = [];
47 // SubRegs - A list of registers that are parts of this register. Note these
48 // are "immediate" sub-registers and the registers within the list do not
49 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
51 list<Register> SubRegs = [];
53 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
54 // These values can be determined by locating the <target>.h file in the
55 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
56 // order of these names correspond to the enumeration used by gcc. A value of
57 // -1 indicates that the gcc number is undefined and -2 that register number
58 // is invalid for this mode/flavour.
59 list<int> DwarfNumbers = [];
62 // RegisterWithSubRegs - This can be used to define instances of Register which
63 // need to specify sub-registers.
64 // List "subregs" specifies which registers are sub-registers to this one. This
65 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
66 // This allows the code generator to be careful not to put two values with
67 // overlapping live ranges into registers which alias.
68 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
69 let SubRegs = subregs;
72 // SubRegSet - This can be used to define a specific mapping of registers to
73 // indices, for use as named subregs of a particular physical register. Each
74 // register in 'subregs' becomes an addressable subregister at index 'n' of the
75 // corresponding register in 'regs'.
76 class SubRegSet<int n, list<Register> regs, list<Register> subregs> {
79 list<Register> From = regs;
80 list<Register> To = subregs;
83 // RegisterClass - Now that all of the registers are defined, and aliases
84 // between registers are defined, specify which registers belong to which
85 // register classes. This also defines the default allocation order of
86 // registers by register allocators.
88 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
89 list<Register> regList> {
90 string Namespace = namespace;
92 // RegType - Specify the list ValueType of the registers in this register
93 // class. Note that all registers in a register class must have the same
94 // ValueTypes. This is a list because some targets permit storing different
95 // types in same register, for example vector values with 128-bit total size,
96 // but different count/size of items, like SSE on x86.
98 list<ValueType> RegTypes = regTypes;
100 // Size - Specify the spill size in bits of the registers. A default value of
101 // zero lets tablgen pick an appropriate size.
104 // Alignment - Specify the alignment required of the registers when they are
105 // stored or loaded to memory.
107 int Alignment = alignment;
109 // CopyCost - This value is used to specify the cost of copying a value
110 // between two registers in this register class. The default value is one
111 // meaning it takes a single instruction to perform the copying. A negative
112 // value means copying is extremely expensive or impossible.
115 // MemberList - Specify which registers are in this class. If the
116 // allocation_order_* method are not specified, this also defines the order of
117 // allocation used by the register allocator.
119 list<Register> MemberList = regList;
121 // SubClassList - Specify which register classes correspond to subregisters
122 // of this class. The order should be by subregister set index.
123 list<RegisterClass> SubRegClassList = [];
125 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
126 // code into a generated register class. The normal usage of this is to
127 // overload virtual methods.
128 code MethodProtos = [{}];
129 code MethodBodies = [{}];
133 //===----------------------------------------------------------------------===//
134 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
135 // to the register numbering used by gcc and gdb. These values are used by a
136 // debug information writer (ex. DwarfWriter) to describe where values may be
137 // located during execution.
138 class DwarfRegNum<list<int> Numbers> {
139 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
140 // These values can be determined by locating the <target>.h file in the
141 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
142 // order of these names correspond to the enumeration used by gcc. A value of
143 // -1 indicates that the gcc number is undefined and -2 that register number is
144 // invalid for this mode/flavour.
145 list<int> DwarfNumbers = Numbers;
148 //===----------------------------------------------------------------------===//
149 // Pull in the common support for scheduling
151 include "TargetSchedule.td"
153 class Predicate; // Forward def
155 //===----------------------------------------------------------------------===//
156 // Instruction set description - These classes correspond to the C++ classes in
157 // the Target/TargetInstrInfo.h file.
160 string Namespace = "";
162 dag OutOperandList; // An dag containing the MI def operand list.
163 dag InOperandList; // An dag containing the MI use operand list.
164 string AsmString = ""; // The .s format to print the instruction with.
166 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
167 // otherwise, uninitialized.
170 // The follow state will eventually be inferred automatically from the
171 // instruction pattern.
173 list<Register> Uses = []; // Default to using no non-operand registers
174 list<Register> Defs = []; // Default to modifying no non-operand registers
176 // Predicates - List of predicates which will be turned into isel matching
178 list<Predicate> Predicates = [];
183 // Added complexity passed onto matching pattern.
184 int AddedComplexity = 0;
186 // These bits capture information about the high-level semantics of the
188 bit isReturn = 0; // Is this instruction a return instruction?
189 bit isBranch = 0; // Is this instruction a branch instruction?
190 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
191 bit isBarrier = 0; // Can control flow fall through this instruction?
192 bit isCall = 0; // Is this instruction a call instruction?
193 bit isSimpleLoad = 0; // Is this just a load instruction?
194 bit mayLoad = 0; // Is it possible for this inst to read memory?
195 bit mayStore = 0; // Is it possible for this inst to write memory?
196 bit isImplicitDef = 0; // Is this instruction an implicit def instruction?
197 bit isTwoAddress = 0; // Is this a two address instruction?
198 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
199 bit isCommutable = 0; // Is this 3 operand instruction commutable?
200 bit isTerminator = 0; // Is this part of the terminator for a basic block?
201 bit isReMaterializable = 0; // Is this instruction re-materializable?
202 bit isPredicable = 0; // Is this instruction predicable?
203 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
204 bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
205 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
206 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
208 // Side effect flags - When set, the flags have these meanings:
210 // hasSideEffects - The instruction has side effects that are not
211 // captured by any operands of the instruction or other flags.
212 // mayHaveSideEffects - Some instances of the instruction can have side
213 // effects. The virtual method "isReallySideEffectFree" is called to
214 // determine this. Load instructions are an example of where this is
215 // useful. In general, loads always have side effects. However, loads from
216 // constant pools don't. Individual back ends make this determination.
217 // neverHasSideEffects - Set on an instruction with no pattern if it has no
219 bit hasSideEffects = 0;
220 bit mayHaveSideEffects = 0;
221 bit neverHasSideEffects = 0;
223 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
225 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
227 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
228 /// be encoded into the output machineinstr.
229 string DisableEncoding = "";
232 /// Predicates - These are extra conditionals which are turned into instruction
233 /// selector matching code. Currently each predicate is just a string.
234 class Predicate<string cond> {
235 string CondString = cond;
238 /// NoHonorSignDependentRounding - This predicate is true if support for
239 /// sign-dependent-rounding is not enabled.
240 def NoHonorSignDependentRounding
241 : Predicate<"!HonorSignDependentRoundingFPMath()">;
243 class Requires<list<Predicate> preds> {
244 list<Predicate> Predicates = preds;
247 /// ops definition - This is just a simple marker used to identify the operands
248 /// list for an instruction. outs and ins are identical both syntatically and
249 /// semantically, they are used to define def operands and use operands to
250 /// improve readibility. This should be used like this:
251 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
256 /// variable_ops definition - Mark this instruction as taking a variable number
260 /// ptr_rc definition - Mark this operand as being a pointer value whose
261 /// register class is resolved dynamically via a callback to TargetInstrInfo.
262 /// FIXME: We should probably change this to a class which contain a list of
263 /// flags. But currently we have but one flag.
266 /// Operand Types - These provide the built-in operand types that may be used
267 /// by a target. Targets can optionally provide their own operand types as
268 /// needed, though this should not be needed for RISC targets.
269 class Operand<ValueType ty> {
271 string PrintMethod = "printOperand";
272 dag MIOperandInfo = (ops);
275 def i1imm : Operand<i1>;
276 def i8imm : Operand<i8>;
277 def i16imm : Operand<i16>;
278 def i32imm : Operand<i32>;
279 def i64imm : Operand<i64>;
281 def f32imm : Operand<f32>;
282 def f64imm : Operand<f64>;
284 /// zero_reg definition - Special node to stand for the zero register.
288 /// PredicateOperand - This can be used to define a predicate operand for an
289 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
290 /// AlwaysVal specifies the value of this predicate when set to "always
292 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
294 let MIOperandInfo = OpTypes;
295 dag DefaultOps = AlwaysVal;
298 /// OptionalDefOperand - This is used to define a optional definition operand
299 /// for an instruction. DefaultOps is the register the operand represents if none
300 /// is supplied, e.g. zero_reg.
301 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
303 let MIOperandInfo = OpTypes;
304 dag DefaultOps = defaultops;
308 // InstrInfo - This class should only be instantiated once to provide parameters
309 // which are global to the the target machine.
312 // If the target wants to associate some target-specific information with each
313 // instruction, it should provide these two lists to indicate how to assemble
314 // the target specific information into the 32 bits available.
316 list<string> TSFlagsFields = [];
317 list<int> TSFlagsShifts = [];
319 // Target can specify its instructions in either big or little-endian formats.
320 // For instance, while both Sparc and PowerPC are big-endian platforms, the
321 // Sparc manual specifies its instructions in the format [31..0] (big), while
322 // PowerPC specifies them using the format [0..31] (little).
323 bit isLittleEndianEncoding = 0;
326 // Standard Instructions.
327 def PHI : Instruction {
328 let OutOperandList = (ops);
329 let InOperandList = (ops variable_ops);
330 let AsmString = "PHINODE";
331 let Namespace = "TargetInstrInfo";
333 def INLINEASM : Instruction {
334 let OutOperandList = (ops);
335 let InOperandList = (ops variable_ops);
337 let Namespace = "TargetInstrInfo";
339 def LABEL : Instruction {
340 let OutOperandList = (ops);
341 let InOperandList = (ops i32imm:$id, i32imm:$flavor);
343 let Namespace = "TargetInstrInfo";
346 def DECLARE : Instruction {
347 let OutOperandList = (ops);
348 let InOperandList = (ops variable_ops);
350 let Namespace = "TargetInstrInfo";
353 def EXTRACT_SUBREG : Instruction {
354 let OutOperandList = (ops variable_ops);
355 let InOperandList = (ops variable_ops);
357 let Namespace = "TargetInstrInfo";
358 let neverHasSideEffects = 1;
360 def INSERT_SUBREG : Instruction {
361 let OutOperandList = (ops variable_ops);
362 let InOperandList = (ops variable_ops);
364 let Namespace = "TargetInstrInfo";
365 let neverHasSideEffects = 1;
368 //===----------------------------------------------------------------------===//
369 // AsmWriter - This class can be implemented by targets that need to customize
370 // the format of the .s file writer.
372 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
373 // on X86 for example).
376 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
377 // class. Generated AsmWriter classes are always prefixed with the target
379 string AsmWriterClassName = "AsmPrinter";
381 // InstFormatName - AsmWriters can specify the name of the format string to
382 // print instructions with.
383 string InstFormatName = "AsmString";
385 // Variant - AsmWriters can be of multiple different variants. Variants are
386 // used to support targets that need to emit assembly code in ways that are
387 // mostly the same for different targets, but have minor differences in
388 // syntax. If the asmstring contains {|} characters in them, this integer
389 // will specify which alternative to use. For example "{x|y|z}" with Variant
390 // == 1, will expand to "y".
393 def DefaultAsmWriter : AsmWriter;
396 //===----------------------------------------------------------------------===//
397 // Target - This class contains the "global" target information
400 // InstructionSet - Instruction set description for this target.
401 InstrInfo InstructionSet;
403 // AssemblyWriters - The AsmWriter instances available for this target.
404 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
407 //===----------------------------------------------------------------------===//
408 // SubtargetFeature - A characteristic of the chip set.
410 class SubtargetFeature<string n, string a, string v, string d,
411 list<SubtargetFeature> i = []> {
412 // Name - Feature name. Used by command line (-mattr=) to determine the
413 // appropriate target chip.
417 // Attribute - Attribute to be set by feature.
419 string Attribute = a;
421 // Value - Value the attribute to be set to by feature.
425 // Desc - Feature description. Used by command line (-mattr=) to display help
430 // Implies - Features that this feature implies are present. If one of those
431 // features isn't set, then this one shouldn't be set either.
433 list<SubtargetFeature> Implies = i;
436 //===----------------------------------------------------------------------===//
437 // Processor chip sets - These values represent each of the chip sets supported
438 // by the scheduler. Each Processor definition requires corresponding
439 // instruction itineraries.
441 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
442 // Name - Chip set name. Used by command line (-mcpu=) to determine the
443 // appropriate target chip.
447 // ProcItin - The scheduling information for the target processor.
449 ProcessorItineraries ProcItin = pi;
451 // Features - list of
452 list<SubtargetFeature> Features = f;
455 //===----------------------------------------------------------------------===//
456 // Pull in the common support for calling conventions.
458 include "TargetCallingConv.td"
460 //===----------------------------------------------------------------------===//
461 // Pull in the common support for DAG isel generation.
463 include "TargetSelectionDAG.td"