1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 // Value types - These values correspond to the register types defined in the
19 // ValueTypes.h file. If you update anything here, you must update it there as
22 class ValueType<int size, int value> {
23 string Namespace = "MVT";
28 def OtherVT: ValueType<0 , 0>; // "Other" value
29 def i1 : ValueType<1 , 1>; // One bit boolean value
30 def i8 : ValueType<8 , 2>; // 8-bit integer value
31 def i16 : ValueType<16 , 3>; // 16-bit integer value
32 def i32 : ValueType<32 , 4>; // 32-bit integer value
33 def i64 : ValueType<64 , 5>; // 64-bit integer value
34 def i128 : ValueType<128, 5>; // 128-bit integer value
35 def f32 : ValueType<32 , 7>; // 32-bit floating point value
36 def f64 : ValueType<64 , 8>; // 64-bit floating point value
37 def f80 : ValueType<80 , 9>; // 80-bit floating point value
38 def f128 : ValueType<128, 9>; // 128-bit floating point value
39 def isVoid : ValueType<0 , 11>; // Produces no value
41 //===----------------------------------------------------------------------===//
42 // Register file description - These classes are used to fill in the target
43 // description classes in llvm/Target/MRegisterInfo.h
46 // Register - You should define one instance of this class for each register in
47 // the target machine.
50 string Namespace = "";
53 // SpillSize - If this value is set to a non-zero value, it is the size in
54 // bits of the spill slot required to hold this register. If this value is
55 // set to zero, the information is inferred from any register classes the
56 // register belongs to.
59 // SpillAlignment - This value is used to specify the alignment required for
60 // spilling the register. Like SpillSize, this should only be explicitly
61 // specified if the register is not in a register class.
62 int SpillAlignment = 0;
65 // NamedReg - If the name for the 'def' of the register should not become the
66 // "name" of the register, you can use this to specify a custom name instead.
68 class NamedReg<string n> : Register {
72 // RegisterAliases - You should define instances of this class to indicate which
73 // registers in the register file are aliased together. This allows the code
74 // generator to be careful not to put two values with overlapping live ranges
75 // into registers which alias.
77 class RegisterAliases<Register reg, list<Register> aliases> {
79 list<Register> Aliases = aliases;
82 // RegisterClass - Now that all of the registers are defined, and aliases
83 // between registers are defined, specify which registers belong to which
84 // register classes. This also defines the default allocation order of
85 // registers by register allocators.
87 class RegisterClass<ValueType regType, int alignment, list<Register> regList> {
88 // RegType - Specify the ValueType of the registers in this register class.
89 // Note that all registers in a register class must have the same ValueType.
91 ValueType RegType = regType;
93 // Alignment - Specify the alignment required of the registers when they are
94 // stored or loaded to memory.
96 int Size = RegType.Size;
97 int Alignment = alignment;
99 // MemberList - Specify which registers are in this class. If the
100 // allocation_order_* method are not specified, this also defines the order of
101 // allocation used by the register allocator.
103 list<Register> MemberList = regList;
105 // Methods - This member can be used to insert arbitrary code into a generated
106 // register class. The normal usage of this is to overload virtual methods.
111 //===----------------------------------------------------------------------===//
112 // Instruction set description - These classes correspond to the C++ classes in
113 // the Target/TargetInstrInfo.h file.
116 string Name = ""; // The opcode string for this instruction
117 string Namespace = "";
119 dag OperandList; // An dag containing the MI operand list.
120 string AsmString = ""; // The .s format to print the instruction with.
122 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
123 // otherwise, uninitialized.
126 // The follow state will eventually be inferred automatically from the
127 // instruction pattern.
129 list<Register> Uses = []; // Default to using no non-operand registers
130 list<Register> Defs = []; // Default to modifying no non-operand registers
132 // These bits capture information about the high-level semantics of the
134 bit isReturn = 0; // Is this instruction a return instruction?
135 bit isBranch = 0; // Is this instruction a branch instruction?
136 bit isBarrier = 0; // Can control flow fall through this instruction?
137 bit isCall = 0; // Is this instruction a call instruction?
138 bit isTwoAddress = 0; // Is this a two address instruction?
139 bit isTerminator = 0; // Is this part of the terminator for a basic block?
143 /// ops definition - This is just a simple marker used to identify the operands
144 /// list for an instruction. This should be used like this:
145 /// (ops R32:$dst, R32:$src) or something similar.
148 /// Operand Types - These provide the built-in operand types that may be used
149 /// by a target. Targets can optionally provide their own operand types as
150 /// needed, though this should not be needed for RISC targets.
151 class Operand<ValueType ty> {
152 int NumMIOperands = 1;
154 string PrintMethod = "printOperand";
157 def i1imm : Operand<i1>;
158 def i8imm : Operand<i8>;
159 def i16imm : Operand<i16>;
160 def i32imm : Operand<i32>;
161 def i64imm : Operand<i64>;
163 // InstrInfo - This class should only be instantiated once to provide parameters
164 // which are global to the the target machine.
169 // If the target wants to associate some target-specific information with each
170 // instruction, it should provide these two lists to indicate how to assemble
171 // the target specific information into the 32 bits available.
173 list<string> TSFlagsFields = [];
174 list<int> TSFlagsShifts = [];
177 //===----------------------------------------------------------------------===//
178 // AsmWriter - This class can be implemented by targets that need to customize
179 // the format of the .s file writer.
181 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
182 // on X86 for example).
185 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
186 // class. Generated AsmWriter classes are always prefixed with the target
188 string AsmWriterClassName = "AsmPrinter";
190 // InstFormatName - AsmWriters can specify the name of the format string to
191 // print instructions with.
192 string InstFormatName = "AsmString";
194 def DefaultAsmWriter : AsmWriter;
197 //===----------------------------------------------------------------------===//
198 // Target - This class contains the "global" target information
201 // CalleeSavedRegisters - As you might guess, this is a list of the callee
202 // saved registers for a target.
203 list<Register> CalleeSavedRegisters = [];
205 // PointerType - Specify the value type to be used to represent pointers in
206 // this target. Typically this is an i32 or i64 type.
207 ValueType PointerType;
209 // InstructionSet - Instruction set description for this target.
210 InstrInfo InstructionSet;
212 // AssemblyWriter - The AsmWriter instance to use for this target.
213 AsmWriter AssemblyWriter = DefaultAsmWriter;
217 //===----------------------------------------------------------------------===//
218 // DAG node definitions used by the instruction selector.
220 // NOTE: all of this is a work-in-progress and should be ignored for now.
223 class Expander<dag pattern, list<dag> result> {
224 dag Pattern = pattern;
225 list<dag> Result = result;
228 class DagNodeValType;
229 def DNVT_any : DagNodeValType; // No constraint on tree node
230 def DNVT_void : DagNodeValType; // Tree node always returns void
231 def DNVT_val : DagNodeValType; // A non-void type
232 def DNVT_arg0 : DagNodeValType; // Tree node returns same type as Arg0
233 def DNVT_arg1 : DagNodeValType; // Tree node returns same type as Arg1
234 def DNVT_ptr : DagNodeValType; // The target pointer type
235 def DNVT_i8 : DagNodeValType; // Always have an i8 value
237 class DagNode<DagNodeValType ret, list<DagNodeValType> args> {
238 DagNodeValType RetType = ret;
239 list<DagNodeValType> ArgTypes = args;
243 // BuiltinDagNodes are built into the instruction selector and correspond to
245 class BuiltinDagNode<DagNodeValType Ret, list<DagNodeValType> Args,
246 string Ename> : DagNode<Ret, Args> {
247 let EnumName = Ename;
251 def Void : RegisterClass<isVoid,0,[]> { let isDummyClass = 1; }
252 def set : DagNode<DNVT_void, [DNVT_val, DNVT_arg0]>;
253 def chain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void], "ChainNode">;
254 def blockchain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void],
256 def ChainExpander : Expander<(chain Void, Void), []>;
257 def BlockChainExpander : Expander<(blockchain Void, Void), []>;
261 def imm : BuiltinDagNode<DNVT_val, [], "Constant">;
262 def frameidx : BuiltinDagNode<DNVT_ptr, [], "FrameIndex">;
263 def basicblock : BuiltinDagNode<DNVT_ptr, [], "BasicBlock">;
266 def plus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Plus">;
267 def minus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Minus">;
268 def times : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Times">;
269 def sdiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SDiv">;
270 def udiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "UDiv">;
271 def srem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SRem">;
272 def urem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "URem">;
273 def and : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "And">;
274 def or : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Or">;
275 def xor : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Xor">;
278 def seteq : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetEQ">;
279 def setne : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetNE">;
280 def setlt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLT">;
281 def setle : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLE">;
282 def setgt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGT">;
283 def setge : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGE">;
285 def load : BuiltinDagNode<DNVT_val, [DNVT_ptr], "Load">;
286 //def store : BuiltinDagNode<DNVT_Void, [DNVT_ptr, DNVT_val]>;
289 def ret : BuiltinDagNode<DNVT_void, [DNVT_val], "Ret">;
290 def retvoid : BuiltinDagNode<DNVT_void, [], "RetVoid">;
291 def br : BuiltinDagNode<DNVT_void, [DNVT_ptr], "Br">;
292 def brcond : BuiltinDagNode<DNVT_void, [DNVT_i8, DNVT_ptr, DNVT_ptr],
295 def unspec1 : BuiltinDagNode<DNVT_any , [DNVT_val], "Unspec1">;
296 def unspec2 : BuiltinDagNode<DNVT_any , [DNVT_val, DNVT_val], "Unspec2">;
298 //===----------------------------------------------------------------------===//
299 // DAG nonterminals definitions used by the instruction selector...
301 class Nonterminal<dag pattern> {
302 dag Pattern = pattern;