1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // Register - You should define one instance of this class for each register
25 // in the target machine. String n will become the "name" of the register.
26 class Register<string n> {
27 string Namespace = "";
30 // SpillSize - If this value is set to a non-zero value, it is the size in
31 // bits of the spill slot required to hold this register. If this value is
32 // set to zero, the information is inferred from any register classes the
33 // register belongs to.
36 // SpillAlignment - This value is used to specify the alignment required for
37 // spilling the register. Like SpillSize, this should only be explicitly
38 // specified if the register is not in a register class.
39 int SpillAlignment = 0;
41 // Aliases - A list of registers that this register overlaps with. A read or
42 // modification of this register can potentially read or modifie the aliased
45 list<Register> Aliases = [];
47 // DwarfNumber - Number used internally by gcc/gdb to identify the register.
48 // These values can be determined by locating the <target>.h file in the
49 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
50 // order of these names correspond to the enumeration used by gcc. A value of
51 // -1 indicates that the gcc number is undefined.
55 // RegisterGroup - This can be used to define instances of Register which
56 // need to specify aliases.
57 // List "aliases" specifies which registers are aliased to this one. This
58 // allows the code generator to be careful not to put two values with
59 // overlapping live ranges into registers which alias.
60 class RegisterGroup<string n, list<Register> aliases> : Register<n> {
61 let Aliases = aliases;
64 // RegisterClass - Now that all of the registers are defined, and aliases
65 // between registers are defined, specify which registers belong to which
66 // register classes. This also defines the default allocation order of
67 // registers by register allocators.
69 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
70 list<Register> regList> {
71 string Namespace = namespace;
73 // RegType - Specify the list ValueType of the registers in this register
74 // class. Note that all registers in a register class must have the same
77 list<ValueType> RegTypes = regTypes;
79 // Size - Specify the spill size in bits of the registers. A default value of
80 // zero lets tablgen pick an appropriate size.
83 // Alignment - Specify the alignment required of the registers when they are
84 // stored or loaded to memory.
86 int Alignment = alignment;
88 // MemberList - Specify which registers are in this class. If the
89 // allocation_order_* method are not specified, this also defines the order of
90 // allocation used by the register allocator.
92 list<Register> MemberList = regList;
94 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
95 // code into a generated register class. The normal usage of this is to
96 // overload virtual methods.
97 code MethodProtos = [{}];
98 code MethodBodies = [{}];
102 //===----------------------------------------------------------------------===//
103 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
104 // to the register numbering used by gcc and gdb. These values are used by a
105 // debug information writer (ex. DwarfWriter) to describe where values may be
106 // located during execution.
107 class DwarfRegNum<int N> {
108 // DwarfNumber - Number used internally by gcc/gdb to identify the register.
109 // These values can be determined by locating the <target>.h file in the
110 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
111 // order of these names correspond to the enumeration used by gcc. A value of
112 // -1 indicates that the gcc number is undefined.
116 //===----------------------------------------------------------------------===//
117 // Pull in the common support for scheduling
119 include "../TargetSchedule.td"
121 class Predicate; // Forward def
123 //===----------------------------------------------------------------------===//
124 // Instruction set description - These classes correspond to the C++ classes in
125 // the Target/TargetInstrInfo.h file.
128 string Name = ""; // The opcode string for this instruction
129 string Namespace = "";
131 dag OperandList; // An dag containing the MI operand list.
132 string AsmString = ""; // The .s format to print the instruction with.
134 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
135 // otherwise, uninitialized.
138 // The follow state will eventually be inferred automatically from the
139 // instruction pattern.
141 list<Register> Uses = []; // Default to using no non-operand registers
142 list<Register> Defs = []; // Default to modifying no non-operand registers
144 // Predicates - List of predicates which will be turned into isel matching
146 list<Predicate> Predicates = [];
148 // Added complexity passed onto matching pattern.
149 int AddedComplexity = 0;
151 // These bits capture information about the high-level semantics of the
153 bit isReturn = 0; // Is this instruction a return instruction?
154 bit isBranch = 0; // Is this instruction a branch instruction?
155 bit isBarrier = 0; // Can control flow fall through this instruction?
156 bit isCall = 0; // Is this instruction a call instruction?
157 bit isLoad = 0; // Is this instruction a load instruction?
158 bit isStore = 0; // Is this instruction a store instruction?
159 bit isTwoAddress = 0; // Is this a two address instruction?
160 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
161 bit isCommutable = 0; // Is this 3 operand instruction commutable?
162 bit isTerminator = 0; // Is this part of the terminator for a basic block?
163 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
164 bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
165 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
166 bit noResults = 0; // Does this instruction produce no results?
168 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
171 /// Predicates - These are extra conditionals which are turned into instruction
172 /// selector matching code. Currently each predicate is just a string.
173 class Predicate<string cond> {
174 string CondString = cond;
177 class Requires<list<Predicate> preds> {
178 list<Predicate> Predicates = preds;
181 /// ops definition - This is just a simple marker used to identify the operands
182 /// list for an instruction. This should be used like this:
183 /// (ops R32:$dst, R32:$src) or something similar.
186 /// variable_ops definition - Mark this instruction as taking a variable number
190 /// Operand Types - These provide the built-in operand types that may be used
191 /// by a target. Targets can optionally provide their own operand types as
192 /// needed, though this should not be needed for RISC targets.
193 class Operand<ValueType ty> {
195 string PrintMethod = "printOperand";
196 int NumMIOperands = 1;
197 dag MIOperandInfo = (ops);
200 def i1imm : Operand<i1>;
201 def i8imm : Operand<i8>;
202 def i16imm : Operand<i16>;
203 def i32imm : Operand<i32>;
204 def i64imm : Operand<i64>;
206 // InstrInfo - This class should only be instantiated once to provide parameters
207 // which are global to the the target machine.
210 // If the target wants to associate some target-specific information with each
211 // instruction, it should provide these two lists to indicate how to assemble
212 // the target specific information into the 32 bits available.
214 list<string> TSFlagsFields = [];
215 list<int> TSFlagsShifts = [];
217 // Target can specify its instructions in either big or little-endian formats.
218 // For instance, while both Sparc and PowerPC are big-endian platforms, the
219 // Sparc manual specifies its instructions in the format [31..0] (big), while
220 // PowerPC specifies them using the format [0..31] (little).
221 bit isLittleEndianEncoding = 0;
224 // Standard Instructions.
225 def PHI : Instruction {
226 let OperandList = (ops variable_ops);
227 let AsmString = "PHINODE";
228 let Namespace = "TargetInstrInfo";
230 def INLINEASM : Instruction {
231 let OperandList = (ops variable_ops);
233 let Namespace = "TargetInstrInfo";
236 //===----------------------------------------------------------------------===//
237 // AsmWriter - This class can be implemented by targets that need to customize
238 // the format of the .s file writer.
240 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
241 // on X86 for example).
244 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
245 // class. Generated AsmWriter classes are always prefixed with the target
247 string AsmWriterClassName = "AsmPrinter";
249 // InstFormatName - AsmWriters can specify the name of the format string to
250 // print instructions with.
251 string InstFormatName = "AsmString";
253 // Variant - AsmWriters can be of multiple different variants. Variants are
254 // used to support targets that need to emit assembly code in ways that are
255 // mostly the same for different targets, but have minor differences in
256 // syntax. If the asmstring contains {|} characters in them, this integer
257 // will specify which alternative to use. For example "{x|y|z}" with Variant
258 // == 1, will expand to "y".
261 def DefaultAsmWriter : AsmWriter;
264 //===----------------------------------------------------------------------===//
265 // Target - This class contains the "global" target information
268 // CalleeSavedRegisters - As you might guess, this is a list of the callee
269 // saved registers for a target.
270 list<Register> CalleeSavedRegisters = [];
272 // PointerType - Specify the value type to be used to represent pointers in
273 // this target. Typically this is an i32 or i64 type.
274 ValueType PointerType;
276 // InstructionSet - Instruction set description for this target.
277 InstrInfo InstructionSet;
279 // AssemblyWriters - The AsmWriter instances available for this target.
280 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
283 //===----------------------------------------------------------------------===//
284 // SubtargetFeature - A characteristic of the chip set.
286 class SubtargetFeature<string n, string a, string v, string d> {
287 // Name - Feature name. Used by command line (-mattr=) to determine the
288 // appropriate target chip.
292 // Attribute - Attribute to be set by feature.
294 string Attribute = a;
296 // Value - Value the attribute to be set to by feature.
300 // Desc - Feature description. Used by command line (-mattr=) to display help
306 //===----------------------------------------------------------------------===//
307 // Processor chip sets - These values represent each of the chip sets supported
308 // by the scheduler. Each Processor definition requires corresponding
309 // instruction itineraries.
311 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
312 // Name - Chip set name. Used by command line (-mcpu=) to determine the
313 // appropriate target chip.
317 // ProcItin - The scheduling information for the target processor.
319 ProcessorItineraries ProcItin = pi;
321 // Features - list of
322 list<SubtargetFeature> Features = f;
325 //===----------------------------------------------------------------------===//
326 // Pull in the common support for DAG isel generation
328 include "../TargetSelectionDAG.td"