1 //===- Target.td - Target Independent TableGen interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 // Value types - These values correspond to the register types defined in the
19 // ValueTypes.h file. If you update anything here, you must update it there as
22 class ValueType<int size, int value> {
23 string Namespace = "MVT";
28 def i1 : ValueType<1 , 1>; // One bit boolean value
29 def i8 : ValueType<8 , 2>; // 8-bit integer value
30 def i16 : ValueType<16 , 3>; // 16-bit integer value
31 def i32 : ValueType<32 , 4>; // 32-bit integer value
32 def i64 : ValueType<64 , 5>; // 64-bit integer value
33 def i128 : ValueType<128, 5>; // 128-bit integer value
34 def f32 : ValueType<32 , 7>; // 32-bit floating point value
35 def f64 : ValueType<64 , 8>; // 64-bit floating point value
36 def f80 : ValueType<80 , 9>; // 80-bit floating point value
37 def f128 : ValueType<128, 9>; // 128-bit floating point value
38 def isVoid : ValueType<0 , 11>; // Produces no value
40 //===----------------------------------------------------------------------===//
41 // Register file description - These classes are used to fill in the target
42 // description classes in llvm/Target/MRegisterInfo.h
45 // Register - You should define one instance of this class for each register in
46 // the target machine.
49 string Namespace = "";
53 // NamedReg - If the name for the 'def' of the register should not become the
54 // "name" of the register, you can use this to specify a custom name instead.
56 class NamedReg<string n> : Register {
60 // RegisterAliases - You should define instances of this class to indicate which
61 // registers in the register file are aliased together. This allows the code
62 // generator to be careful not to put two values with overlapping live ranges
63 // into registers which alias.
65 class RegisterAliases<Register reg, list<Register> aliases> {
67 list<Register> Aliases = aliases;
70 // RegisterClass - Now that all of the registers are defined, and aliases
71 // between registers are defined, specify which registers belong to which
72 // register classes. This also defines the default allocation order of
73 // registers by register allocators.
75 class RegisterClass<ValueType regType, int alignment, list<Register> regList> {
76 // RegType - Specify the ValueType of the registers in this register class.
77 // Note that all registers in a register class must have the same ValueType.
79 ValueType RegType = regType;
81 // Alignment - Specify the alignment required of the registers when they are
82 // stored or loaded to memory.
84 int Size = RegType.Size;
85 int Alignment = alignment;
87 // MemberList - Specify which registers are in this class. If the
88 // allocation_order_* method are not specified, this also defines the order of
89 // allocation used by the register allocator.
91 list<Register> MemberList = regList;
93 // Methods - This member can be used to insert arbitrary code into a generated
94 // register class. The normal usage of this is to overload virtual methods.
97 // isDummyClass - If this is set to true, this register class is not really
98 // part of the target, it is just used for other purposes.
103 //===----------------------------------------------------------------------===//
104 // Instruction set description - These classes correspond to the C++ classes in
105 // the Target/TargetInstrInfo.h file.
109 string Name; // The opcode string for this instruction
110 string Namespace = "";
112 list<Register> Uses = []; // Default to using no non-operand registers
113 list<Register> Defs = []; // Default to modifying no non-operand registers
115 // These bits capture information about the high-level semantics of the
117 bit isReturn = 0; // Is this instruction a return instruction?
118 bit isBranch = 0; // Is this instruction a branch instruction?
119 bit isCall = 0; // Is this instruction a call instruction?
120 bit isTwoAddress = 0; // Is this a two address instruction?
121 bit isTerminator = 0; // Is this part of the terminator for a basic block?
123 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
124 // otherwise, uninitialized.
128 class Expander<dag pattern, list<dag> result> {
129 dag Pattern = pattern;
130 list<dag> Result = result;
134 // InstrInfo - This class should only be instantiated once to provide parameters
135 // which are global to the the target machine.
140 // If the target wants to associate some target-specific information with each
141 // instruction, it should provide these two lists to indicate how to assemble
142 // the target specific information into the 32 bits available.
144 list<string> TSFlagsFields = [];
145 list<int> TSFlagsShifts = [];
149 //===----------------------------------------------------------------------===//
150 // Target - This class contains the "global" target information
153 // CalleeSavedRegisters - As you might guess, this is a list of the callee
154 // saved registers for a target.
155 list<Register> CalleeSavedRegisters = [];
157 // PointerType - Specify the value type to be used to represent pointers in
158 // this target. Typically this is an i32 or i64 type.
159 ValueType PointerType;
161 // InstructionSet - Instruction set description for this target
162 InstrInfo InstructionSet;
166 //===----------------------------------------------------------------------===//
167 // DAG node definitions used by the instruction selector...
169 class DagNodeValType;
170 def DNVT_any : DagNodeValType; // No constraint on tree node
171 def DNVT_void : DagNodeValType; // Tree node always returns void
172 def DNVT_val : DagNodeValType; // A non-void type
173 def DNVT_arg0 : DagNodeValType; // Tree node returns same type as Arg0
174 def DNVT_arg1 : DagNodeValType; // Tree node returns same type as Arg1
175 def DNVT_ptr : DagNodeValType; // The target pointer type
176 def DNVT_i8 : DagNodeValType; // Always have an i8 value
178 class DagNode<DagNodeValType ret, list<DagNodeValType> args> {
179 DagNodeValType RetType = ret;
180 list<DagNodeValType> ArgTypes = args;
184 // BuiltinDagNodes are built into the instruction selector and correspond to
186 class BuiltinDagNode<DagNodeValType Ret, list<DagNodeValType> Args,
187 string Ename> : DagNode<Ret, Args> {
188 let EnumName = Ename;
192 def Void : RegisterClass<isVoid,0,[]> { let isDummyClass = 1; }
193 def set : DagNode<DNVT_void, [DNVT_val, DNVT_arg0]>;
194 def chain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void], "ChainNode">;
195 def blockchain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void],
197 def ChainExpander : Expander<(chain Void, Void), []>;
198 def BlockChainExpander : Expander<(blockchain Void, Void), []>;
202 def imm : BuiltinDagNode<DNVT_val, [], "Constant">;
203 def frameidx : BuiltinDagNode<DNVT_ptr, [], "FrameIndex">;
204 def basicblock : BuiltinDagNode<DNVT_ptr, [], "BasicBlock">;
207 def plus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Plus">;
208 def minus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Minus">;
209 def times : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Times">;
210 def sdiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SDiv">;
211 def udiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "UDiv">;
212 def srem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SRem">;
213 def urem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "URem">;
214 def and : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "And">;
215 def or : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Or">;
216 def xor : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Xor">;
219 def seteq : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetEQ">;
220 def setne : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetNE">;
221 def setlt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLT">;
222 def setle : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLE">;
223 def setgt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGT">;
224 def setge : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGE">;
226 def load : BuiltinDagNode<DNVT_val, [DNVT_ptr], "Load">;
227 //def store : BuiltinDagNode<DNVT_Void, [DNVT_ptr, DNVT_val]>;
230 def ret : BuiltinDagNode<DNVT_void, [DNVT_val], "Ret">;
231 def retvoid : BuiltinDagNode<DNVT_void, [], "RetVoid">;
232 def br : BuiltinDagNode<DNVT_void, [DNVT_ptr], "Br">;
233 def brcond : BuiltinDagNode<DNVT_void, [DNVT_i8, DNVT_ptr, DNVT_ptr],
236 def unspec1 : BuiltinDagNode<DNVT_any , [DNVT_val], "Unspec1">;
237 def unspec2 : BuiltinDagNode<DNVT_any , [DNVT_val, DNVT_val], "Unspec2">;
239 //===----------------------------------------------------------------------===//
240 // DAG nonterminals definitions used by the instruction selector...
242 class Nonterminal<dag pattern> {
243 dag Pattern = pattern;