1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 // Value types - These values correspond to the register types defined in the
19 // ValueTypes.h file. If you update anything here, you must update it there as
22 class ValueType<int size, int value> {
23 string Namespace = "MVT";
28 def OtherVT: ValueType<0 , 0>; // "Other" value
29 def i1 : ValueType<1 , 1>; // One bit boolean value
30 def i8 : ValueType<8 , 2>; // 8-bit integer value
31 def i16 : ValueType<16 , 3>; // 16-bit integer value
32 def i32 : ValueType<32 , 4>; // 32-bit integer value
33 def i64 : ValueType<64 , 5>; // 64-bit integer value
34 def i128 : ValueType<128, 5>; // 128-bit integer value
35 def f32 : ValueType<32 , 7>; // 32-bit floating point value
36 def f64 : ValueType<64 , 8>; // 64-bit floating point value
37 def f80 : ValueType<80 , 9>; // 80-bit floating point value
38 def f128 : ValueType<128, 9>; // 128-bit floating point value
39 def isVoid : ValueType<0 , 11>; // Produces no value
41 //===----------------------------------------------------------------------===//
42 // Register file description - These classes are used to fill in the target
43 // description classes in llvm/Target/MRegisterInfo.h
46 // Register - You should define one instance of this class for each register
47 // in the target machine. String n will become the "name" of the register.
48 class RegisterBase<string n> {
49 string Namespace = "";
52 // SpillSize - If this value is set to a non-zero value, it is the size in
53 // bits of the spill slot required to hold this register. If this value is
54 // set to zero, the information is inferred from any register classes the
55 // register belongs to.
58 // SpillAlignment - This value is used to specify the alignment required for
59 // spilling the register. Like SpillSize, this should only be explicitly
60 // specified if the register is not in a register class.
61 int SpillAlignment = 0;
64 class Register<string n> : RegisterBase<n> {
65 list<RegisterBase> Aliases = [];
68 // RegisterGroup - This can be used to define instances of Register which
69 // need to specify aliases.
70 // List "aliases" specifies which registers are aliased to this one. This
71 // allows the code generator to be careful not to put two values with
72 // overlapping live ranges into registers which alias.
73 class RegisterGroup<string n, list<Register> aliases> : Register<n> {
74 let Aliases = aliases;
77 // RegisterClass - Now that all of the registers are defined, and aliases
78 // between registers are defined, specify which registers belong to which
79 // register classes. This also defines the default allocation order of
80 // registers by register allocators.
82 class RegisterClass<ValueType regType, int alignment, list<Register> regList> {
83 // RegType - Specify the ValueType of the registers in this register class.
84 // Note that all registers in a register class must have the same ValueType.
86 ValueType RegType = regType;
88 // Alignment - Specify the alignment required of the registers when they are
89 // stored or loaded to memory.
91 int Size = RegType.Size;
92 int Alignment = alignment;
94 // MemberList - Specify which registers are in this class. If the
95 // allocation_order_* method are not specified, this also defines the order of
96 // allocation used by the register allocator.
98 list<Register> MemberList = regList;
100 // Methods - This member can be used to insert arbitrary code into a generated
101 // register class. The normal usage of this is to overload virtual methods.
106 //===----------------------------------------------------------------------===//
107 // Instruction set description - These classes correspond to the C++ classes in
108 // the Target/TargetInstrInfo.h file.
111 string Name = ""; // The opcode string for this instruction
112 string Namespace = "";
114 dag OperandList; // An dag containing the MI operand list.
115 string AsmString = ""; // The .s format to print the instruction with.
117 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
118 // otherwise, uninitialized.
121 // The follow state will eventually be inferred automatically from the
122 // instruction pattern.
124 list<Register> Uses = []; // Default to using no non-operand registers
125 list<Register> Defs = []; // Default to modifying no non-operand registers
127 // These bits capture information about the high-level semantics of the
129 bit isReturn = 0; // Is this instruction a return instruction?
130 bit isBranch = 0; // Is this instruction a branch instruction?
131 bit isBarrier = 0; // Can control flow fall through this instruction?
132 bit isCall = 0; // Is this instruction a call instruction?
133 bit isTwoAddress = 0; // Is this a two address instruction?
134 bit isTerminator = 0; // Is this part of the terminator for a basic block?
138 /// ops definition - This is just a simple marker used to identify the operands
139 /// list for an instruction. This should be used like this:
140 /// (ops R32:$dst, R32:$src) or something similar.
143 /// Operand Types - These provide the built-in operand types that may be used
144 /// by a target. Targets can optionally provide their own operand types as
145 /// needed, though this should not be needed for RISC targets.
146 class Operand<ValueType ty> {
147 int NumMIOperands = 1;
149 string PrintMethod = "printOperand";
152 def i1imm : Operand<i1>;
153 def i8imm : Operand<i8>;
154 def i16imm : Operand<i16>;
155 def i32imm : Operand<i32>;
156 def i64imm : Operand<i64>;
158 // InstrInfo - This class should only be instantiated once to provide parameters
159 // which are global to the the target machine.
164 // If the target wants to associate some target-specific information with each
165 // instruction, it should provide these two lists to indicate how to assemble
166 // the target specific information into the 32 bits available.
168 list<string> TSFlagsFields = [];
169 list<int> TSFlagsShifts = [];
172 //===----------------------------------------------------------------------===//
173 // AsmWriter - This class can be implemented by targets that need to customize
174 // the format of the .s file writer.
176 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
177 // on X86 for example).
180 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
181 // class. Generated AsmWriter classes are always prefixed with the target
183 string AsmWriterClassName = "AsmPrinter";
185 // InstFormatName - AsmWriters can specify the name of the format string to
186 // print instructions with.
187 string InstFormatName = "AsmString";
189 def DefaultAsmWriter : AsmWriter;
192 //===----------------------------------------------------------------------===//
193 // Target - This class contains the "global" target information
196 // CalleeSavedRegisters - As you might guess, this is a list of the callee
197 // saved registers for a target.
198 list<Register> CalleeSavedRegisters = [];
200 // PointerType - Specify the value type to be used to represent pointers in
201 // this target. Typically this is an i32 or i64 type.
202 ValueType PointerType;
204 // InstructionSet - Instruction set description for this target.
205 InstrInfo InstructionSet;
207 // AssemblyWriter - The AsmWriter instance to use for this target.
208 AsmWriter AssemblyWriter = DefaultAsmWriter;
212 //===----------------------------------------------------------------------===//
213 // DAG node definitions used by the instruction selector.
215 // NOTE: all of this is a work-in-progress and should be ignored for now.
218 class Expander<dag pattern, list<dag> result> {
219 dag Pattern = pattern;
220 list<dag> Result = result;
223 class DagNodeValType;
224 def DNVT_any : DagNodeValType; // No constraint on tree node
225 def DNVT_void : DagNodeValType; // Tree node always returns void
226 def DNVT_val : DagNodeValType; // A non-void type
227 def DNVT_arg0 : DagNodeValType; // Tree node returns same type as Arg0
228 def DNVT_arg1 : DagNodeValType; // Tree node returns same type as Arg1
229 def DNVT_ptr : DagNodeValType; // The target pointer type
230 def DNVT_i8 : DagNodeValType; // Always have an i8 value
232 class DagNode<DagNodeValType ret, list<DagNodeValType> args> {
233 DagNodeValType RetType = ret;
234 list<DagNodeValType> ArgTypes = args;
238 // BuiltinDagNodes are built into the instruction selector and correspond to
240 class BuiltinDagNode<DagNodeValType Ret, list<DagNodeValType> Args,
241 string Ename> : DagNode<Ret, Args> {
242 let EnumName = Ename;
246 def Void : RegisterClass<isVoid,0,[]> { let isDummyClass = 1; }
247 def set : DagNode<DNVT_void, [DNVT_val, DNVT_arg0]>;
248 def chain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void], "ChainNode">;
249 def blockchain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void],
251 def ChainExpander : Expander<(chain Void, Void), []>;
252 def BlockChainExpander : Expander<(blockchain Void, Void), []>;
256 def imm : BuiltinDagNode<DNVT_val, [], "Constant">;
257 def frameidx : BuiltinDagNode<DNVT_ptr, [], "FrameIndex">;
258 def basicblock : BuiltinDagNode<DNVT_ptr, [], "BasicBlock">;
261 def plus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Plus">;
262 def minus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Minus">;
263 def times : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Times">;
264 def sdiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SDiv">;
265 def udiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "UDiv">;
266 def srem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SRem">;
267 def urem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "URem">;
268 def and : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "And">;
269 def or : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Or">;
270 def xor : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Xor">;
273 def seteq : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetEQ">;
274 def setne : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetNE">;
275 def setlt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLT">;
276 def setle : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLE">;
277 def setgt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGT">;
278 def setge : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGE">;
280 def load : BuiltinDagNode<DNVT_val, [DNVT_ptr], "Load">;
281 //def store : BuiltinDagNode<DNVT_Void, [DNVT_ptr, DNVT_val]>;
284 def ret : BuiltinDagNode<DNVT_void, [DNVT_val], "Ret">;
285 def retvoid : BuiltinDagNode<DNVT_void, [], "RetVoid">;
286 def br : BuiltinDagNode<DNVT_void, [DNVT_ptr], "Br">;
287 def brcond : BuiltinDagNode<DNVT_void, [DNVT_i8, DNVT_ptr, DNVT_ptr],
290 def unspec1 : BuiltinDagNode<DNVT_any , [DNVT_val], "Unspec1">;
291 def unspec2 : BuiltinDagNode<DNVT_any , [DNVT_val, DNVT_val], "Unspec2">;
293 //===----------------------------------------------------------------------===//
294 // DAG nonterminals definitions used by the instruction selector...
296 class Nonterminal<dag pattern> {
297 dag Pattern = pattern;