1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 // Value types - These values correspond to the register types defined in the
19 // ValueTypes.h file. If you update anything here, you must update it there as
22 class ValueType<int size, int value> {
23 string Namespace = "MVT";
28 def OtherVT: ValueType<0 , 0>; // "Other" value
29 def i1 : ValueType<1 , 1>; // One bit boolean value
30 def i8 : ValueType<8 , 2>; // 8-bit integer value
31 def i16 : ValueType<16 , 3>; // 16-bit integer value
32 def i32 : ValueType<32 , 4>; // 32-bit integer value
33 def i64 : ValueType<64 , 5>; // 64-bit integer value
34 def i128 : ValueType<128, 6>; // 128-bit integer value
35 def f32 : ValueType<32 , 7>; // 32-bit floating point value
36 def f64 : ValueType<64 , 8>; // 64-bit floating point value
37 def f80 : ValueType<80 , 9>; // 80-bit floating point value
38 def f128 : ValueType<128, 10>; // 128-bit floating point value
39 def FlagVT : ValueType<0 , 11>; // Condition code or machine flag
40 def isVoid : ValueType<0 , 12>; // Produces no value
41 def Vector : ValueType<0 , 13>; // Abstract vector value
42 def v16i8 : ValueType<128, 14>; // 16 x i8 vector value
43 def v8i16 : ValueType<128, 15>; // 8 x i16 vector value
44 def v4i32 : ValueType<128, 16>; // 4 x i32 vector value
45 def v2i64 : ValueType<128, 17>; // 2 x i64 vector value
46 def v4f32 : ValueType<128, 18>; // 4 x f32 vector value
47 def v2f64 : ValueType<128, 19>; // 2 x f64 vector value
49 //===----------------------------------------------------------------------===//
50 // Register file description - These classes are used to fill in the target
51 // description classes.
53 class RegisterClass; // Forward def
55 // Register - You should define one instance of this class for each register
56 // in the target machine. String n will become the "name" of the register.
57 class Register<string n> {
58 string Namespace = "";
61 // SpillSize - If this value is set to a non-zero value, it is the size in
62 // bits of the spill slot required to hold this register. If this value is
63 // set to zero, the information is inferred from any register classes the
64 // register belongs to.
67 // SpillAlignment - This value is used to specify the alignment required for
68 // spilling the register. Like SpillSize, this should only be explicitly
69 // specified if the register is not in a register class.
70 int SpillAlignment = 0;
72 // Aliases - A list of registers that this register overlaps with. A read or
73 // modification of this register can potentially read or modifie the aliased
76 list<Register> Aliases = [];
79 // RegisterGroup - This can be used to define instances of Register which
80 // need to specify aliases.
81 // List "aliases" specifies which registers are aliased to this one. This
82 // allows the code generator to be careful not to put two values with
83 // overlapping live ranges into registers which alias.
84 class RegisterGroup<string n, list<Register> aliases> : Register<n> {
85 let Aliases = aliases;
88 // RegisterClass - Now that all of the registers are defined, and aliases
89 // between registers are defined, specify which registers belong to which
90 // register classes. This also defines the default allocation order of
91 // registers by register allocators.
93 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
94 list<Register> regList> {
95 string Namespace = namespace;
97 // RegType - Specify the ValueType of the registers in this register class.
98 // Note that all registers in a register class must have the same ValueType.
100 list<ValueType> RegTypes = regTypes;
102 // Size - Specify the spill size in bits of the registers. A default value of
103 // zero lets tablgen pick an appropriate size.
106 // Alignment - Specify the alignment required of the registers when they are
107 // stored or loaded to memory.
109 int Alignment = alignment;
111 // MemberList - Specify which registers are in this class. If the
112 // allocation_order_* method are not specified, this also defines the order of
113 // allocation used by the register allocator.
115 list<Register> MemberList = regList;
117 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
118 // code into a generated register class. The normal usage of this is to
119 // overload virtual methods.
120 code MethodProtos = [{}];
121 code MethodBodies = [{}];
125 //===----------------------------------------------------------------------===//
126 // Pull in the common support for scheduling
128 include "../TargetSchedule.td"
131 //===----------------------------------------------------------------------===//
132 // Instruction set description - These classes correspond to the C++ classes in
133 // the Target/TargetInstrInfo.h file.
136 string Name = ""; // The opcode string for this instruction
137 string Namespace = "";
139 dag OperandList; // An dag containing the MI operand list.
140 string AsmString = ""; // The .s format to print the instruction with.
142 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
143 // otherwise, uninitialized.
146 // The follow state will eventually be inferred automatically from the
147 // instruction pattern.
149 list<Register> Uses = []; // Default to using no non-operand registers
150 list<Register> Defs = []; // Default to modifying no non-operand registers
152 // These bits capture information about the high-level semantics of the
154 bit isReturn = 0; // Is this instruction a return instruction?
155 bit isBranch = 0; // Is this instruction a branch instruction?
156 bit isBarrier = 0; // Can control flow fall through this instruction?
157 bit isCall = 0; // Is this instruction a call instruction?
158 bit isLoad = 0; // Is this instruction a load instruction?
159 bit isStore = 0; // Is this instruction a store instruction?
160 bit isTwoAddress = 0; // Is this a two address instruction?
161 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
162 bit isCommutable = 0; // Is this 3 operand instruction commutable?
163 bit isTerminator = 0; // Is this part of the terminator for a basic block?
164 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
165 bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
166 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
168 InstrItinClass Itinerary; // Execution steps used for scheduling.
172 /// ops definition - This is just a simple marker used to identify the operands
173 /// list for an instruction. This should be used like this:
174 /// (ops R32:$dst, R32:$src) or something similar.
177 /// variable_ops definition - Mark this instruction as taking a variable number
181 /// Operand Types - These provide the built-in operand types that may be used
182 /// by a target. Targets can optionally provide their own operand types as
183 /// needed, though this should not be needed for RISC targets.
184 class Operand<ValueType ty> {
186 string PrintMethod = "printOperand";
187 int NumMIOperands = 1;
188 dag MIOperandInfo = (ops);
191 def i1imm : Operand<i1>;
192 def i8imm : Operand<i8>;
193 def i16imm : Operand<i16>;
194 def i32imm : Operand<i32>;
195 def i64imm : Operand<i64>;
197 // InstrInfo - This class should only be instantiated once to provide parameters
198 // which are global to the the target machine.
203 // If the target wants to associate some target-specific information with each
204 // instruction, it should provide these two lists to indicate how to assemble
205 // the target specific information into the 32 bits available.
207 list<string> TSFlagsFields = [];
208 list<int> TSFlagsShifts = [];
210 // Target can specify its instructions in either big or little-endian formats.
211 // For instance, while both Sparc and PowerPC are big-endian platforms, the
212 // Sparc manual specifies its instructions in the format [31..0] (big), while
213 // PowerPC specifies them using the format [0..31] (little).
214 bit isLittleEndianEncoding = 0;
217 //===----------------------------------------------------------------------===//
218 // AsmWriter - This class can be implemented by targets that need to customize
219 // the format of the .s file writer.
221 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
222 // on X86 for example).
225 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
226 // class. Generated AsmWriter classes are always prefixed with the target
228 string AsmWriterClassName = "AsmPrinter";
230 // InstFormatName - AsmWriters can specify the name of the format string to
231 // print instructions with.
232 string InstFormatName = "AsmString";
234 // Variant - AsmWriters can be of multiple different variants. Variants are
235 // used to support targets that need to emit assembly code in ways that are
236 // mostly the same for different targets, but have minor differences in
237 // syntax. If the asmstring contains {|} characters in them, this integer
238 // will specify which alternative to use. For example "{x|y|z}" with Variant
239 // == 1, will expand to "y".
242 def DefaultAsmWriter : AsmWriter;
245 //===----------------------------------------------------------------------===//
246 // Target - This class contains the "global" target information
249 // CalleeSavedRegisters - As you might guess, this is a list of the callee
250 // saved registers for a target.
251 list<Register> CalleeSavedRegisters = [];
253 // PointerType - Specify the value type to be used to represent pointers in
254 // this target. Typically this is an i32 or i64 type.
255 ValueType PointerType;
257 // InstructionSet - Instruction set description for this target.
258 InstrInfo InstructionSet;
260 // AssemblyWriters - The AsmWriter instances available for this target.
261 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
264 //===----------------------------------------------------------------------===//
265 // SubtargetFeature - A characteristic of the chip set.
267 class SubtargetFeature<string n, string t, string a, string d> {
268 // Name - Feature name. Used by command line (-mattr=) to determine the
269 // appropriate target chip.
273 // Type - Type of attribute to be set by feature.
277 // Attribute - Attribute to be set by feature.
279 string Attribute = a;
281 // Desc - Feature description. Used by command line (-mattr=) to display help
287 //===----------------------------------------------------------------------===//
288 // Processor chip sets - These values represent each of the chip sets supported
289 // by the scheduler. Each Processor definition requires corresponding
290 // instruction itineraries.
292 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
293 // Name - Chip set name. Used by command line (-mcpu=) to determine the
294 // appropriate target chip.
298 // ProcItin - The scheduling information for the target processor.
300 ProcessorItineraries ProcItin = pi;
302 // Features - list of
303 list<SubtargetFeature> Features = f;
306 //===----------------------------------------------------------------------===//
307 // Pull in the common support for DAG isel generation
309 include "../TargetSelectionDAG.td"