1 //===- Target.td - Target Independent TableGen interface --------*- C++ -*-===//
3 // This file defines the target-independent interfaces which should be
4 // implemented by each target which is using a TableGen based code generator.
6 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
11 // Value types - These values correspond to the register types defined in the
12 // ValueTypes.h file. If you update anything here, you must update it there as
15 class ValueType<int size, int value> {
16 string Namespace = "MVT";
21 def i1 : ValueType<1 , 1>; // One bit boolean value
22 def i8 : ValueType<8 , 2>; // 8-bit integer value
23 def i16 : ValueType<16 , 3>; // 16-bit integer value
24 def i32 : ValueType<32 , 4>; // 32-bit integer value
25 def i64 : ValueType<64 , 5>; // 64-bit integer value
26 def i128 : ValueType<128, 5>; // 128-bit integer value
27 def f32 : ValueType<32 , 7>; // 32-bit floating point value
28 def f64 : ValueType<64 , 8>; // 64-bit floating point value
29 def f80 : ValueType<80 , 9>; // 80-bit floating point value
30 def f128 : ValueType<128, 9>; // 128-bit floating point value
31 def isVoid : ValueType<0 , 11>; // Produces no value
33 //===----------------------------------------------------------------------===//
34 // Register file description - These classes are used to fill in the target
35 // description classes in llvm/Target/MRegisterInfo.h
38 // Register - You should define one instance of this class for each register in
39 // the target machine.
42 string Namespace = "";
46 // NamedReg - If the name for the 'def' of the register should not become the
47 // "name" of the register, you can use this to specify a custom name instead.
49 class NamedReg<string n> : Register {
53 // RegisterAliases - You should define instances of this class to indicate which
54 // registers in the register file are aliased together. This allows the code
55 // generator to be careful not to put two values with overlapping live ranges
56 // into registers which alias.
58 class RegisterAliases<Register reg, list<Register> aliases> {
60 list<Register> Aliases = aliases;
63 // RegisterClass - Now that all of the registers are defined, and aliases
64 // between registers are defined, specify which registers belong to which
65 // register classes. This also defines the default allocation order of
66 // registers by register allocators.
68 class RegisterClass<ValueType regType, int alignment, list<Register> regList> {
69 // RegType - Specify the ValueType of the registers in this register class.
70 // Note that all registers in a register class must have the same ValueType.
72 ValueType RegType = regType;
74 // Alignment - Specify the alignment required of the registers when they are
75 // stored or loaded to memory.
77 int Size = RegType.Size;
78 int Alignment = alignment;
80 // MemberList - Specify which registers are in this class. If the
81 // allocation_order_* method are not specified, this also defines the order of
82 // allocation used by the register allocator.
84 list<Register> MemberList = regList;
86 // Methods - This member can be used to insert arbitrary code into a generated
87 // register class. The normal usage of this is to overload virtual methods.
90 // isDummyClass - If this is set to true, this register class is not really
91 // part of the target, it is just used for other purposes.
96 //===----------------------------------------------------------------------===//
97 // Instruction set description - These classes correspond to the C++ classes in
98 // the Target/TargetInstrInfo.h file.
102 string Name; // The opcode string for this instruction
103 string Namespace = "";
105 list<Register> Uses = []; // Default to using no non-operand registers
106 list<Register> Defs = []; // Default to modifying no non-operand registers
108 // These bits capture information about the high-level semantics of the
110 bit isReturn = 0; // Is this instruction a return instruction?
111 bit isBranch = 0; // Is this instruction a branch instruction?
112 bit isCall = 0; // Is this instruction a call instruction?
113 bit isTwoAddress = 0; // Is this a two address instruction?
114 bit isTerminator = 0; // Is this part of the terminator for a basic block?
116 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
117 // otherwise, uninitialized.
121 class Expander<dag pattern, list<dag> result> {
122 dag Pattern = pattern;
123 list<dag> Result = result;
127 // InstrInfo - This class should only be instantiated once to provide parameters
128 // which are global to the the target machine.
133 // If the target wants to associate some target-specific information with each
134 // instruction, it should provide these two lists to indicate how to assemble
135 // the target specific information into the 32 bits available.
137 list<string> TSFlagsFields = [];
138 list<int> TSFlagsShifts = [];
142 //===----------------------------------------------------------------------===//
143 // Target - This class contains the "global" target information
146 // CalleeSavedRegisters - As you might guess, this is a list of the callee
147 // saved registers for a target.
148 list<Register> CalleeSavedRegisters = [];
150 // PointerType - Specify the value type to be used to represent pointers in
151 // this target. Typically this is an i32 or i64 type.
152 ValueType PointerType;
154 // InstructionSet - Instruction set description for this target
155 InstrInfo InstructionSet;
159 //===----------------------------------------------------------------------===//
160 // DAG node definitions used by the instruction selector...
162 class DagNodeValType;
163 def DNVT_any : DagNodeValType; // No constraint on tree node
164 def DNVT_void : DagNodeValType; // Tree node always returns void
165 def DNVT_val : DagNodeValType; // A non-void type
166 def DNVT_arg0 : DagNodeValType; // Tree node returns same type as Arg0
167 def DNVT_arg1 : DagNodeValType; // Tree node returns same type as Arg1
168 def DNVT_ptr : DagNodeValType; // The target pointer type
169 def DNVT_i8 : DagNodeValType; // Always have an i8 value
171 class DagNode<DagNodeValType ret, list<DagNodeValType> args> {
172 DagNodeValType RetType = ret;
173 list<DagNodeValType> ArgTypes = args;
177 // BuiltinDagNodes are built into the instruction selector and correspond to
179 class BuiltinDagNode<DagNodeValType Ret, list<DagNodeValType> Args,
180 string Ename> : DagNode<Ret, Args> {
181 let EnumName = Ename;
185 def Void : RegisterClass<isVoid,0,[]> { let isDummyClass = 1; }
186 def set : DagNode<DNVT_void, [DNVT_val, DNVT_arg0]>;
187 def chain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void], "ChainNode">;
188 def blockchain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void],
190 def ChainExpander : Expander<(chain Void, Void), []>;
191 def BlockChainExpander : Expander<(blockchain Void, Void), []>;
195 def imm : BuiltinDagNode<DNVT_val, [], "Constant">;
196 def frameidx : BuiltinDagNode<DNVT_ptr, [], "FrameIndex">;
197 def basicblock : BuiltinDagNode<DNVT_ptr, [], "BasicBlock">;
200 def plus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Plus">;
201 def minus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Minus">;
202 def times : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Times">;
203 def sdiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SDiv">;
204 def udiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "UDiv">;
205 def srem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SRem">;
206 def urem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "URem">;
207 def and : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "And">;
208 def or : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Or">;
209 def xor : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Xor">;
212 def seteq : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetEQ">;
213 def setne : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetNE">;
214 def setlt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLT">;
215 def setle : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLE">;
216 def setgt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGT">;
217 def setge : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGE">;
219 def load : BuiltinDagNode<DNVT_val, [DNVT_ptr], "Load">;
220 //def store : BuiltinDagNode<DNVT_Void, [DNVT_ptr, DNVT_val]>;
223 def ret : BuiltinDagNode<DNVT_void, [DNVT_val], "Ret">;
224 def retvoid : BuiltinDagNode<DNVT_void, [], "RetVoid">;
225 def br : BuiltinDagNode<DNVT_void, [DNVT_ptr], "Br">;
226 def brcond : BuiltinDagNode<DNVT_void, [DNVT_i8, DNVT_ptr, DNVT_ptr],
229 def unspec1 : BuiltinDagNode<DNVT_any , [DNVT_val], "Unspec1">;
230 def unspec2 : BuiltinDagNode<DNVT_any , [DNVT_val, DNVT_val], "Unspec2">;
232 //===----------------------------------------------------------------------===//
233 // DAG nonterminals definitions used by the instruction selector...
235 class Nonterminal<dag pattern> {
236 dag Pattern = pattern;