1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 // Value types - These values correspond to the register types defined in the
19 // ValueTypes.h file. If you update anything here, you must update it there as
22 class ValueType<int size, int value> {
23 string Namespace = "MVT";
28 def OtherVT: ValueType<0 , 0>; // "Other" value
29 def i1 : ValueType<1 , 1>; // One bit boolean value
30 def i8 : ValueType<8 , 2>; // 8-bit integer value
31 def i16 : ValueType<16 , 3>; // 16-bit integer value
32 def i32 : ValueType<32 , 4>; // 32-bit integer value
33 def i64 : ValueType<64 , 5>; // 64-bit integer value
34 def i128 : ValueType<128, 6>; // 128-bit integer value
35 def f32 : ValueType<32 , 7>; // 32-bit floating point value
36 def f64 : ValueType<64 , 8>; // 64-bit floating point value
37 def f80 : ValueType<80 , 9>; // 80-bit floating point value
38 def f128 : ValueType<128, 10>; // 128-bit floating point value
39 def FlagVT : ValueType<0 , 11>; // Condition code or machine flag
40 def isVoid : ValueType<0 , 12>; // Produces no value
41 def Vector : ValueType<0 , 13>; // Abstract vector value
42 def v8i8 : ValueType<64 , 14>; // 8 x i8 vector value
43 def v4i16 : ValueType<64 , 15>; // 4 x i16 vector value
44 def v2i32 : ValueType<64 , 16>; // 2 x i32 vector value
45 def v16i8 : ValueType<128, 17>; // 16 x i8 vector value
46 def v8i16 : ValueType<128, 18>; // 8 x i16 vector value
47 def v4i32 : ValueType<128, 19>; // 4 x i32 vector value
48 def v2i64 : ValueType<128, 20>; // 2 x i64 vector value
49 def v2f32 : ValueType<64, 21>; // 2 x f32 vector value
50 def v4f32 : ValueType<128, 22>; // 4 x f32 vector value
51 def v2f64 : ValueType<128, 23>; // 2 x f64 vector value
53 //===----------------------------------------------------------------------===//
54 // Register file description - These classes are used to fill in the target
55 // description classes.
57 class RegisterClass; // Forward def
59 // Register - You should define one instance of this class for each register
60 // in the target machine. String n will become the "name" of the register.
61 class Register<string n> {
62 string Namespace = "";
65 // SpillSize - If this value is set to a non-zero value, it is the size in
66 // bits of the spill slot required to hold this register. If this value is
67 // set to zero, the information is inferred from any register classes the
68 // register belongs to.
71 // SpillAlignment - This value is used to specify the alignment required for
72 // spilling the register. Like SpillSize, this should only be explicitly
73 // specified if the register is not in a register class.
74 int SpillAlignment = 0;
76 // Aliases - A list of registers that this register overlaps with. A read or
77 // modification of this register can potentially read or modifie the aliased
80 list<Register> Aliases = [];
83 // RegisterGroup - This can be used to define instances of Register which
84 // need to specify aliases.
85 // List "aliases" specifies which registers are aliased to this one. This
86 // allows the code generator to be careful not to put two values with
87 // overlapping live ranges into registers which alias.
88 class RegisterGroup<string n, list<Register> aliases> : Register<n> {
89 let Aliases = aliases;
92 // RegisterClass - Now that all of the registers are defined, and aliases
93 // between registers are defined, specify which registers belong to which
94 // register classes. This also defines the default allocation order of
95 // registers by register allocators.
97 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
98 list<Register> regList> {
99 string Namespace = namespace;
101 // RegType - Specify the ValueType of the registers in this register class.
102 // Note that all registers in a register class must have the same ValueType.
104 list<ValueType> RegTypes = regTypes;
106 // Size - Specify the spill size in bits of the registers. A default value of
107 // zero lets tablgen pick an appropriate size.
110 // Alignment - Specify the alignment required of the registers when they are
111 // stored or loaded to memory.
113 int Alignment = alignment;
115 // MemberList - Specify which registers are in this class. If the
116 // allocation_order_* method are not specified, this also defines the order of
117 // allocation used by the register allocator.
119 list<Register> MemberList = regList;
121 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
122 // code into a generated register class. The normal usage of this is to
123 // overload virtual methods.
124 code MethodProtos = [{}];
125 code MethodBodies = [{}];
129 //===----------------------------------------------------------------------===//
130 // Pull in the common support for scheduling
132 include "../TargetSchedule.td"
134 class Predicate; // Forward def
136 //===----------------------------------------------------------------------===//
137 // Instruction set description - These classes correspond to the C++ classes in
138 // the Target/TargetInstrInfo.h file.
141 string Name = ""; // The opcode string for this instruction
142 string Namespace = "";
144 dag OperandList; // An dag containing the MI operand list.
145 string AsmString = ""; // The .s format to print the instruction with.
147 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
148 // otherwise, uninitialized.
151 // The follow state will eventually be inferred automatically from the
152 // instruction pattern.
154 list<Register> Uses = []; // Default to using no non-operand registers
155 list<Register> Defs = []; // Default to modifying no non-operand registers
157 // Predicates - List of predicates which will be turned into isel matching
159 list<Predicate> Predicates = [];
161 // These bits capture information about the high-level semantics of the
163 bit isReturn = 0; // Is this instruction a return instruction?
164 bit isBranch = 0; // Is this instruction a branch instruction?
165 bit isBarrier = 0; // Can control flow fall through this instruction?
166 bit isCall = 0; // Is this instruction a call instruction?
167 bit isLoad = 0; // Is this instruction a load instruction?
168 bit isStore = 0; // Is this instruction a store instruction?
169 bit isTwoAddress = 0; // Is this a two address instruction?
170 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
171 bit isCommutable = 0; // Is this 3 operand instruction commutable?
172 bit isTerminator = 0; // Is this part of the terminator for a basic block?
173 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
174 bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
175 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
176 bit noResults = 0; // Does this instruction produce no results?
178 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
181 /// Predicates - These are extra conditionals which are turned into instruction
182 /// selector matching code. Currently each predicate is just a string.
183 class Predicate<string cond> {
184 string CondString = cond;
187 class Requires<list<Predicate> preds> {
188 list<Predicate> Predicates = preds;
191 /// ops definition - This is just a simple marker used to identify the operands
192 /// list for an instruction. This should be used like this:
193 /// (ops R32:$dst, R32:$src) or something similar.
196 /// variable_ops definition - Mark this instruction as taking a variable number
200 /// Operand Types - These provide the built-in operand types that may be used
201 /// by a target. Targets can optionally provide their own operand types as
202 /// needed, though this should not be needed for RISC targets.
203 class Operand<ValueType ty> {
205 string PrintMethod = "printOperand";
206 int NumMIOperands = 1;
207 dag MIOperandInfo = (ops);
210 def i1imm : Operand<i1>;
211 def i8imm : Operand<i8>;
212 def i16imm : Operand<i16>;
213 def i32imm : Operand<i32>;
214 def i64imm : Operand<i64>;
216 // InstrInfo - This class should only be instantiated once to provide parameters
217 // which are global to the the target machine.
220 // If the target wants to associate some target-specific information with each
221 // instruction, it should provide these two lists to indicate how to assemble
222 // the target specific information into the 32 bits available.
224 list<string> TSFlagsFields = [];
225 list<int> TSFlagsShifts = [];
227 // Target can specify its instructions in either big or little-endian formats.
228 // For instance, while both Sparc and PowerPC are big-endian platforms, the
229 // Sparc manual specifies its instructions in the format [31..0] (big), while
230 // PowerPC specifies them using the format [0..31] (little).
231 bit isLittleEndianEncoding = 0;
234 // Standard Instructions.
235 def PHI : Instruction {
236 let OperandList = (ops variable_ops);
237 let AsmString = "PHINODE";
239 def INLINEASM : Instruction {
240 let OperandList = (ops variable_ops);
244 //===----------------------------------------------------------------------===//
245 // AsmWriter - This class can be implemented by targets that need to customize
246 // the format of the .s file writer.
248 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
249 // on X86 for example).
252 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
253 // class. Generated AsmWriter classes are always prefixed with the target
255 string AsmWriterClassName = "AsmPrinter";
257 // InstFormatName - AsmWriters can specify the name of the format string to
258 // print instructions with.
259 string InstFormatName = "AsmString";
261 // Variant - AsmWriters can be of multiple different variants. Variants are
262 // used to support targets that need to emit assembly code in ways that are
263 // mostly the same for different targets, but have minor differences in
264 // syntax. If the asmstring contains {|} characters in them, this integer
265 // will specify which alternative to use. For example "{x|y|z}" with Variant
266 // == 1, will expand to "y".
269 def DefaultAsmWriter : AsmWriter;
272 //===----------------------------------------------------------------------===//
273 // Target - This class contains the "global" target information
276 // CalleeSavedRegisters - As you might guess, this is a list of the callee
277 // saved registers for a target.
278 list<Register> CalleeSavedRegisters = [];
280 // PointerType - Specify the value type to be used to represent pointers in
281 // this target. Typically this is an i32 or i64 type.
282 ValueType PointerType;
284 // InstructionSet - Instruction set description for this target.
285 InstrInfo InstructionSet;
287 // AssemblyWriters - The AsmWriter instances available for this target.
288 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
291 //===----------------------------------------------------------------------===//
292 // SubtargetFeature - A characteristic of the chip set.
294 class SubtargetFeature<string n, string a, string v, string d> {
295 // Name - Feature name. Used by command line (-mattr=) to determine the
296 // appropriate target chip.
300 // Attribute - Attribute to be set by feature.
302 string Attribute = a;
304 // Value - Value the attribute to be set to by feature.
308 // Desc - Feature description. Used by command line (-mattr=) to display help
314 //===----------------------------------------------------------------------===//
315 // Processor chip sets - These values represent each of the chip sets supported
316 // by the scheduler. Each Processor definition requires corresponding
317 // instruction itineraries.
319 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
320 // Name - Chip set name. Used by command line (-mcpu=) to determine the
321 // appropriate target chip.
325 // ProcItin - The scheduling information for the target processor.
327 ProcessorItineraries ProcItin = pi;
329 // Features - list of
330 list<SubtargetFeature> Features = f;
333 //===----------------------------------------------------------------------===//
334 // Pull in the common support for DAG isel generation
336 include "../TargetSelectionDAG.td"