1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
15 // Include all information about LLVM intrinsics.
16 include "llvm/Intrinsics.td"
18 //===----------------------------------------------------------------------===//
19 // Register file description - These classes are used to fill in the target
20 // description classes.
22 class RegisterClass; // Forward def
24 // Register - You should define one instance of this class for each register
25 // in the target machine. String n will become the "name" of the register.
26 class Register<string n> {
27 string Namespace = "";
30 // SpillSize - If this value is set to a non-zero value, it is the size in
31 // bits of the spill slot required to hold this register. If this value is
32 // set to zero, the information is inferred from any register classes the
33 // register belongs to.
36 // SpillAlignment - This value is used to specify the alignment required for
37 // spilling the register. Like SpillSize, this should only be explicitly
38 // specified if the register is not in a register class.
39 int SpillAlignment = 0;
41 // Aliases - A list of registers that this register overlaps with. A read or
42 // modification of this register can potentially read or modify the aliased
44 list<Register> Aliases = [];
46 // SubRegs - A list of registers that are parts of this register. Note these
47 // are "immediate" sub-registers and the registers within the list do not
48 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
50 list<Register> SubRegs = [];
52 // DwarfNumber - Number used internally by gcc/gdb to identify the register.
53 // These values can be determined by locating the <target>.h file in the
54 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
55 // order of these names correspond to the enumeration used by gcc. A value of
56 // -1 indicates that the gcc number is undefined.
60 // RegisterWithSubRegs - This can be used to define instances of Register which
61 // need to specify sub-registers.
62 // List "subregs" specifies which registers are sub-registers to this one. This
63 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
64 // This allows the code generator to be careful not to put two values with
65 // overlapping live ranges into registers which alias.
66 class RegisterWithSubRegs<string n, list<Register> subregs> : Register<n> {
67 let SubRegs = subregs;
70 // SubRegSet - This can be used to define a specific mapping of registers to
71 // indices, for use as named subregs of a particular physical register. Each
72 // register in 'subregs' becomes an addressable subregister at index 'n' of the
73 // corresponding register in 'regs'.
74 class SubRegSet<int n, list<Register> regs, list<Register> subregs> {
77 list<Register> From = regs;
78 list<Register> To = subregs;
81 // RegisterClass - Now that all of the registers are defined, and aliases
82 // between registers are defined, specify which registers belong to which
83 // register classes. This also defines the default allocation order of
84 // registers by register allocators.
86 class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
87 list<Register> regList> {
88 string Namespace = namespace;
90 // RegType - Specify the list ValueType of the registers in this register
91 // class. Note that all registers in a register class must have the same
92 // ValueTypes. This is a list because some targets permit storing different
93 // types in same register, for example vector values with 128-bit total size,
94 // but different count/size of items, like SSE on x86.
96 list<ValueType> RegTypes = regTypes;
98 // Size - Specify the spill size in bits of the registers. A default value of
99 // zero lets tablgen pick an appropriate size.
102 // Alignment - Specify the alignment required of the registers when they are
103 // stored or loaded to memory.
105 int Alignment = alignment;
107 // MemberList - Specify which registers are in this class. If the
108 // allocation_order_* method are not specified, this also defines the order of
109 // allocation used by the register allocator.
111 list<Register> MemberList = regList;
113 // SubClassList - Specify which register classes correspond to subregisters
114 // of this class. The order should be by subregister set index.
115 list<RegisterClass> SubRegClassList = [];
117 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
118 // code into a generated register class. The normal usage of this is to
119 // overload virtual methods.
120 code MethodProtos = [{}];
121 code MethodBodies = [{}];
125 //===----------------------------------------------------------------------===//
126 // DwarfRegNum - This class provides a mapping of the llvm register enumeration
127 // to the register numbering used by gcc and gdb. These values are used by a
128 // debug information writer (ex. DwarfWriter) to describe where values may be
129 // located during execution.
130 class DwarfRegNum<int N> {
131 // DwarfNumber - Number used internally by gcc/gdb to identify the register.
132 // These values can be determined by locating the <target>.h file in the
133 // directory llvmgcc/gcc/config/<target>/ and looking for REGISTER_NAMES. The
134 // order of these names correspond to the enumeration used by gcc. A value of
135 // -1 indicates that the gcc number is undefined.
139 //===----------------------------------------------------------------------===//
140 // Pull in the common support for scheduling
142 include "TargetSchedule.td"
144 class Predicate; // Forward def
146 //===----------------------------------------------------------------------===//
147 // Instruction set description - These classes correspond to the C++ classes in
148 // the Target/TargetInstrInfo.h file.
151 string Name = ""; // The opcode string for this instruction
152 string Namespace = "";
154 dag OutOperandList; // An dag containing the MI def operand list.
155 dag InOperandList; // An dag containing the MI use operand list.
156 string AsmString = ""; // The .s format to print the instruction with.
158 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
159 // otherwise, uninitialized.
162 // The follow state will eventually be inferred automatically from the
163 // instruction pattern.
165 list<Register> Uses = []; // Default to using no non-operand registers
166 list<Register> Defs = []; // Default to modifying no non-operand registers
168 // Predicates - List of predicates which will be turned into isel matching
170 list<Predicate> Predicates = [];
175 // Added complexity passed onto matching pattern.
176 int AddedComplexity = 0;
178 // These bits capture information about the high-level semantics of the
180 bit isReturn = 0; // Is this instruction a return instruction?
181 bit isBranch = 0; // Is this instruction a branch instruction?
182 bit isBarrier = 0; // Can control flow fall through this instruction?
183 bit isCall = 0; // Is this instruction a call instruction?
184 bit isLoad = 0; // Is this instruction a load instruction?
185 bit isStore = 0; // Is this instruction a store instruction?
186 bit isTwoAddress = 0; // Is this a two address instruction?
187 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
188 bit isCommutable = 0; // Is this 3 operand instruction commutable?
189 bit isTerminator = 0; // Is this part of the terminator for a basic block?
190 bit isReMaterializable = 0; // Is this instruction re-materializable?
191 bit isPredicable = 0; // Is this instruction predicable?
192 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
193 bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
194 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
195 bit noResults = 0; // Does this instruction produce no results?
196 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
198 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
200 string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
202 /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
203 /// be encoded into the output machineinstr.
204 string DisableEncoding = "";
207 /// Imp - Helper class for specifying the implicit uses/defs set for an
209 class Imp<list<Register> uses, list<Register> defs> {
210 list<Register> Uses = uses;
211 list<Register> Defs = defs;
214 /// Predicates - These are extra conditionals which are turned into instruction
215 /// selector matching code. Currently each predicate is just a string.
216 class Predicate<string cond> {
217 string CondString = cond;
220 /// NoHonorSignDependentRounding - This predicate is true if support for
221 /// sign-dependent-rounding is not enabled.
222 def NoHonorSignDependentRounding
223 : Predicate<"!HonorSignDependentRoundingFPMath()">;
225 class Requires<list<Predicate> preds> {
226 list<Predicate> Predicates = preds;
229 /// ops definition - This is just a simple marker used to identify the operands
230 /// list for an instruction. outs and ins are identical both syntatically and
231 /// semantically, they are used to define def operands and use operands to
232 /// improve readibility. This should be used like this:
233 /// (outs R32:$dst), (ins R32:$src1, R32:$src2) or something similar.
238 /// variable_ops definition - Mark this instruction as taking a variable number
242 /// ptr_rc definition - Mark this operand as being a pointer value whose
243 /// register class is resolved dynamically via a callback to TargetInstrInfo.
244 /// FIXME: We should probably change this to a class which contain a list of
245 /// flags. But currently we have but one flag.
248 /// Operand Types - These provide the built-in operand types that may be used
249 /// by a target. Targets can optionally provide their own operand types as
250 /// needed, though this should not be needed for RISC targets.
251 class Operand<ValueType ty> {
253 string PrintMethod = "printOperand";
254 dag MIOperandInfo = (ops);
257 def i1imm : Operand<i1>;
258 def i8imm : Operand<i8>;
259 def i16imm : Operand<i16>;
260 def i32imm : Operand<i32>;
261 def i64imm : Operand<i64>;
263 /// zero_reg definition - Special node to stand for the zero register.
267 /// PredicateOperand - This can be used to define a predicate operand for an
268 /// instruction. OpTypes specifies the MIOperandInfo for the operand, and
269 /// AlwaysVal specifies the value of this predicate when set to "always
271 class PredicateOperand<ValueType ty, dag OpTypes, dag AlwaysVal>
273 let MIOperandInfo = OpTypes;
274 dag DefaultOps = AlwaysVal;
277 /// OptionalDefOperand - This is used to define a optional definition operand
278 /// for an instruction. DefaultOps is the register the operand represents if none
279 /// is supplied, e.g. zero_reg.
280 class OptionalDefOperand<ValueType ty, dag OpTypes, dag defaultops>
282 let MIOperandInfo = OpTypes;
283 dag DefaultOps = defaultops;
287 // InstrInfo - This class should only be instantiated once to provide parameters
288 // which are global to the the target machine.
291 // If the target wants to associate some target-specific information with each
292 // instruction, it should provide these two lists to indicate how to assemble
293 // the target specific information into the 32 bits available.
295 list<string> TSFlagsFields = [];
296 list<int> TSFlagsShifts = [];
298 // Target can specify its instructions in either big or little-endian formats.
299 // For instance, while both Sparc and PowerPC are big-endian platforms, the
300 // Sparc manual specifies its instructions in the format [31..0] (big), while
301 // PowerPC specifies them using the format [0..31] (little).
302 bit isLittleEndianEncoding = 0;
305 // Standard Instructions.
306 def PHI : Instruction {
307 let OutOperandList = (ops);
308 let InOperandList = (ops variable_ops);
309 let AsmString = "PHINODE";
310 let Namespace = "TargetInstrInfo";
312 def INLINEASM : Instruction {
313 let OutOperandList = (ops);
314 let InOperandList = (ops variable_ops);
316 let Namespace = "TargetInstrInfo";
318 def LABEL : Instruction {
319 let OutOperandList = (ops);
320 let InOperandList = (ops i32imm:$id);
322 let Namespace = "TargetInstrInfo";
326 //===----------------------------------------------------------------------===//
327 // AsmWriter - This class can be implemented by targets that need to customize
328 // the format of the .s file writer.
330 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
331 // on X86 for example).
334 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
335 // class. Generated AsmWriter classes are always prefixed with the target
337 string AsmWriterClassName = "AsmPrinter";
339 // InstFormatName - AsmWriters can specify the name of the format string to
340 // print instructions with.
341 string InstFormatName = "AsmString";
343 // Variant - AsmWriters can be of multiple different variants. Variants are
344 // used to support targets that need to emit assembly code in ways that are
345 // mostly the same for different targets, but have minor differences in
346 // syntax. If the asmstring contains {|} characters in them, this integer
347 // will specify which alternative to use. For example "{x|y|z}" with Variant
348 // == 1, will expand to "y".
351 def DefaultAsmWriter : AsmWriter;
354 //===----------------------------------------------------------------------===//
355 // Target - This class contains the "global" target information
358 // InstructionSet - Instruction set description for this target.
359 InstrInfo InstructionSet;
361 // AssemblyWriters - The AsmWriter instances available for this target.
362 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
365 //===----------------------------------------------------------------------===//
366 // SubtargetFeature - A characteristic of the chip set.
368 class SubtargetFeature<string n, string a, string v, string d,
369 list<SubtargetFeature> i = []> {
370 // Name - Feature name. Used by command line (-mattr=) to determine the
371 // appropriate target chip.
375 // Attribute - Attribute to be set by feature.
377 string Attribute = a;
379 // Value - Value the attribute to be set to by feature.
383 // Desc - Feature description. Used by command line (-mattr=) to display help
388 // Implies - Features that this feature implies are present. If one of those
389 // features isn't set, then this one shouldn't be set either.
391 list<SubtargetFeature> Implies = i;
394 //===----------------------------------------------------------------------===//
395 // Processor chip sets - These values represent each of the chip sets supported
396 // by the scheduler. Each Processor definition requires corresponding
397 // instruction itineraries.
399 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
400 // Name - Chip set name. Used by command line (-mcpu=) to determine the
401 // appropriate target chip.
405 // ProcItin - The scheduling information for the target processor.
407 ProcessorItineraries ProcItin = pi;
409 // Features - list of
410 list<SubtargetFeature> Features = f;
413 //===----------------------------------------------------------------------===//
414 // Pull in the common support for calling conventions.
416 include "TargetCallingConv.td"
418 //===----------------------------------------------------------------------===//
419 // Pull in the common support for DAG isel generation.
421 include "TargetSelectionDAG.td"