1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 // Value types - These values correspond to the register types defined in the
19 // ValueTypes.h file. If you update anything here, you must update it there as
22 class ValueType<int size, int value> {
23 string Namespace = "MVT";
28 def OtherVT: ValueType<0 , 0>; // "Other" value
29 def i1 : ValueType<1 , 1>; // One bit boolean value
30 def i8 : ValueType<8 , 2>; // 8-bit integer value
31 def i16 : ValueType<16 , 3>; // 16-bit integer value
32 def i32 : ValueType<32 , 4>; // 32-bit integer value
33 def i64 : ValueType<64 , 5>; // 64-bit integer value
34 def i128 : ValueType<128, 5>; // 128-bit integer value
35 def f32 : ValueType<32 , 7>; // 32-bit floating point value
36 def f64 : ValueType<64 , 8>; // 64-bit floating point value
37 def f80 : ValueType<80 , 9>; // 80-bit floating point value
38 def f128 : ValueType<128, 10>; // 128-bit floating point value
39 def FlagVT : ValueType<0 , 11>; // Condition code or machine flag
40 def isVoid : ValueType<0 , 12>; // Produces no value
42 //===----------------------------------------------------------------------===//
43 // Register file description - These classes are used to fill in the target
44 // description classes.
46 class RegisterClass; // Forward def
48 // Register - You should define one instance of this class for each register
49 // in the target machine. String n will become the "name" of the register.
50 class Register<string n> {
51 string Namespace = "";
54 // SpillSize - If this value is set to a non-zero value, it is the size in
55 // bits of the spill slot required to hold this register. If this value is
56 // set to zero, the information is inferred from any register classes the
57 // register belongs to.
60 // SpillAlignment - This value is used to specify the alignment required for
61 // spilling the register. Like SpillSize, this should only be explicitly
62 // specified if the register is not in a register class.
63 int SpillAlignment = 0;
65 // Aliases - A list of registers that this register overlaps with. A read or
66 // modification of this register can potentially read or modifie the aliased
69 list<Register> Aliases = [];
72 // RegisterGroup - This can be used to define instances of Register which
73 // need to specify aliases.
74 // List "aliases" specifies which registers are aliased to this one. This
75 // allows the code generator to be careful not to put two values with
76 // overlapping live ranges into registers which alias.
77 class RegisterGroup<string n, list<Register> aliases> : Register<n> {
78 let Aliases = aliases;
81 // RegisterClass - Now that all of the registers are defined, and aliases
82 // between registers are defined, specify which registers belong to which
83 // register classes. This also defines the default allocation order of
84 // registers by register allocators.
86 class RegisterClass<string namespace, ValueType regType, int alignment,
87 list<Register> regList> {
88 string Namespace = namespace;
90 // RegType - Specify the ValueType of the registers in this register class.
91 // Note that all registers in a register class must have the same ValueType.
93 ValueType RegType = regType;
95 // Alignment - Specify the alignment required of the registers when they are
96 // stored or loaded to memory.
98 int Size = RegType.Size;
99 int Alignment = alignment;
101 // MemberList - Specify which registers are in this class. If the
102 // allocation_order_* method are not specified, this also defines the order of
103 // allocation used by the register allocator.
105 list<Register> MemberList = regList;
107 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
108 // code into a generated register class. The normal usage of this is to
109 // overload virtual methods.
110 code MethodProtos = [{}];
111 code MethodBodies = [{}];
115 //===----------------------------------------------------------------------===//
116 // Instruction set description - These classes correspond to the C++ classes in
117 // the Target/TargetInstrInfo.h file.
120 string Name = ""; // The opcode string for this instruction
121 string Namespace = "";
123 dag OperandList; // An dag containing the MI operand list.
124 string AsmString = ""; // The .s format to print the instruction with.
126 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
127 // otherwise, uninitialized.
130 // The follow state will eventually be inferred automatically from the
131 // instruction pattern.
133 list<Register> Uses = []; // Default to using no non-operand registers
134 list<Register> Defs = []; // Default to modifying no non-operand registers
136 // These bits capture information about the high-level semantics of the
138 bit isReturn = 0; // Is this instruction a return instruction?
139 bit isBranch = 0; // Is this instruction a branch instruction?
140 bit isBarrier = 0; // Can control flow fall through this instruction?
141 bit isCall = 0; // Is this instruction a call instruction?
142 bit isLoad = 0; // Is this instruction a load instruction?
143 bit isStore = 0; // Is this instruction a store instruction?
144 bit isTwoAddress = 0; // Is this a two address instruction?
145 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
146 bit isCommutable = 0; // Is this 3 operand instruction commutable?
147 bit isTerminator = 0; // Is this part of the terminator for a basic block?
148 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
149 bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
153 /// ops definition - This is just a simple marker used to identify the operands
154 /// list for an instruction. This should be used like this:
155 /// (ops R32:$dst, R32:$src) or something similar.
158 /// variable_ops definition - Mark this instruction as taking a variable number
162 /// Operand Types - These provide the built-in operand types that may be used
163 /// by a target. Targets can optionally provide their own operand types as
164 /// needed, though this should not be needed for RISC targets.
165 class Operand<ValueType ty> {
166 int NumMIOperands = 1;
168 string PrintMethod = "printOperand";
171 def i1imm : Operand<i1>;
172 def i8imm : Operand<i8>;
173 def i16imm : Operand<i16>;
174 def i32imm : Operand<i32>;
175 def i64imm : Operand<i64>;
177 // InstrInfo - This class should only be instantiated once to provide parameters
178 // which are global to the the target machine.
183 // If the target wants to associate some target-specific information with each
184 // instruction, it should provide these two lists to indicate how to assemble
185 // the target specific information into the 32 bits available.
187 list<string> TSFlagsFields = [];
188 list<int> TSFlagsShifts = [];
190 // Target can specify its instructions in either big or little-endian formats.
191 // For instance, while both Sparc and PowerPC are big-endian platforms, the
192 // Sparc manual specifies its instructions in the format [31..0] (big), while
193 // PowerPC specifies them using the format [0..31] (little).
194 bit isLittleEndianEncoding = 0;
197 //===----------------------------------------------------------------------===//
198 // AsmWriter - This class can be implemented by targets that need to customize
199 // the format of the .s file writer.
201 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
202 // on X86 for example).
205 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
206 // class. Generated AsmWriter classes are always prefixed with the target
208 string AsmWriterClassName = "AsmPrinter";
210 // InstFormatName - AsmWriters can specify the name of the format string to
211 // print instructions with.
212 string InstFormatName = "AsmString";
214 // Variant - AsmWriters can be of multiple different variants. Variants are
215 // used to support targets that need to emit assembly code in ways that are
216 // mostly the same for different targets, but have minor differences in
217 // syntax. If the asmstring contains {|} characters in them, this integer
218 // will specify which alternative to use. For example "{x|y|z}" with Variant
219 // == 1, will expand to "y".
222 def DefaultAsmWriter : AsmWriter;
225 //===----------------------------------------------------------------------===//
226 // Target - This class contains the "global" target information
229 // CalleeSavedRegisters - As you might guess, this is a list of the callee
230 // saved registers for a target.
231 list<Register> CalleeSavedRegisters = [];
233 // PointerType - Specify the value type to be used to represent pointers in
234 // this target. Typically this is an i32 or i64 type.
235 ValueType PointerType;
237 // InstructionSet - Instruction set description for this target.
238 InstrInfo InstructionSet;
240 // AssemblyWriters - The AsmWriter instances available for this target.
241 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
245 //===----------------------------------------------------------------------===//
246 // DAG node definitions used by the instruction selector.
248 // NOTE: all of this is a work-in-progress and should be ignored for now.
251 class Expander<dag pattern, list<dag> result> {
252 dag Pattern = pattern;
253 list<dag> Result = result;
256 class DagNodeValType;
257 def DNVT_any : DagNodeValType; // No constraint on tree node
258 def DNVT_void : DagNodeValType; // Tree node always returns void
259 def DNVT_val : DagNodeValType; // A non-void type
260 def DNVT_arg0 : DagNodeValType; // Tree node returns same type as Arg0
261 def DNVT_arg1 : DagNodeValType; // Tree node returns same type as Arg1
262 def DNVT_ptr : DagNodeValType; // The target pointer type
263 def DNVT_i8 : DagNodeValType; // Always have an i8 value
265 class DagNode<DagNodeValType ret, list<DagNodeValType> args> {
266 DagNodeValType RetType = ret;
267 list<DagNodeValType> ArgTypes = args;
271 // BuiltinDagNodes are built into the instruction selector and correspond to
273 class BuiltinDagNode<DagNodeValType Ret, list<DagNodeValType> Args,
274 string Ename> : DagNode<Ret, Args> {
275 let EnumName = Ename;
279 def Void : RegisterClass<isVoid,0,[]> { let isDummyClass = 1; }
280 def set : DagNode<DNVT_void, [DNVT_val, DNVT_arg0]>;
281 def chain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void], "ChainNode">;
282 def blockchain : BuiltinDagNode<DNVT_void, [DNVT_void, DNVT_void],
284 def ChainExpander : Expander<(chain Void, Void), []>;
285 def BlockChainExpander : Expander<(blockchain Void, Void), []>;
289 def imm : BuiltinDagNode<DNVT_val, [], "Constant">;
290 def frameidx : BuiltinDagNode<DNVT_ptr, [], "FrameIndex">;
291 def basicblock : BuiltinDagNode<DNVT_ptr, [], "BasicBlock">;
294 def plus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Plus">;
295 def minus : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Minus">;
296 def times : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Times">;
297 def sdiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SDiv">;
298 def udiv : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "UDiv">;
299 def srem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "SRem">;
300 def urem : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "URem">;
301 def and : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "And">;
302 def or : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Or">;
303 def xor : BuiltinDagNode<DNVT_arg0, [DNVT_arg1, DNVT_arg0], "Xor">;
306 def seteq : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetEQ">;
307 def setne : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetNE">;
308 def setlt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLT">;
309 def setle : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetLE">;
310 def setgt : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGT">;
311 def setge : BuiltinDagNode<DNVT_i8 , [DNVT_arg1, DNVT_arg0], "SetGE">;
313 def load : BuiltinDagNode<DNVT_val, [DNVT_ptr], "Load">;
314 //def store : BuiltinDagNode<DNVT_Void, [DNVT_ptr, DNVT_val]>;
317 def ret : BuiltinDagNode<DNVT_void, [DNVT_val], "Ret">;
318 def retvoid : BuiltinDagNode<DNVT_void, [], "RetVoid">;
319 def br : BuiltinDagNode<DNVT_void, [DNVT_ptr], "Br">;
320 def brcond : BuiltinDagNode<DNVT_void, [DNVT_i8, DNVT_ptr, DNVT_ptr],
323 def unspec1 : BuiltinDagNode<DNVT_any , [DNVT_val], "Unspec1">;
324 def unspec2 : BuiltinDagNode<DNVT_any , [DNVT_val, DNVT_val], "Unspec2">;
326 //===----------------------------------------------------------------------===//
327 // DAG nonterminals definitions used by the instruction selector...
329 class Nonterminal<dag pattern> {
330 dag Pattern = pattern;