1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces which should be
11 // implemented by each target which is using a TableGen based code generator.
13 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 // Value types - These values correspond to the register types defined in the
19 // ValueTypes.h file. If you update anything here, you must update it there as
22 class ValueType<int size, int value> {
23 string Namespace = "MVT";
28 def OtherVT: ValueType<0 , 0>; // "Other" value
29 def i1 : ValueType<1 , 1>; // One bit boolean value
30 def i8 : ValueType<8 , 2>; // 8-bit integer value
31 def i16 : ValueType<16 , 3>; // 16-bit integer value
32 def i32 : ValueType<32 , 4>; // 32-bit integer value
33 def i64 : ValueType<64 , 5>; // 64-bit integer value
34 def i128 : ValueType<128, 6>; // 128-bit integer value
35 def f32 : ValueType<32 , 7>; // 32-bit floating point value
36 def f64 : ValueType<64 , 8>; // 64-bit floating point value
37 def f80 : ValueType<80 , 9>; // 80-bit floating point value
38 def f128 : ValueType<128, 10>; // 128-bit floating point value
39 def FlagVT : ValueType<0 , 11>; // Condition code or machine flag
40 def isVoid : ValueType<0 , 12>; // Produces no value
41 def Vector : ValueType<0 , 13>; // Abstract vector type
43 //===----------------------------------------------------------------------===//
44 // Register file description - These classes are used to fill in the target
45 // description classes.
47 class RegisterClass; // Forward def
49 // Register - You should define one instance of this class for each register
50 // in the target machine. String n will become the "name" of the register.
51 class Register<string n> {
52 string Namespace = "";
55 // SpillSize - If this value is set to a non-zero value, it is the size in
56 // bits of the spill slot required to hold this register. If this value is
57 // set to zero, the information is inferred from any register classes the
58 // register belongs to.
61 // SpillAlignment - This value is used to specify the alignment required for
62 // spilling the register. Like SpillSize, this should only be explicitly
63 // specified if the register is not in a register class.
64 int SpillAlignment = 0;
66 // Aliases - A list of registers that this register overlaps with. A read or
67 // modification of this register can potentially read or modifie the aliased
70 list<Register> Aliases = [];
73 // RegisterGroup - This can be used to define instances of Register which
74 // need to specify aliases.
75 // List "aliases" specifies which registers are aliased to this one. This
76 // allows the code generator to be careful not to put two values with
77 // overlapping live ranges into registers which alias.
78 class RegisterGroup<string n, list<Register> aliases> : Register<n> {
79 let Aliases = aliases;
82 // RegisterClass - Now that all of the registers are defined, and aliases
83 // between registers are defined, specify which registers belong to which
84 // register classes. This also defines the default allocation order of
85 // registers by register allocators.
87 class RegisterClass<string namespace, ValueType regType, int alignment,
88 list<Register> regList> {
89 string Namespace = namespace;
91 // RegType - Specify the ValueType of the registers in this register class.
92 // Note that all registers in a register class must have the same ValueType.
94 ValueType RegType = regType;
96 // Alignment - Specify the alignment required of the registers when they are
97 // stored or loaded to memory.
99 int Size = RegType.Size;
100 int Alignment = alignment;
102 // MemberList - Specify which registers are in this class. If the
103 // allocation_order_* method are not specified, this also defines the order of
104 // allocation used by the register allocator.
106 list<Register> MemberList = regList;
108 // MethodProtos/MethodBodies - These members can be used to insert arbitrary
109 // code into a generated register class. The normal usage of this is to
110 // overload virtual methods.
111 code MethodProtos = [{}];
112 code MethodBodies = [{}];
116 //===----------------------------------------------------------------------===//
117 // Pull in the common support for scheduling
119 include "../TargetSchedule.td"
122 //===----------------------------------------------------------------------===//
123 // Instruction set description - These classes correspond to the C++ classes in
124 // the Target/TargetInstrInfo.h file.
127 string Name = ""; // The opcode string for this instruction
128 string Namespace = "";
130 dag OperandList; // An dag containing the MI operand list.
131 string AsmString = ""; // The .s format to print the instruction with.
133 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
134 // otherwise, uninitialized.
137 // The follow state will eventually be inferred automatically from the
138 // instruction pattern.
140 list<Register> Uses = []; // Default to using no non-operand registers
141 list<Register> Defs = []; // Default to modifying no non-operand registers
143 // These bits capture information about the high-level semantics of the
145 bit isReturn = 0; // Is this instruction a return instruction?
146 bit isBranch = 0; // Is this instruction a branch instruction?
147 bit isBarrier = 0; // Can control flow fall through this instruction?
148 bit isCall = 0; // Is this instruction a call instruction?
149 bit isLoad = 0; // Is this instruction a load instruction?
150 bit isStore = 0; // Is this instruction a store instruction?
151 bit isTwoAddress = 0; // Is this a two address instruction?
152 bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
153 bit isCommutable = 0; // Is this 3 operand instruction commutable?
154 bit isTerminator = 0; // Is this part of the terminator for a basic block?
155 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
156 bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
158 InstrItinClass Itinerary; // Execution steps used for scheduling.
162 /// ops definition - This is just a simple marker used to identify the operands
163 /// list for an instruction. This should be used like this:
164 /// (ops R32:$dst, R32:$src) or something similar.
167 /// variable_ops definition - Mark this instruction as taking a variable number
171 /// Operand Types - These provide the built-in operand types that may be used
172 /// by a target. Targets can optionally provide their own operand types as
173 /// needed, though this should not be needed for RISC targets.
174 class Operand<ValueType ty> {
176 string PrintMethod = "printOperand";
177 int NumMIOperands = 1;
178 dag MIOperandInfo = (ops);
181 def i1imm : Operand<i1>;
182 def i8imm : Operand<i8>;
183 def i16imm : Operand<i16>;
184 def i32imm : Operand<i32>;
185 def i64imm : Operand<i64>;
187 // InstrInfo - This class should only be instantiated once to provide parameters
188 // which are global to the the target machine.
193 // If the target wants to associate some target-specific information with each
194 // instruction, it should provide these two lists to indicate how to assemble
195 // the target specific information into the 32 bits available.
197 list<string> TSFlagsFields = [];
198 list<int> TSFlagsShifts = [];
200 // Target can specify its instructions in either big or little-endian formats.
201 // For instance, while both Sparc and PowerPC are big-endian platforms, the
202 // Sparc manual specifies its instructions in the format [31..0] (big), while
203 // PowerPC specifies them using the format [0..31] (little).
204 bit isLittleEndianEncoding = 0;
207 //===----------------------------------------------------------------------===//
208 // AsmWriter - This class can be implemented by targets that need to customize
209 // the format of the .s file writer.
211 // Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
212 // on X86 for example).
215 // AsmWriterClassName - This specifies the suffix to use for the asmwriter
216 // class. Generated AsmWriter classes are always prefixed with the target
218 string AsmWriterClassName = "AsmPrinter";
220 // InstFormatName - AsmWriters can specify the name of the format string to
221 // print instructions with.
222 string InstFormatName = "AsmString";
224 // Variant - AsmWriters can be of multiple different variants. Variants are
225 // used to support targets that need to emit assembly code in ways that are
226 // mostly the same for different targets, but have minor differences in
227 // syntax. If the asmstring contains {|} characters in them, this integer
228 // will specify which alternative to use. For example "{x|y|z}" with Variant
229 // == 1, will expand to "y".
232 def DefaultAsmWriter : AsmWriter;
235 //===----------------------------------------------------------------------===//
236 // Target - This class contains the "global" target information
239 // CalleeSavedRegisters - As you might guess, this is a list of the callee
240 // saved registers for a target.
241 list<Register> CalleeSavedRegisters = [];
243 // PointerType - Specify the value type to be used to represent pointers in
244 // this target. Typically this is an i32 or i64 type.
245 ValueType PointerType;
247 // InstructionSet - Instruction set description for this target.
248 InstrInfo InstructionSet;
250 // AssemblyWriters - The AsmWriter instances available for this target.
251 list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
254 //===----------------------------------------------------------------------===//
255 // SubtargetFeature - A characteristic of the chip set.
257 class SubtargetFeature<string n, string t, string a, string d> {
258 // Name - Feature name. Used by command line (-mattr=) to determine the
259 // appropriate target chip.
263 // Type - Type of attribute to be set by feature.
267 // Attribute - Attribute to be set by feature.
269 string Attribute = a;
271 // Desc - Feature description. Used by command line (-mattr=) to display help
277 //===----------------------------------------------------------------------===//
278 // Processor chip sets - These values represent each of the chip sets supported
279 // by the scheduler. Each Processor definition requires corresponding
280 // instruction itineraries.
282 class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
283 // Name - Chip set name. Used by command line (-mcpu=) to determine the
284 // appropriate target chip.
288 // ProcItin - The scheduling information for the target processor.
290 ProcessorItineraries ProcItin = pi;
292 // Features - list of
293 list<SubtargetFeature> Features = f;
296 //===----------------------------------------------------------------------===//
297 // Pull in the common support for DAG isel generation
299 include "../TargetSelectionDAG.td"