1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetInstrInfo.h"
15 #include "llvm/Target/TargetInstrItineraries.h"
16 #include "llvm/Target/TargetRegisterInfo.h"
17 #include "llvm/CodeGen/SelectionDAGNodes.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/Support/ErrorHandling.h"
23 //===----------------------------------------------------------------------===//
25 //===----------------------------------------------------------------------===//
27 /// getRegClass - Get the register class for the operand, handling resolution
28 /// of "symbolic" pointer register classes etc. If this is not a register
29 /// operand, this returns null.
30 const TargetRegisterClass *
31 TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const {
32 if (isLookupPtrRegClass())
33 return TRI->getPointerRegClass(RegClass);
34 // Instructions like INSERT_SUBREG do not have fixed register classes.
37 // Otherwise just look it up normally.
38 return TRI->getRegClass(RegClass);
41 //===----------------------------------------------------------------------===//
43 //===----------------------------------------------------------------------===//
45 TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
47 : Descriptors(Desc), NumOpcodes(numOpcodes) {
50 TargetInstrInfo::~TargetInstrInfo() {
54 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
55 const MachineInstr *MI) const {
56 if (!ItinData || ItinData->isEmpty())
59 unsigned Class = MI->getDesc().getSchedClass();
60 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
64 // The # of u-ops is dynamically determined. The specific target should
65 // override this function to return the right number.
70 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
71 const MachineInstr *DefMI, unsigned DefIdx,
72 const MachineInstr *UseMI, unsigned UseIdx) const {
73 if (!ItinData || ItinData->isEmpty())
76 unsigned DefClass = DefMI->getDesc().getSchedClass();
77 unsigned UseClass = UseMI->getDesc().getSchedClass();
78 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
82 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
83 SDNode *DefNode, unsigned DefIdx,
84 SDNode *UseNode, unsigned UseIdx) const {
85 if (!ItinData || ItinData->isEmpty())
88 if (!DefNode->isMachineOpcode())
91 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
92 if (!UseNode->isMachineOpcode())
93 return ItinData->getOperandCycle(DefClass, DefIdx);
94 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
95 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
98 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
99 const MachineInstr *MI,
100 unsigned *PredCost) const {
101 if (!ItinData || ItinData->isEmpty())
104 return ItinData->getStageLatency(MI->getDesc().getSchedClass());
107 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
109 if (!ItinData || ItinData->isEmpty())
112 if (!N->isMachineOpcode())
115 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
118 bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData,
119 const MachineInstr *DefMI,
120 unsigned DefIdx) const {
121 if (!ItinData || ItinData->isEmpty())
124 unsigned DefClass = DefMI->getDesc().getSchedClass();
125 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
126 return (DefCycle != -1 && DefCycle <= 1);
129 /// insertNoop - Insert a noop into the instruction stream at the specified
131 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
132 MachineBasicBlock::iterator MI) const {
133 llvm_unreachable("Target didn't implement insertNoop!");
137 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
138 const TargetInstrDesc &TID = MI->getDesc();
139 if (!TID.isTerminator()) return false;
141 // Conditional branch is a special case.
142 if (TID.isBranch() && !TID.isBarrier())
144 if (!TID.isPredicable())
146 return !isPredicated(MI);
150 /// Measure the specified inline asm to determine an approximation of its
152 /// Comments (which run till the next SeparatorChar or newline) do not
153 /// count as an instruction.
154 /// Any other non-whitespace text is considered an instruction, with
155 /// multiple instructions separated by SeparatorChar or newlines.
156 /// Variable-length instructions are not handled here; this function
157 /// may be overloaded in the target code to do that.
158 unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
159 const MCAsmInfo &MAI) const {
162 // Count the number of instructions in the asm.
163 bool atInsnStart = true;
165 for (; *Str; ++Str) {
166 if (*Str == '\n' || *Str == MAI.getSeparatorChar())
168 if (atInsnStart && !std::isspace(*Str)) {
169 Length += MAI.getMaxInstLength();
172 if (atInsnStart && strncmp(Str, MAI.getCommentString(),
173 strlen(MAI.getCommentString())) == 0)