1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetInstrInfo.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCInstrItineraries.h"
18 #include "llvm/Support/ErrorHandling.h"
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 TargetInstrInfo::~TargetInstrInfo() {
29 const TargetRegisterClass*
30 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
31 const TargetRegisterInfo *TRI,
32 const MachineFunction &MF) const {
33 if (OpNum >= MCID.getNumOperands())
36 short RegClass = MCID.OpInfo[OpNum].RegClass;
37 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
38 return TRI->getPointerRegClass(MF, RegClass);
40 // Instructions like INSERT_SUBREG do not have fixed register classes.
44 // Otherwise just look it up normally.
45 return TRI->getRegClass(RegClass);
49 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
50 const MachineInstr *MI) const {
51 if (!ItinData || ItinData->isEmpty())
54 unsigned Class = MI->getDesc().getSchedClass();
55 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
59 // The # of u-ops is dynamically determined. The specific target should
60 // override this function to return the right number.
65 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
66 const MachineInstr *DefMI, unsigned DefIdx,
67 const MachineInstr *UseMI, unsigned UseIdx) const {
68 if (!ItinData || ItinData->isEmpty())
71 unsigned DefClass = DefMI->getDesc().getSchedClass();
72 unsigned UseClass = UseMI->getDesc().getSchedClass();
73 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
76 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
77 const MachineInstr *MI,
78 unsigned *PredCost) const {
79 if (!ItinData || ItinData->isEmpty())
82 return ItinData->getStageLatency(MI->getDesc().getSchedClass());
85 bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData,
86 const MachineInstr *DefMI,
87 unsigned DefIdx) const {
88 if (!ItinData || ItinData->isEmpty())
91 unsigned DefClass = DefMI->getDesc().getSchedClass();
92 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
93 return (DefCycle != -1 && DefCycle <= 1);
96 /// insertNoop - Insert a noop into the instruction stream at the specified
98 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
99 MachineBasicBlock::iterator MI) const {
100 llvm_unreachable("Target didn't implement insertNoop!");
104 /// Measure the specified inline asm to determine an approximation of its
106 /// Comments (which run till the next SeparatorString or newline) do not
107 /// count as an instruction.
108 /// Any other non-whitespace text is considered an instruction, with
109 /// multiple instructions separated by SeparatorString or newlines.
110 /// Variable-length instructions are not handled here; this function
111 /// may be overloaded in the target code to do that.
112 unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
113 const MCAsmInfo &MAI) const {
116 // Count the number of instructions in the asm.
117 bool atInsnStart = true;
119 for (; *Str; ++Str) {
120 if (*Str == '\n' || strncmp(Str, MAI.getSeparatorString(),
121 strlen(MAI.getSeparatorString())) == 0)
123 if (atInsnStart && !std::isspace(*Str)) {
124 Length += MAI.getMaxInstLength();
127 if (atInsnStart && strncmp(Str, MAI.getCommentString(),
128 strlen(MAI.getCommentString())) == 0)