1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetInstrInfo.h"
15 #include "llvm/Target/TargetInstrItineraries.h"
16 #include "llvm/Target/TargetRegisterInfo.h"
17 #include "llvm/CodeGen/SelectionDAGNodes.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/Support/ErrorHandling.h"
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 /// getRegClass - Get the register class for the operand, handling resolution
27 /// of "symbolic" pointer register classes etc. If this is not a register
28 /// operand, this returns null.
29 const TargetRegisterClass *
30 TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const {
31 if (isLookupPtrRegClass())
32 return TRI->getPointerRegClass(RegClass);
33 // Instructions like INSERT_SUBREG do not have fixed register classes.
36 // Otherwise just look it up normally.
37 return TRI->getRegClass(RegClass);
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
44 TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
46 : Descriptors(Desc), NumOpcodes(numOpcodes) {
49 TargetInstrInfo::~TargetInstrInfo() {
53 TargetInstrInfo::getNumMicroOps(const MachineInstr *MI,
54 const InstrItineraryData *ItinData) const {
55 if (!ItinData || ItinData->isEmpty())
58 unsigned Class = MI->getDesc().getSchedClass();
59 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
63 // The # of u-ops is dynamically determined. The specific target should
64 // override this function to return the right number.
69 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
70 const MachineInstr *DefMI, unsigned DefIdx,
71 const MachineInstr *UseMI, unsigned UseIdx) const {
72 if (!ItinData || ItinData->isEmpty())
75 unsigned DefClass = DefMI->getDesc().getSchedClass();
76 unsigned UseClass = UseMI->getDesc().getSchedClass();
77 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
81 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
82 SDNode *DefNode, unsigned DefIdx,
83 SDNode *UseNode, unsigned UseIdx) const {
84 if (!ItinData || ItinData->isEmpty())
87 if (!DefNode->isMachineOpcode())
90 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
91 if (!UseNode->isMachineOpcode())
92 return ItinData->getOperandCycle(DefClass, DefIdx);
93 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
94 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
97 bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData,
98 const MachineInstr *DefMI,
99 unsigned DefIdx) const {
100 if (!ItinData || ItinData->isEmpty())
103 unsigned DefClass = DefMI->getDesc().getSchedClass();
104 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
105 return (DefCycle != -1 && DefCycle <= 1);
108 /// insertNoop - Insert a noop into the instruction stream at the specified
110 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
111 MachineBasicBlock::iterator MI) const {
112 llvm_unreachable("Target didn't implement insertNoop!");
116 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
117 const TargetInstrDesc &TID = MI->getDesc();
118 if (!TID.isTerminator()) return false;
120 // Conditional branch is a special case.
121 if (TID.isBranch() && !TID.isBarrier())
123 if (!TID.isPredicable())
125 return !isPredicated(MI);
129 /// Measure the specified inline asm to determine an approximation of its
131 /// Comments (which run till the next SeparatorChar or newline) do not
132 /// count as an instruction.
133 /// Any other non-whitespace text is considered an instruction, with
134 /// multiple instructions separated by SeparatorChar or newlines.
135 /// Variable-length instructions are not handled here; this function
136 /// may be overloaded in the target code to do that.
137 unsigned TargetInstrInfo::getInlineAsmLength(const char *Str,
138 const MCAsmInfo &MAI) const {
141 // Count the number of instructions in the asm.
142 bool atInsnStart = true;
144 for (; *Str; ++Str) {
145 if (*Str == '\n' || *Str == MAI.getSeparatorChar())
147 if (atInsnStart && !isspace(*Str)) {
148 Length += MAI.getMaxInstLength();
151 if (atInsnStart && strncmp(Str, MAI.getCommentString(),
152 strlen(MAI.getCommentString())) == 0)