1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetInstrInfo.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 #include "llvm/Constant.h"
17 #include "llvm/DerivedTypes.h"
20 TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
22 : Descriptors(Desc), NumOpcodes(numOpcodes) {
25 TargetInstrInfo::~TargetInstrInfo() {
28 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
29 const TargetInstrDesc &TID = MI->getDesc();
30 if (!TID.isTerminator()) return false;
32 // Conditional branch is a special case.
33 if (TID.isBranch() && !TID.isBarrier())
35 if (!TID.isPredicable())
37 return !isPredicated(MI);
40 /// getRegClass - Get the register class for the operand, handling resolution
41 /// of "symbolic" pointer register classes etc. If this is not a register
42 /// operand, this returns null.
43 const TargetRegisterClass *
44 TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const {
45 if (isLookupPtrRegClass())
46 return TRI->getPointerRegClass(RegClass);
47 return TRI->getRegClass(RegClass);
50 /// getInstrOperandRegClass - Return register class of the operand of an
51 /// instruction of the specified TargetInstrDesc.
52 const TargetRegisterClass*
53 llvm::getInstrOperandRegClass(const TargetRegisterInfo *TRI,
54 const TargetInstrDesc &II, unsigned Op) {
55 // FIXME: Should be an assert!
56 if (Op >= II.getNumOperands())
58 return II.OpInfo[Op].getRegClass(TRI);